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Is INT8 Portable? A Cross-Platform Measurement Study of Quantized Inference on Embedded and Automotive Accelerators

Yuyeong Shin

arXiv:2609.16085v1cs.ARcs.LGcs.PF

TL;DR

INT8 quantization is widely assumed to make inference faster at a small accuracy cost and produce a portable model. In a controlled cross-platform study, the authors find that speed, per-input numerical agreement, and vendor-NPU deployment depend on the target; edge-NPU latency also tracks output transfer size.

  • Problem

    The paper tests the assumption that INT8 is faster at a small, bounded accuracy cost and that a model quantized once can be deployed across targets.

    Source: §1 · p. 1

  • Method

    The study compares hardware targets while fixing the model artifact and quantization scales so the target integer kernel or ISA is the variable.

    Source: §3.3 · p. 5

  • Results

    Across hardware classes, INT8 portability fails across speed, numerical agreement, and vendor-NPU deployment; predictions agree 958–965/1000 when targets use different integer kernels.

    Source: §1 · p. 2, §11 · p. 16

  • Takeaways & Limitations

    Re-validate INT8 for each target, use vendor-native quantization for vendor NPUs, and provision accelerators by output and data-movement size.

    Source: §11 · p. 16

    The vendor-NPU comparison is outside the fixed-scale invariance claim because external QDQ was rejected, and power-of-two mitigation was tested on one model and one CPU boundary.

    Source: §5 · p. 8, §10 · p. 16

Abstract

from arXiv · show

Eight-bit integer (INT8) post-training quantization is the default recipe for edge deployment, under a widely held assumption: INT8 makes inference faster at a small, predictable accuracy cost, and a model quantized once can be carried to any target. We test that assumption with a controlled measurement study across seven hardware classes -- ARM and x86 CPUs, a discrete GPU, an NVIDIA Jetson AGX Orin iGPU and its NVDLA cores, and two vendor NPUs (Qualcomm Hexagon HTP, DEEPX DX-M1) -- holding the ONNX artifact and the quantization scales fixed so the integer kernel or ISA is the only free variable. Portability fails on three axes. (1) The sign of the INT8 speedup is set by the CPU's dot-product ISA (ARM dotprod/SDOT, x86 VNNI): cores that have it speed up by up to 2.1x, cores that lack it slow down by 1.7x, for the identical model and runtime. (2) INT8 outputs are not portable, and the rule is an invariance rather than a gradient: FP32 predictions are bit-identical for every pair (1000/1000), while INT8 predictions agree 1000/1000 exactly when two targets share an integer kernel and 958-965/1000 whenever they do not -- independent of whether the boundary is CPU<->CPU or CPU<->accelerator, and invisible to top-1 accuracy, which is preserved. (3) Vendor NPUs own quantization: a bring-your-own QDQ graph fails silently on one NPU (external scales ignored, accuracy 0.75 -> 0.005 while it compiles, profiles and runs without error) and loudly on the other (the compiler refuses the graph), so only the vendor's native path yields a correct engine. We further show that edge-NPU latency regimes are set by output/device-to-host transfer size rather than compute, and locate the transition with a fixed-compute sweep. We release the scripts and 32 reports. "Quantize once, deploy anywhere" is unsafe for embedded and automotive deployment, where per-input determinism and redundancy matter.

1 Introduction

The paper tests the assumption that INT8 is predictably faster, mildly costly, and portable by holding artifacts and quantization scales fixed across seven hardware classes. It finds failures in speed, numerical agreement, and vendor-NPU deployability, alongside an edge-NPU latency regime governed by output movement.

Measurement approach

  • The study holds the model artifact and quantization scales fixed across targets to isolate the target's integer kernel or instruction set.It covers seven hardware classes and three model families.Source: §1 · pp. 1, 3

Speed portability

  • 1.83× and 2.11× speedups on dot-product CPUs contrast with 1.65–1.76× slowdowns on CPUs without the relevant instruction.The comparisons use the identical INT8 model and ONNX Runtime MLAS; the speedup sign depends on the target CPU's accumulate instruction.Source: §1 · pp. 2–3

Numerical portability

  • INT8 predictions agree 1000/1000 when targets share an integer kernel but only 958–965/1000 when they do not, while FP32 remains bit-identical.The disagreement occurs across CPU↔CPU and CPU↔accelerator boundaries and is invisible to top-1 accuracy.Source: §1 · pp. 2–3

Vendor-NPU deployability

  • Vendor NPUs control quantization: Qualcomm silently ignores external QDQ scales, while DEEPX rejects the graph.On Qualcomm, accuracy collapses from 0.75 to 0.005 even though the model compiles, profiles, and runs.Source: §1 · pp. 2–3

Edge-NPU performance

  • On an edge NPU, output and data-movement size set the latency regime; a fixed-compute sweep locates a transition band whose width equals the core count.The device-to-host output transfer, rather than compute, determines whether adding cores helps.Source: §1 · pp. 2–3

Deployment relevance

  • Non-portable INT8 numerics undermine the determinism and cross-module consistency assumed by safety cases and redundant automotive architectures.The authors frame the findings for embedded and automotive systems where per-input agreement matters.Source: §1 · p. 2

2 Background and Related Work

The related work establishes quantization methods, hardware-specific kernels, and several deployability and reproducibility concerns. This study focuses on cross-device behavior under fixed scales, including per-input numerical agreement and output-driven edge-NPU latency.

Quantization foundations

  • Integer-only quantization and its design axes are established prior work; this paper measures existing INT8 behavior across hardware boundaries rather than proposing a new quantization algorithm.The foundations are associated with Jacob et al. [2], Krishnamoorthi [3], and Nagel et al. [4]; symmetric INT8 accuracy and rounding are covered by [6] and [7].Source: §2 · p. 3

Edge and mobile benchmarking

  • Prior edge benchmarks quantize per submission and backend, but do not hold scales fixed across targets or report per-input numerical agreement.The paper identifies fixed-scale numerical portability as the gap its cross-device measurements address.Source: §2 · p. 3

Numerical reproducibility

  • Concurrent work localizes INT8 divergence to epilogue scale application and rounding on one GPU, whereas this study measures prediction disagreement across physical hardware boundaries.Chen [22] studies LLM kernels on one device; this work compares vision and detection models across CPUs, GPU, and vendor NPU with identical ONNX scales and an FP32 control.Source: §2 · p. 4

Vendor NPU toolchains

  • Earlier vendor-toolchain work documents backend accuracy differences, while this study characterizes bring-your-own-QDQ rejection as silent failure or compile refusal.The passage cites MQBench [23], Quant-Trim [34], and vendor-native quantization paths.Source: §2 · p. 4

Accelerator characterization

  • The study extends compute- and memory-bound accelerator analysis with an output-size-driven D2H/PCIe-bound regime on an edge NPU.The Orin DLA is characterized as an INT8-only, CNN-favoring datapath that fragments on transformers; GPU-fallback subgraphs are also reported to serialize parallel accelerator work [41] [43].Source: §2 · p. 4

Automotive compute and redundancy

  • Non-portable INT8 numerics matter to automotive redundancy because cross-module agreement is assumed in functional-safety architectures.The paper connects this motivation to ISO 26262 / ASIL, NVIDIA DRIVE, and heterogeneous AV-SoC scheduling [46].Source: §2 · p. 5

3 Experimental Methodology

The methodology compares representative devices and models while controlling artifacts and scales where possible. It reports relative comparisons within a protocol whose timing and accuracy scope limits absolute claims.

3.1 Hardware matrix

  • Table 1 lists eight targets across seven hardware classes, with one device per class, supporting relative claims about representatives rather than population claims about an ISA.The matrix identifies each target and its role in the study.Source: §3.1 · p. 5, Table 1 · p. 5

3.2 Models and datasets

  • The evaluation includes classification, CNN detection, transformer detection, and 3D BEV models, with accuracy measured on ImageNet and COCO subsets or full sets as specified.Absolute accuracy and latency are not comparable across sections because batch size, resolution, and evaluation subset differ.Source: §3.2 · p. 5

3.3 Controlled-comparison principle

  • Cross-target comparisons fix the model artifact and quantization scales so the target's integer kernel or ISA is the only free variable.When a vendor NPU rejects external QDQ and scales cannot be fixed, the result is treated as a deployment finding rather than a kernel comparison.Source: §3.3 · pp. 5–6

3.4 Measurement protocol and scope

  • Accelerator timings use event timing and CPU timings use wall-clock timing, while numerical agreement counts matching top-1 predictions across a fixed input bundle.Most latencies are single-run p50 without confidence intervals, and some accuracy results use subsets, bounding claims to relative comparisons.Source: §3.4 · p. 6

4 The Speedup Sign Is ISA-Determined (C1)

On the identical ResNet-50 INT8 QDQ model and ONNX Runtime CPU path, INT8 speedup depends on the CPU’s dot-product instruction, not simply on using an integer model.

4 The Speedup Sign Is ISA-Determined (C1)

  • On the identical ResNet-50 INT8 QDQ model and ONNX Runtime CPU (MLAS) path, compared with FP32, two CPUs with dot-product instructions speed up under INT8, while two without them slow down.Source: Figure 1 · p. 6, §4 · pp. 6–7
  • The determinant is the presence of a dot-product/accumulate instruction, because without it INT8 re-quantization and widening overhead is not amortized by a faster inner product.ARM dot-product-equipped cores speed up, while the ARM Cortex-A53 without dot-product slows down.Source: Figure 1 · p. 6, §4 · p. 7

5 INT8 Outputs Are Not Portable (C2) — headline

With fixed model scales, INT8 agreement depends on whether targets share an integer kernel, not on the hardware boundary; FP32 predictions were bit-identical in the measured configurations.

5 INT8 Outputs Are Not Portable (C2) — headline

  • FP32 predictions were bit-identical on every measured platform pair (1000/1000), scoped to the fixed-thread-count, single-reduction-path configuration tested.The paper does not claim FP32 is portable by construction under other parallelization or hardware settings.Source: §5 · p. 7
  • 1000/1000 INT8 predictions agree when targets share an integer kernel, versus 958–965/1000 when they do not, regardless of whether the boundary is CPU↔CPU or CPU↔accelerator.The CPU↔accelerator pair falls within the CPU↔CPU agreement range; the DEEPX row is excluded because scales were not held fixed.Source: Table 3 · p. 7, §5 · pp. 7–8, Figure 2 · p. 8
  • The CPU↔GPU pair disagreed on 39/1000 inputs despite identical QDQ scales, implicating kernel-specific rounding and accumulation rather than scale mismatch or hardware noise.The CPU and TensorRT paths use the same model artifact; their integer kernels differ.Source: §5 · p. 8
  • The DEEPX vendor-NPU comparison is a deployment observation, not evidence for the kernel invariance, because its external QDQ graph is rejected and scales and calibration differ.The reported 939/1000 agreement therefore does not isolate the kernel as the cause.Source: §5 · p. 8
  • INT8 disagreements can be invisible to top-1 accuracy: the Jetson iGPU scored 0.7620 versus its FP32 result while differing from CPU predictions on individual inputs.A standard accuracy-after-quantization report would not reveal the per-input portability failure.Source: §5 · p. 8
  • Unlike concurrent single-GPU kernel comparisons by Chen [22], this study measures divergence across physical devices for vision and detection models against FP32 controls.The paper presents the fleet-level, cross-target comparison as complementary to that prior work.Source: §5 · pp. 8–9
  • Power-of-two scales did not restore cross-kernel agreement: x86↔Pi 5 agreement fell from 958/1000 to 869/1000 with ceil rounding and 919/1000 with nearest rounding.MLAS does not special-case the power-of-two multiplier as a shared exact shift; coarser requantization increased epilogue divergence.Source: §5 · p. 9
  • Heterogeneous automotive redundancy and cross-module consistency checks assume per-input agreement, which the measured INT8 paths do not provide across different integer kernels.The paper reports that this assumption holds under FP32 but not under INT8 across heterogeneous kernels.Source: §5 · p. 9

6 Vendors Own Quantization: Two Failure Modes (C3)

Vendor NPUs do not reliably accept externally quantized QDQ graphs: Qualcomm silently ignores external scales, while DEEPX rejects the graph, and both require their native quantization paths for correct engines.

6 Vendors Own Quantization: Two Failure Modes (C3)

  • Qualcomm Hexagon HTP silently ignored external QDQ scales: the model compiled, profiled, and ran without error, but top-1 fell from 0.75 to 0.005.The HTP-native QDQ path recovered top-1 to 0.735 and ran in 748 µs versus 1052 µs for the external-QDQ engine.Source: §6 · pp. 9–10
  • The DEEPX compiler rejected the externally quantized graph with a hard error and emitted no engine; its native PTQ path compiled and reached top-1 0.7660.The native path supplies FP32 and lets the compiler perform PTQ.Source: §6 · p. 10
  • Both NPUs were correct only through vendor-native quantization, making the accelerator—not the user’s toolchain—the owner of the deployed numerics.Qualcomm fails open with a silently broken running model; DEEPX fails closed by refusing to build.Source: §6 · pp. 9–10

7 Bottleneck Regimes Are Set by Output Size, Not Hardware (C4)

On one PCIe-attached edge NPU, output/D2H size—not compute—tracks latency regime and multicore scaling. A fixed-compute sweep locates a transition band whose width equals the core count.

7 Bottleneck Regimes Are Set by Output Size, Not Hardware (C4)

  • 41.01 fps on three cores for YOLOv5s versus ResNet-50’s 1078.93 fps, a 26.3× gap despite YOLOv5s having the least compute and largest output.The comparison attributes the reversal to moving the larger output across the PCIe Gen2×1 link.Source: §7 · p. 10, Table 4 · p. 10
  • 2.97–2.99× three-core scaling holds below ≈63 KB of output, then declines to 1.00× as output grows with NPU compute fixed.The sweep holds 1-core inference at 2.70 ms across 12 output sizes; Figure 3 plots the transition and Table 5 lists representative points.Source: Figure 3 · p. 11, §7 · p. 11, Table 5 · p. 11
  • The transition spans a band from D2H = compute/N to D2H = compute, with a measured 3.36× width on the three-core device.The thresholds are extrapolated: ≈319 KB for link saturation and ≈1.05 MB for a single inference becoming D2H-bound; the band-width/core-count ratio is bandwidth-independent.Source: §7 · pp. 11–12
  • DETR is host-CPU-compute-bound: its 910.6 ms FP32 transformer stage is 87.9% of runtime, while NPU INT8 takes 41.11 ms, or 4.0%.The four measured stages sum to 1015.96 ms, close to the runtime p50 of 1017.53 ms; the 1036.34 ms harness wall-clock includes about 20 ms of overhead.Source: §7 · p. 12
  • In the compute-bound regime, YOLO26n reaches 91.51 fps versus 8.01 fps on the A76, but those gains disappear when output pushes the NPU into a D2H-bound regime.The NPU’s host-side perf/watt is ×29.29 in the favorable regime; the paper’s design rule is to provision and partition by data movement, not TOPS.Source: §7 · p. 12

8 When INT8 Breaks Down: Transformers and the Granularity Lever (supporting)

DETR exposes a sharp INT8 accuracy collapse and shows that its severity depends on activation handling across quantizers. The results connect activation granularity and calibration to deployment outcomes, while a vendor toolchain avoids collapse by leaving much of the transformer in FP32.

8.1 The collapse, and what does not explain it

  • −42.9% mAP: DETR falls from FP32 0.4207 to INT8 0.2402 on a discrete GPU, with a cross-confirmed −43.8% drop on Jetson.Small-object mAP falls 77–85%; the measurements use different listed device paths and calibration setups.Source: §8.1 · p. 12
  • Leaving all 36 attention-score matmuls in FP recovers only +0.0036 mAP, while either network half alone reproduces most of the full collapse.Three commonly recommended exclusion patterns are no-ops on this graph; the two halves’ losses are strongly sub-additive, pointing to distributed damage rather than one fragile subgraph.Source: §8.1 · pp. 12–13, Table 6 · p. 12
  • SmoothQuant recovers 59.9% of the gap in fake quantization but only about 9% on-device, where the buildable INT8 path quantizes Gemms only.Attention, LayerNorm, and Softmax remain FP16 in that on-device path, so the lever does not reach the dominant residual.Source: §8.1 · p. 13

8.2 A toolchain that declines: no collapse by avoidance

  • The DEEPX path changes DETR mAP from 0.4377 to 0.4385, within noise, by assigning much of the transformer to host CPU FP32 rather than quantizing it.Only the CNN backbone and first encoder self-attention block run on the NPU in INT8; 23.99 MB of FP32 attention state crosses to the host per frame, and the pipeline is host-CPU-bound at about 1.04 s end-to-end.Source: §8.2 · p. 13

8.3 The quantizer does not port either

  • The two vendors’ relative mAP deltas differ by 37.1 points even though DEEPX quantizes strictly more of the graph and loses less.The columns are not comparable in absolute mAP because evaluation subsets, resolutions, and runtimes differ; the comparison is between each pipeline’s FP32-to-INT8 relative delta.Source: Table 7 · p. 13, §8.3 · pp. 13–14
  • A per-tensor MinMax scale uses the largest calibration activation, so an outlier can coarsen quantization for the other activations; EMA damping addresses that effect.The ORT path further calibrates over dynamic input shapes, so its 100 calibration images do not share a common activation geometry.Source: §8.3 · p. 14
  • On Jetson NVDLA v2, INT8 is mandatory and leads CNN perf-per-watt, but the same fallback recipe fragments DETR across DLA and GPU.ResNet-50 gets a clean two-fallback offload; DETR has 326 DLA layers, 404 GPU-fallback layers, and 16 ForeignNodes, running in 398.64 ms versus 13.28 ms.Source: §8.3 · p. 14

9 Methodology Pitfalls and Silent Failures (C8)

The paper identifies evaluation and implementation pitfalls that can produce plausible but misleading quantization results. Subset evaluation, preprocessing, SQNR, and silent execution failures each undermine common single-number conclusions.

9 Methodology Pitfalls and Silent Failures (C8)

  • A 1000-image ImageNet subset overstated top-1 by +9.77 percentage points on average versus full validation, across eight model configurations.The inflation ranged from +8.41 to +10.39 pp, flipped three quantization-delta signs, and changed 5 of 13 significance verdicts.Source: §9 · p. 14
  • Resize/crop choice changed top-1 by −1.07 pp, about 9× the −0.12 pp cost of quantization.The paper therefore treats quantization comparisons as meaningful only with fixed, reported preprocessing.Source: §9 · p. 14
  • Per-layer SQNR had essentially no rank correlation with top-1 delta (Spearman ρ = −0.030 over 21 layers and 50k validation images).These measurements do not support ranking layers by SQNR to guide mixed precision.Source: §9 · p. 14
  • Silent fallbacks and implementation errors produced plausible-looking but wrong outputs or timings, including CPU execution instead of TensorRT and a zero-copy buffer bug.The reported examples also include external QDQ falling back to CPU/FP32, an invalid graph after an apparently successful opset conversion, and a TensorRT wheel lacking the assumed trtexec binary.Source: §9 · pp. 14–15

10 Threats to Validity

The authors bound their claims to controlled relative comparisons, noting limitations in latency measurement, evaluation subsets, device coverage, and toolchain variation. Several threshold and portability findings are specific to the tested hardware, workloads, or measurement setup.

10 Threats to Validity

  • Most latencies are single-run p50 values without confidence intervals, so differences below a few percent are directional rather than claimed.The authors consider sign flips of 1.6–2.1× and regime differences above 20× far outside plausible run-to-run noise.Source: §10 · p. 15
  • Several accuracy and agreement results use subsets; the 958–1000/1000 agreement counts are internally comparable on fixed bundles, not comparable to full-validation absolute accuracy.The study reports relative deltas within controlled comparisons because batch size, resolution, and evaluation subset differ across sections.Source: §10 · p. 15
  • With one unit per hardware class, claims apply to the representative device tested, not to all devices of that class.The authors explicitly avoid generalizing the results to all A76 or x86 systems.Source: §10 · p. 15
  • Runtime versions differ across CPU targets, limiting absolute latency comparisons, but controls show version does not separate INT8 agreement outcomes or the speedup sign.A78AE and x86 both ran ONNX Runtime 1.23.2 yet had opposite INT8 speedup signs; an agreeing pair and a disagreeing pair were both cross-version.Source: §10 · p. 15
  • Some perf-per-watt values use host-side power boundaries because on-board or DLA power could not be isolated.The measurement boundary is reported alongside each affected figure.Source: §10 · p. 15
  • The regime-transition sweep uses synthetic random-weight models for latency characterization only, and vendor-NPU findings cover Qualcomm and DEEPX, not other automotive NPUs.BEV capstone models also use initialization weights and are excluded from accuracy claims; TI and Renesas were unavailable.Source: §10 · pp. 15–16
  • The transition thresholds of ≈319 KB and ≈1.05 MB are linear-fit extrapolations specific in absolute position to the host’s PCIe Gen2×1 link.The structural result—that the transition band’s width equals core count—follows from N cores sharing one D2H link and is bandwidth-independent.Source: §10 · p. 16
  • The power-of-two mitigation result is limited to one model, two rounding modes, and the x86-no-VNNI to A76-SDOT boundary.A different boundary or a kernel pair implementing M = 2k as an exact shift could behave differently; the mechanism attribution is based on output measurements rather than kernel-source inspection.Source: §10 · p. 16

11 Conclusion

Across seven hardware classes, INT8 portability fails in speed, numerical agreement, and deployment; per-target re-validation is the dependable path. The conclusion connects these failures to determinism and data-movement constraints in automotive systems.

11 Conclusion

  • INT8 is not portable across speed, numerical agreement, or deployment: its speedup depends on CPU dot-product ISA, predictions can diverge across targets, and vendor NPUs control quantization.FP32 predictions remain bit-identical, while INT8 agreement follows whether targets share an integer kernel; vendor-native quantization is needed for a correct NPU engine.Source: §11 · p. 16
  • For safety-relevant or redundant automotive compute, do not assume heterogeneous units running the same INT8 model agree per input; FP32 agrees, while INT8 may not.The conclusion recommends per-target re-validation and vendor-native quantization, and provisioning accelerators by output/data-movement size.Source: §11 · p. 16
  • Power-of-two scales did not restore cross-kernel agreement on the tested x86↔A76 pair; per-target re-validation, rather than a scale constraint, remains the dependable path.Whether the mitigation transfers to other boundaries or to kernel pairs sharing an exact power-of-two shift remains open.Source: §11 · p. 16
  • The findings motivate treating inter-module data movement and cross-module INT8 consistency as first-order constraints in heterogeneous automotive compute design.The paper describes follow-on work characterizing a heterogeneous multi-module automotive compute platform.Source: §11 · p. 16
  • The study releases its measurement scripts and 32 HTML reports, with numbered claims mapped to the reports and scripts that produced them.Appendix A provides the claim-to-report mapping.Source: §11 · p. 17

A Claim-to-Artifact Map

The claim-to-artifact map links paper claims to reports and scripts. Its accompanying caveat is that absolute values are batch-1, subset-based, and measured on different paths, so only within-comparison relative relations are valid.

A Claim-to-Artifact Map

  • The map links each claim to its report and supporting scripts, making paper numbers traceable to the runs that produced them.Of 32 released reports, 24 are cited as load-bearing for claims; absolute values are batch-1, subset-based, and measured on different paths.Source: Table 8 · p. 20, A Claim-to-Artifact Map · p. 20
  • Qualcomm HTP’s bring-your-own QDQ path drops accuracy from 0.75 to 0.005, while its native path recovers 0.735.The map identifies the report and scripts associated with the Qualcomm claim.Source: A Claim-to-Artifact Map · p. 21
  • The DEEPX inventory covers three models and two regimes; a 12-point fixed-compute output sweep locates a transition band whose width equals core count.YOLOv5s is reported as 26.3× slower than ResNet-50.Source: A Claim-to-Artifact Map · p. 21
  • In the compute-bound regime, the DEEPX NPU has ×11.42 throughput and ×29.29 perf/W relative to the host CPU.The map identifies the DETR stage-decomposition report and scripts for this comparison.Source: A Claim-to-Artifact Map · p. 21
  • SmoothQuant recovers 59.9% of the gap in the torch fake-quant path, but only ∼9% on-device with Gemm-only INT8 coverage.The map lists separate reports for these two findings.Source: A Claim-to-Artifact Map · p. 21
  • The NVDLA entry reports an INT8-only datapath at 51.29 inf/s/W and DETR fragmentation into 16 ForeignNodes.The associated report and scripts are listed in the map.Source: A Claim-to-Artifact Map · p. 21
  • The reproduction entry reports subset inflation of +9.77 pp, averaged over eight configurations.The claim-to-artifact map identifies the reproduction and real-ImageNet reports.Source: A Claim-to-Artifact Map · p. 21
  • Infrastructure probes found TensorRT EP silently running on CPU and zero-copy output-buffer aliasing collapsing top-1 to 0.0014 without an error.The map lists distinct reports for the TensorRT and output-buffer findings.Source: A Claim-to-Artifact Map · pp. 21–22

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