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EBL: Efficient Broad Learning for Distributed Adaptive Harmonic Analysis

Changhong Li, Georgios Floros, Biswajit Basu, Shreejith Shanker

arXiv:2609.16358v1cs.ARcs.LG

TL;DR

EV charging introduces dynamic harmonic distortion, while BLS-style estimators can be costly to deploy on edge hardware. EBL combines a quantised FPGA estimator with closed-form online adaptation, achieving faster response than the nearest reported FPGA method and lower estimation error after adaptation in real-world scenarios.

  • Problem

    EV charging introduces dynamic harmonic distortion in power grids, while BLS-style models can require more computation and memory than conventional ML models, complicating hardware deployment.

    Source: §I · p. 1

  • Method

    EBL combines a quantised, sparse BLS-style FPGA estimator with a shared feature backbone and task-specific heads adapted through closed-form updates.

    Source: §I · pp. 1–2, §II · p. 2

  • Results

    EBL achieves 17.4× faster response than the nearest FPGA-based method, and in G2V its fifth-order harmonic estimation error is 16.4× lower than FFT.

    Source: C. Online Adaptation Across Operating… · p. 3, D. Latency and Resource Efficiency · p. 4

  • Takeaways & Limitations

    EBL provides half-cycle real-time estimation with asynchronous FFT supervision and online adaptation across multiple harmonic-estimation scenarios.

    Source: §II · p. 2, A. Harmonic Estimation Model · p. 2

Abstract

from arXiv · show

Renewable energy systems and electrified transport have found widespread adoption in recent years. The integration of these non-linear loads, dominated by electric vehicle (EV) charging, however, has introduced severe harmonic distortion into the power grid, impacting the efficiency and lifetime of substation equipment and switchgear in the distribution network. Rapid and high-precision harmonic analysis has hence become a prerequisite for effective harmonic control at the source of injection. This paper proposes an Efficient Broad Learning (EBL) framework for distributed adaptive harmonic estimation. As a quantised FPGA acceleration framework for BLS-style harmonic estimation, it offers high-accuracy estimation with half-cycle input, reconfigurable flexibility enabled by the FPGA implementation, and ultra-low latency, achieving 17.4 $\times$ faster predictions than the nearest reported FPGA method. For harmonic prediction across multi-scenario charging and discharging nodes, the online transfer learning based on a closed-form solution rather than backpropagation in EBL demonstrates rapid adaptability. By exploiting bespoke quantisation and sparsity, the approach consumes 5.9\% of the LUTs on the Zynq Ultrascale+ ZU7EV FPGA, using $\approx$ 82\% of the LUTs required by the state-of-the-art FPGA-accelerated estimator.

I. INTRODUCTION

The paper motivates EBL as an efficient edge approach to harmonic estimation in EV-integrated grids, where timely estimates matter but existing methods can require longer windows or costly computation. EBL combines quantisation and sparsity with FPGA acceleration and closed-form adaptation across estimation scenarios.

I. INTRODUCTION

  • EV charging introduces dynamic nonlinearity and harmonic distortion, making accurate and timely estimation important for harmonic mitigation and adaptive control.The introduction notes that harmonics degrade power quality and accelerate equipment ageing.Source: §I · p. 1
  • Existing FPGA and other edge methods still require longer observation windows, limiting their use in dynamic harmonic-estimation conditions associated with EV charging.The paper also notes that some advanced approaches require higher computational cost or stronger signal assumptions.Source: §I · p. 1
  • Quantisation and sparsity are used to make BLS-style edge harmonic estimation hardware-efficient without sacrificing performance.The paper contrasts this with BLS-style models' higher computation and memory costs, which can make hardware deployment slower or more expensive.Source: §I · p. 1
  • The FPGA implementation targets nanosecond-level estimation latency, and Fig. 1 includes latency cycles across estimation methods.The supplied figure caption identifies the latency comparison but does not report its values.Source: §I · p. 1, Figure 1 · p. 2
  • EBL uses BLS-style fast closed-form solving and dynamic routing between a backbone and task-specific heads to adapt across harmonic-estimation scenarios.The introduction presents this as rapid, low-cost adaptation.Source: §I · p. 2

II. METHODOLOGY AND DESIGN

EBL separates real-time harmonic estimation from slower adaptive learning. A shared feature backbone supports half-cycle inference and multiple scenario-specific regression heads updated using asynchronous FFT supervision.

II. METHODOLOGY AND DESIGN

  • EBL combines a real-time harmonic-estimation accelerator with a non-real-time adaptive-learning component.The two components are shown as separate paths in the framework overview.Source: §II · p. 2
  • A quantised, sparse dataflow accelerator uses a broad feature backbone to estimate harmonics from half a power cycle of input.The framework overview identifies this hardware path as the real-time estimator.Source: §II · p. 2
  • The frozen backbone supplies features to multiple regression heads whose decoupled weights can be updated online using asynchronous long-window FFT supervision.This design supports adaptive deployment across multiple scenarios.Source: §II · p. 2

A. Harmonic Estimation Model

The harmonic-estimation model uses half-cycle waveform inputs for rapid inference, while a longer-window FFT path supplies slower supervision and recalibration. Its BLS-derived frozen feature layers and compressed weights are designed to preserve accuracy with lower deployment cost.

A. Harmonic Estimation Model

  • EBL estimates harmonics from 32 raw waveform samples, or half a cycle, while conventional FFT-based methods require at least one cycle for acceptable accuracy.The half-cycle input lets the learned estimator respond to harmonic events before multi-cycle FFT accumulation completes.Source: A. Harmonic Estimation Model · p. 2
  • A longer-window FFT path provides slower but more reliable supervision and recalibration, separate from the half-cycle real-time inference path.The FFT path is asynchronous; the accelerator uses half-cycle inputs for real-time estimates.Source: A. Harmonic Estimation Model · p. 2
  • The BLS-derived broad feature and enhancement layers remain frozen, while the final head layers are updated through closed-form regression rather than backpropagation.The broad and enhancement layers construct a high-dimensional feature space through random mappings.Source: A. Harmonic Estimation Model · p. 2
  • The model uses 3-bit weight and activation quantisation, 16-bit output quantisation, and 85% unstructured pruning, yielding a theoretical 71× compression ratio against FP32.These settings were selected as the most compressed configuration with no accuracy loss relative to the FP32 model.Source: A. Harmonic Estimation Model · p. 2

B. FPGA Dataflow Accelerator with Multi-head Reuse

The FPGA accelerator maps a sparse shared feature backbone to a streaming dataflow design, then broadcasts its features to reusable task-specific regression heads. Head weights can be loaded and updated online without changing the shared feature computation.

B. FPGA Dataflow Accelerator with Multi-head Reuse

  • FINN transforms the sparse quantised model into a streaming accelerator with a fully unrolled backbone matrix-vector-activation unit.Embedding unstructured sparsity lets the compiler remove corresponding multipliers and adder-tree logic, reducing resource consumption and critical path.Source: B. FPGA Dataflow Accelerator with… · p. 2
  • An AXI Stream Broadcaster replicates the backbone feature stream so multiple regression heads can share features with reduced hardware overhead.The backbone and heads run at a shared pipeline cadence.Source: B. FPGA Dataflow Accelerator with… · p. 2
  • Each reusable regression head has decoupled writable weights that can be dynamically loaded from LUTRAM and updated online during operation.The heads use a common execution schedule and fixed output interval to avoid blocking and pipeline stalls.Source: B. FPGA Dataflow Accelerator with… · p. 2

C. Closed-form Online Adaptation and Dynamic Routing

The paper addresses costly accelerator regeneration for changing harmonic-estimation tasks by updating task heads through closed-form regression. Updated weights can then be reloaded without regenerating the accelerator.

C. Closed-form Online Adaptation and Dynamic Routing

  • Fine-tuning for a different task would otherwise require regenerating the entire accelerator through time-consuming synthesis, placement, and routing.Adaptation is needed for harmonic estimation under varying operating conditions.Source: C. Closed-form Online Adaptation and… · p. 2
  • Task-head weights are updated through closed-form ridge regression, making online retraining more practical without costly backpropagation.The update uses a feature matrix and target matrix, with the regularisation parameter selected on the validation split and shared by task heads.Source: C. Closed-form Online Adaptation and… · p. 3
  • Fine-tuned weights are compiled into .dat files and reloaded into task-head LU-TRAMs, supporting software updates without accelerator regeneration.This supports fine-tuning across deployment scenarios and different regression tasks.Source: C. Closed-form Online Adaptation and… · p. 3

III. EXPERIMENTAL RESULTS

Experiments use both a simulated benchmark scenario and recordings from EV-charging and grid-connected-battery operating modes. The accelerator targets the AMD ZU7EV FPGA.

A. Experimental Setup

  • Scenario A1 provides the simulated benchmark for accuracy comparisons, with 60 Hz fundamental frequency, ±0.5% frequency variation, ±1% harmonic-amplitude variation, and 26 dB Gaussian white noise.The scenario is taken from BLS evaluation for comparison, especially with BLS.Source: A. Experimental Setup · p. 3
  • Real-world current recordings cover EV-charger G2V and V2G modes and grid-connected-battery G2B and B2G modes.Each operating scenario forms a separate recording group for adaptation and validation.Source: A. Experimental Setup · p. 3
  • The accelerator is generated for the AMD ZU7EV FPGA on the ZCU104 development kit, with the backbone frozen during fine-tuning and only regression-head weights updated.Training and hardware compilation use Vivado 2022.2 on a workstation with an NVIDIA RTX A4000 GPU and Intel U7–265K CPU.Source: A. Experimental Setup · p. 3

B. Synthetic Signal Harmonic Estimation

In simulated scenario A1, compressed EBL retains accuracy close to BLS and leads on selected mean and maximum relative-error comparisons. Table I reports error by harmonic order and method.

B. Synthetic Signal Harmonic Estimation

  • For harmonic order k, relative error is defined as 100|Âk − Ak|/max(|Ak|, ϵ).The entries in Table I are percentages.Source: B. Synthetic Signal Harmonic Estimation · p. 3
  • EBL achieves the lowest mean relative errors on the 3rd and 5th harmonics and the lowest maximum relative errors on the 3rd, 5th, and 7th harmonics.These results hold despite 3-bit quantisation and 85% unstructured pruning; EBL preserves accuracy close to original BLS, while FFT and WPT have much larger errors, especially at higher harmonic orders.Source: Table I · p. 3, B. Synthetic Signal Harmonic Estimation · p. 3
  • Table I reports mean and maximum relative error (%) for different estimation methods at each harmonic order.The comparison uses competing-model results recreated from and the proposed EBL under the same input sequence.Source: Table I · p. 3, B. Synthetic Signal Harmonic Estimation · p. 3

C. Online Adaptation Across Operating Scenarios

Across real-world charging and discharging scenarios, EBL generalizes from simulation and estimates harmonic amplitudes with lower error than FFT. Fine-tuning further reduces error, with closed-form regression often improving on the pretrained model.

C. Online Adaptation Across Operating Scenarios

  • EBL generalizes from the simulation-trained setting to real-world scenarios and achieves lower estimation errors than FFT; fine-tuning further reduces its error.The reported outputs evaluate harmonic amplitudes, and the advantage is particularly evident in G2V mode.Source: C. Online Adaptation Across Operating… · p. 3
  • 16.4× lower estimation error than FFT is reported for EBL on the 5th-order harmonic in G2V mode.This is the passage’s example of the advantage in that operating mode.Source: C. Online Adaptation Across Operating… · p. 3
  • In most scenarios, closed-form regression updates perform better than the pretrained model and require fewer online resources by updating only task heads.Figure 3 shows fine-tuning iterations under different scenarios.Source: C. Online Adaptation Across Operating… · p. 3

D. Latency and Resource Efficiency

EBL’s sparse implementation reduces latency and hardware resource use. It outperforms reported harmonic-estimation methods in latency, including the nearest FPGA-based comparator.

D. Latency and Resource Efficiency

  • 70 ns (Prop (s)) is ≈17.4× faster than the nearest FPGA-based harmonic-estimation method, DWPT.Sparse optimisation reduces EBL latency from 82 ns (Prop (d)) to 70 ns (Prop (s)); both EBL implementations have lower latency than the reported methods across deployment devices.Source: Table II · p. 4, D. Latency and Resource Efficiency · p. 4
  • Unstructured sparsity reduces LUT and FF utilisation by 47% and 44%, respectively.Compared with the FPGA DWPT baseline, sparse EBL has superior latency and accuracy while using fewer LUTs and DSPs.Source: Table III · p. 4, D. Latency and Resource Efficiency · p. 4
  • EBL preserves BLS’s short input window, high accuracy, and rapid closed-form fine-tuning while reducing resource use and latency for edge deployment.The latency comparison concerns different methods and deployment platforms, while the resource comparison includes traditional FPGA approaches and dense and sparse EBL versions.Source: D. Latency and Resource Efficiency · p. 4, Table II · p. 4, Table III · p. 4

IV. CONCLUSION

The conclusion presents EBL as a quantised FPGA implementation of a BLS-style estimator for distributed, adaptive harmonic estimation. It reports faster response with lower resource consumption and identifies harmonic-control parameter prediction as future work.

IV. CONCLUSION

  • EBL is a quantised FPGA implementation of a BLS-style edge harmonic estimator for distributed, adaptive harmonic estimation.It adapts to different estimation scenarios through efficient closed-form updates.Source: §IV · p. 4
  • EBL achieves a 17.4× faster response with significantly lower LUT and DSP consumption than conventional edge deployment schemes.Source: §IV · p. 4
  • Future work will extend EBL to harmonic-control strategy parameter prediction for real-time harmonic optimisation.Source: §IV · p. 4
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