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FINNAS: FINN-Guided Hardware-Aware NAS and Pruning for FPGA Jet Substructure Classification
Eva Chauffour, Changhong Li, Georgios Floros, Shreejith Shanker
TL;DR
Repeated synthesis makes it costly to identify efficient QNN designs for FPGA inference, while conventional FINN DSE and prior NAS approaches leave gaps in architecture, precision, or in-search hardware-cost exploration. FINNAS evolves MLP topology and precision using proxy accuracy and FINN-estimated LUT and latency costs, then retrains and prunes finalists. On JSC, a compact design improves accuracy over a dense FINN baseline while reducing LUT usage and latency.
Problem
Extensive synthesis makes hardware-aware design-space exploration costly, while conventional FINN DSE focuses on predefined dense QNNs and NASH evaluates hardware costs after architecture search.
Source: §II · p. 2Method
FINNAS evolves quantised MLP topology and global precision settings using proxy validation accuracy and FINN-estimated LUT usage and latency, then retrains and prunes selected finalists.
Source: §I · p. 1, §II · p. 2Results
8.5× LUT usage reduction and 1.7× latency reduction, with accuracy improving from 73.78% to 74.36%, compared with the dense FINN baseline.
Source: B. Comparison with Prior Work · p. 4Takeaways & Limitations
On the JSC task, FINNAS extends the performance frontier of the end-to-end FINN design framework, and unstructured pruning reduces LUT and FF usage across synthesised finalists.
Source: §IV · p. 4, B. Comparison with Prior Work · p. 4
Abstract
from arXiv · showhide
FPGAs are well suited to deploying quantised neural networks (QNNs) under strict accuracy, latency, and resource constraints; however, identifying efficient model-accelerator combinations commonly requires extensive manual design-space exploration and repeated hardware synthesis. This paper presents FINNAS, a FINN-guided hardware-aware evolutionary neural architecture search framework. FINNAS jointly searches quantised MLP depth, width, and global precision settings, and ranks candidates using proxy validation accuracy together with FINN-estimated LUT usage and latency under a fully parallel mapping. Selected finalists are fully retrained, subjected to post-search unstructured pruning, and validated using RTL simulation and Vivado out-of-context synthesis. On the CERNBox jet substructure classification task, the searched implementations expose competitive accuracy-resource trade-offs. Compared with a manually optimised dense FINN accelerator, a compact FINNAS design improves accuracy from 73.78\% to 74.36\%, while reducing LUT usage by \(8.5\times\) and RTL-simulation latency by \(1.77\times\). Unstructured pruning further provides consistent LUT and FF reductions across the fully parallel finalists.
I. INTRODUCTION
Low-latency FPGA inference is important for jet substructure classification, but existing deployment flows leave architecture-level exploration limited or hardware-cost feedback outside the search. FINNAS searches MLP topology and precision using accuracy and FINN-estimated hardware costs, with reported gains over a dense FINN baseline.
I. INTRODUCTION
- The HLF CERNBox JSC task represents each event using 16 high-level input features and commonly evaluates compact fully connected classifiers.It is presented as a benchmark for real-time FPGA inference.Source: §I · p. 1
- Specialised LUT-mapped FPGA accelerators can achieve high accuracy with limited resource use, but typically require specialised mappings and more complex implementation processes.Source: §I · p. 1
- Conventional FINN DSE mainly explores heuristic folding for predefined dense QNNs, while NASH evaluates FINN-derived resource and latency costs after architecture search.NASH also searches under predefined bit-width settings.Source: §I · p. 1
- FINNAS incorporates proxy validation accuracy and FINN-estimated LUT usage and latency into evolutionary search over quantised MLP topology and precision settings, followed by post-search unstructured pruning.Source: §I · p. 1
- FINNAS achieves higher accuracy and lower latency with up to an 8.5× LUT usage reduction relative to the hand-optimised dense FINN baseline.The case study is the JSC task.Source: §I · p. 1
II. METHODOLOGY AND DESIGN
Hardware performance depends on how a QNN is mapped to the target FPGA, making extensive synthesis-based exploration costly. FINNAS uses evolutionary architecture and precision search with FINN-derived estimates to narrow candidates before final hardware evaluation.
II. METHODOLOGY AND DESIGN
- Figure 1 compares the FINNAS workflow with conventional FPGA design-space exploration.Source: §II · p. 1, Figure 1 · p. 2
- Repeated synthesis of model variations makes conventional hardware-aware design-space exploration expensive.Hardware characteristics depend on how a network is mapped to the target FPGA.Source: §II · p. 2
- FINNAS uses evolutionary search over network architectures and quantisation bit-widths, incorporating FINN-derived hardware estimates to guide candidate evaluation without synthesising every architecture.Selected finalists are fully retrained, pruned, fine-tuned, and evaluated through RTL simulation and OOC synthesis.Source: §II · p. 2
A. Hardware-Aware Evolutionary Search
FINNAS evaluates discrete MLP architecture and precision candidates using proxy accuracy and FINN hardware estimates, then evolves and ranks candidates under hardware budgets.
A. Hardware-Aware Evolutionary Search
- The search uses an evolutionary algorithm rather than NASH’s differentiable strategy, matching the discrete architectural and quantisation variables considered.Candidate fitness uses proxy training and FINN hardware-estimate reports.Source: A. Hardware-Aware Evolutionary Search · p. 2
- Each candidate encodes ordered hidden-layer widths and four global precision fields, then receives 16 epochs of proxy training to obtain validation accuracy.Initial values come from finite sets, with repairs enforcing the stated cross-field quantisation constraints.Source: A. Hardware-Aware Evolutionary Search · p. 2
- FINN estimates candidate LUT usage and latency without OOC synthesis or RTL simulation, using the same fully parallel mapping for every candidate.For each fully connected layer, SIMD = Nin and PE = Nout.Source: A. Hardware-Aware Evolutionary Search · p. 2
- The reward combines estimated accuracy and hardware metrics, with LUT and latency budgets controlling penalties for candidates that exceed either budget.Candidates within budget receive no extra reward for further reducing that metric, allowing accuracy to drive selection in the feasible region.Source: A. Hardware-Aware Evolutionary Search · p. 2
- Each generation ranks candidates, retains elites, selects parents by tournament, and varies widths, layer counts, and quantisation through crossover and mutation.Repair, random candidate injection, duplicate removal, and cached fitness support exploration; the five highest-ranked archived architectures become finalists after Ngen generations.Source: A. Hardware-Aware Evolutionary Search · pp. 2–3
B. Finalist Training and Pruning
Finalists are retrained as dense baselines, then subjected to global magnitude pruning and conditional fine-tuning before held-out testing.
B. Finalist Training and Pruning
- Finalists receive up to 500 training epochs with early stopping, then global magnitude pruning at multiple sparsity targets and held-out testing.Pruning zeros weights below a global threshold without changing tensor shapes; fine-tuning runs for up to 100 epochs if raw accuracy drops beyond ε, with masks preserving pruned weights.Source: B. Finalist Training and Pruning · p. 3
A. Experimental Setup
FINNAS was evaluated on a Virtex UltraScale+ VU9P using Vivado OOC synthesis and RTL simulation. Proxy estimates preserved candidate rankings despite substantial absolute error, while avoiding repeated synthesis during search.
A. Experimental Setup
- Vivado 2022.2 OOC synthesis and RTL simulation targeted a Virtex UltraScale+ xcvu9p-flgb2104-2-i with Flow_PerfOptimized_high.The workstation used an NVIDIA RTX 5070 Ti GPU and AMD Ryzen 5 9600X CPU.Source: A. Experimental Setup · p. 3
- A single 500-candidate NAS run took around six hours, versus at least 40 serial hours to OOC-synthesise those candidates.The synthesis estimate uses the shortest observed runtime, approximately five minutes per design.Source: A. Experimental Setup · p. 3
- For 20 dense finalists, estimated versus synthesised LUT usage had Spearman ρ = 0.854, and estimated versus RTL cycle latency had ρ = 0.781.LUT usage was systematically overestimated and latency represented only crudely, but the estimates preserved enough relative ordering to guide candidate ranking.Source: A. Experimental Setup · p. 3
- The reported visuals cover accuracy–LUT trade-offs for HLF JSC implementations and comparisons of FINNAS with prior implementations and FINN baselines.Fig. 2 labels selected FINNAS finalists A–E and also shows additional NAS candidates and pruned FINN variants.Source: Figure 2 · p. 3, Table II · p. 3
B. Comparison with Prior Work
FINNAS is compared with specialized FPGA accelerators and dense or sparse FINN implementations on HLF JSC. The searched designs offer accuracy-resource trade-offs, while unstructured pruning reduces hardware use with accuracy and timing effects that vary by design.
B. Comparison with Prior Work
- The comparison covers prior task-specific FPGA accelerators, a representative dense FINN implementation, and its sparse FINN variants.The prior-work baselines use method-specific flows, often with specialized LUT-based mappings, while the FINN baseline and Designs A–E use the general FINN dataflow toolchain.Source: B. Comparison with Prior Work · p. 3
- Designs A–E came from searches with LUT budgets of 160, 150, 100, 70, and 100k, respectively, using different global precision settings and selected USP levels.Their hidden-layer topologies and selected pruning levels are listed in Table II.Source: B. Comparison with Prior Work · p. 3
- Design A achieved 75.03% accuracy using 21.4k LUTs, while compact Designs D and E exceeded 74% accuracy using 8.1k and 6.8k LUTs.Design C had the lowest latency among synthesised designs exceeding 74% accuracy; Design B was the highest-accuracy selected design satisfying the 2 ns timing constraint.Source: B. Comparison with Prior Work · p. 4
- Across synthesised finalists, 30%, 50%, and 70% USP reduced average LUT usage by 14.7%, 28.6%, and 39.8%, and FF usage by 17.2%, 26.9%, and 41.4%.Pruning generally trades accuracy for resource savings in larger MLPs, while some compact models maintain or slightly improve accuracy; Fmax improved for all five reported designs, enabling timing closure for A, B, D, and E.Source: B. Comparison with Prior Work · p. 4
- Design E reduces LUT usage by 8.5× and latency by 1.7× versus the dense FINN baseline, while improving accuracy from 73.78% to 74.36%.FINNAS also maintains competitive accuracy at moderate and low LUT usage compared with specialized FPGA implementations.Source: B. Comparison with Prior Work · p. 4
IV. CONCLUSION
FINNAS searches QNN architectures and bit widths with hardware performance in view. On JSC, it improves the accuracy-resource trade-off against a hand-optimised dense FINN accelerator; future work will add sparse patterns and inter-layer optimisation.
IV. CONCLUSION
- FINNAS performs hardware-aware architecture and bit-width search for QNNs to co-optimise accuracy and hardware performance.Source: §IV · p. 4
- Against a hand-optimised dense FINN accelerator on JSC, the proposed design reduces LUT usage by up to 8.5× and latency by 1.7× while achieving higher accuracy.Source: §IV · p. 4
- Future work will investigate sparse patterns in the search space and inter-layer optimisation in the automated design flow.Source: §IV · p. 4