REQAP: Resilient Weight Packing and Quantization for Edge DNN Acceleration

Mahdi Taheri; Samira Nazari; Mubassher Ansari; Ali Azarpeyvand; Mohsen Afsharchi; Maksim Jenihhin; Christian Herglotz

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REQAP: Resilient Weight Packing and Quantization for Edge DNN Acceleration

Mahdi Taheri, Samira Nazari, Mubassher Ansari, Ali Azarpeyvand, Mohsen Afsharchi, Maksim Jenihhin, Christian Herglotz

arXiv:2609.17555v1Jul 20, 2026cs.ARcs.AIcs.LG

TL;DR

Edge DNN deployment requires compression without sacrificing reliability under hardware faults, while existing methods leave these objectives largely separate. The paper co-designs sensitivity-driven mixed precision, deterministic SWAR register packing, and selective MSB protection for systolic arrays. Across AlexNet, VGG-11, and ResNet-18, the framework reports up to 62% memory savings, up to 56% fewer MAC operations, and improved fault-injection resilience.

Problem
Existing quantization, packing, and fault-protection methods largely operate independently, leaving their joint optimization for reliable, efficient edge DNN acceleration underexplored.
Method
The framework combines sensitivity-driven layer-wise quantization, symmetric weight–activation precision, compile-time Safe-FFD register packing, and selective MSB replication for TMR-style protection.
Results
Across AlexNet, VGG-11, and ResNet-18, evaluations report up to 62% memory savings and significant fault-resilience improvements, while packing reduces MAC operations by up to 56%.
Takeaways & Limitations
The integrated framework balances memory efficiency, execution efficiency, numerical correctness, and fault resilience without hardware modifications.

Abstract

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Efficient deployment of Deep Neural Networks (DNNs) on edge accelerators requires aggressive model compression while maintaining reliability in fault-prone hardware environments. This paper presents a reliability-aware quantized weight packing methodology for systolic-array-based DNN accelerators. A sensitivity-driven mixed-precision quantization framework assigns layer-wise bit-widths according to accuracy impact while enforcing symmetric precision between weights and activations. A deterministic register-level packing strategy consolidates multiple heterogeneous operand pairs into fixed-width register words, enabling SIMD-within-a-register (SWAR) style parallel execution that reduces both memory footprint and execution cycles. To improve resilience against hardware faults, selective bit-level protection replicates the most significant bits (MSBs) of critical layers into unused register space, achieving TMR-style protection with minimal overhead. A systolic-array simulation framework is developed to evaluate the proposed packing and fault-tolerance mechanisms under realistic execution conditions. Simulations in AlexNet, VGG-11, and ResNet-18 demonstrate up to 62% memory reduction and up to 56% reduction in Multiply-Accumulate (MAC) operations, while significantly improving accuracy resilience under fault injection compared to baseline and fully protected models.

I. INTRODUCTION

Edge DNN accelerators need compression and fault tolerance, but existing methods largely optimize these concerns separately. The paper integrates mixed-precision quantization, deterministic register packing, and selective protection for systolic-array inference.

I. INTRODUCTION: Hardware faults threaten edge DNN inference, while ECC and redundancy can impose substantial memory, area, and energy overhead.Relevant fault sources include voltage scaling, radiation, and manufacturing variability.
I. INTRODUCTION: Existing approaches optimize quantization, register packing, and reliability largely independently, leaving their joint optimization underexplored.This separation also limits use of register slack for embedded fault protection.
I. INTRODUCTION: The proposed methodology co-optimizes sensitivity-driven mixed-precision quantization, deterministic register packing, and selective fault protection for systolic-array accelerators.The framework includes a simulation environment for execution efficiency and reliability under realistic fault conditions.
I. INTRODUCTION: Selective bit-level protection replicates sensitive-layer MSBs in unused register space to provide TMR-style fault masking with minimal memory overhead.The design targets protection through register slack rather than uniform redundancy.
I. INTRODUCTION: Safe-FFD packs heterogeneous-precision operand pairs into fixed-width registers at compile time, enabling SWAR execution without hardware modification.The approach is evaluated in a systolic-array simulation framework modeling packing, execution, and fault injection.

II. PROPOSED METHODOLOGY

The methodology combines SIMD register-level packing with selective redundancy to improve efficiency and resilience. Safe-FFD deterministically packs matched weight–activation pairs while enforcing capacity and overflow safety.

II. PROPOSED METHODOLOGY: The framework combines SIMD register-level packing with selective bit-level redundancy to balance performance, memory efficiency, and fault resilience.Packing is performed for systolic-array-based DNN acceleration.
II. PROPOSED METHODOLOGY: Symmetric precision enforces bits(Wi) = bits(Ai) = bi for corresponding weights and activations, ensuring deterministic packing.The packing constraint is defined over register width R and the slots in each word.
II. PROPOSED METHODOLOGY: Each weight–activation pair uses slot cost ϕi = 2bi, and Safe-FFD inserts sorted slots into the first feasible word or opens a new word.No operand crosses a register boundary.
II. PROPOSED METHODOLOGY: Packing density dj counts operand pairs per word, while unused word bits form slack and overflow constraints keep accumulation representable.These constraints govern safe use of fixed-width registers.
II. PROPOSED METHODOLOGY: Safe-FFD packs heterogeneous operand pairs into fixed-width register words, reducing iteration depth from K slots to Keff = |J| words.Lower iteration depth reduces memory accesses and cycles proportionally to average packing density.

B. Sensitivity-Based Layer Profiling

Layer sensitivity profiling measures accuracy loss from candidate quantization widths and uses a greedy search to balance accuracy and packing density. Higher precision is retained for critical layers while resilient layers are compressed more aggressively.

B. Sensitivity-Based Layer Profiling: Layer sensitivity is measured as accuracy drop relative to full precision when only that layer is quantized at a candidate bit-width.The reference is AccREF, while AccQUANT represents the accuracy after quantizing layer l to b bits.
B. Sensitivity-Based Layer Profiling: A greedy search assigns the bit-width vector under a total accuracy-drop constraint τ, using register-word requirements from Safe-FFD.The optimization connects quantization choices to packing cost.
B. Sensitivity-Based Layer Profiling: Critical layers retain higher precision, whereas resilient layers are compressed aggressively to maximize packing density and balance accuracy with execution efficiency.The resulting schedule is importance-driven rather than uniform across layers.

C. Selective Protection with MSB Redundancy

Selective MSB redundancy protects only the most critical layers by using unused register bits for TMR-style fault masking. Majority voting restores protected MSBs before multiplication without changing quantization width or range.

C. Selective Protection with MSB Redundancy: For selected critical layers, each quantized weight MSB is replicated twice into available register bits, creating three replicas for TMR.The redundant bits do not alter the quantization range or bit-width.
C. Selective Protection with MSB Redundancy: A lightweight majority voter reconstructs the MSB during inference, then clears redundant bits before packed multiplication.The mechanism preserves packing efficiency while adding minimal area and memory overhead.

D. Systolic-Array Simulation Framework for Packed SIMD Execution

The framework simulates packed SIMD execution on a parameterized systolic array, modeling packed data movement, accumulation, and selective MSB correction during inference.

Simulation framework: The simulator models register-level SIMD execution, packed data movement, and accumulation for systolic-array-based DNN inference.It targets FPGA-style accelerators and evaluates the proposed strategy under realistic execution conditions.
Packed execution: Each processing element consumes one packed operand word per cycle, with heterogeneous operand pairs arranged using compile-time Safe-FFD packing traces.Fixed-width registers and statically determined offsets and masks support subword-level parallelism.
Packed execution: The SIMD MAC operation extracts packed subwords using predefined offsets and masks, while Keff denotes the reduced number of packed register words.The effective iteration count is reduced from the original K operand pairs after packing.
Reliability-aware execution: The execution model reduces iteration depth from K to Keff, lowering memory accesses and execution cycles according to average packing density.For protected layers, MSB replicas in register slack are reconstructed by majority voting before computation without modifying the PE architecture.

A. Experimental Setup

The evaluation uses AlexNet, VGG-11, and ResNet-18 to measure efficiency and reliability across quantized, packed, and protected configurations.

Models and configurations: AlexNet is trained on Fashion MNIST, while VGG-11 and ResNet-18 are trained on CIFAR-10 for the comparative evaluation.Each model undergoes sensitivity-based quantization, deterministic register packing, and reliability analysis.
Evaluation metrics: Execution efficiency is measured with MAC operations, memory utilization, and Safe-FFD packing density.Reliability is assessed using RAP and Pdrop.
Evaluation metrics: RAP combines accuracy degradation with memory and execution overhead relative to the unprotected baseline, with lower values indicating a better trade-off.The metric uses memory and performance overhead terms relative to the unprotected configuration.
Evaluation metrics: Pdrop estimates the likelihood of an accuracy drop over the device lifetime caused by faults, building on single-bit-flip probabilities.It serves as a resilience metric for fault-induced errors.

B. Reliability and performance evaluation

Across three DNNs, selective protection combined with register packing improves the efficiency–reliability trade-off under fault injection compared with unprotected and fully protected baselines.

Overall comparison: Across AlexNet, VGG-11, and ResNet-18, proposed configurations reduce memory usage and execution cost while maintaining lower RAP and Pdrop than the baselines.Higher packing depth improves efficiency, while selective MSB protection avoids the overhead of full protection.
Fault-injection results: The qp4 VGG-11 configuration achieves zero accuracy drop, RAP, and Pdrop at the reported BER because majority voting corrects every corrupted MSB.The passage attributes the zero metrics to complete fault masking in that case.
Fault-injection results: Across BERs from 1 × 10^-5 to 3 × 10^-4, unprotected quantized models show increasing accuracy degradation, especially beyond 1 × 10^-4.The proposed (p3, d4), (p4, d3), and (p5, d2) configurations exhibit smaller drops across the evaluated architectures.
Fault-injection results: 79.80% versus 9.06%: VGG-11 accuracy drop falls from the unprotected q3 configuration to protected-and-packed (p3, d4) at BER = 1 × 10^-4.The protected configuration limits the drop under the stated fault-injection condition.
Efficiency and reliability: Selective protection with packing substantially reduces multiplications and RAP relative to both unprotected and fully protected baselines.The comparison is reported for the evaluated architectures in Figures 3a–3c.

C. Packing Efficiency Analysis

Safe-FFD packing reduces MAC operations by consolidating heterogeneous-precision operands into fixed-width registers, with gains varying across architectures and quantization schedules.

C. Packing Efficiency Analysis: Evaluations use 32-bit registers and sensitivity-derived operand widths of 2, 4, or 8 bits across AlexNet, VGG-11, and ResNet-18.The packing schedule is constructed separately for each architecture.
C. Packing Efficiency Analysis: 55.9% MAC reduction is achieved for VGG-11, compared with 42.9% for ResNet-18 and 6.5% for AlexNet.VGG-11 achieves the highest efficiency gain among the evaluated architectures.
C. Packing Efficiency Analysis: Figure 3 jointly displays multiplication counts and RAP values across evaluated configurations for all three architectures.Bars represent multiplication counts on the left axis, while the line represents RAP on the right axis.
C. Packing Efficiency Analysis: Packing heterogeneous-precision operand pairs at compile time enables multiple MAC operations per register word without changing PE hardware.The resulting reduction in effective iteration depth translates into fewer memory accesses and execution cycles.
C. Packing Efficiency Analysis: VGG-11’s higher packing density reflects a more aggressive quantization schedule that assigns lower bit-widths to multiple layers.These assignments enable tighter packing within the 32-bit register constraint.

IV. CONCLUSION

The framework combines sensitivity-driven mixed precision, deterministic register packing, and selective MSB protection for reliable systolic-array DNN acceleration. Across AlexNet, VGG-11, and ResNet-18, it reports memory savings, fewer MAC operations, and improved reliability without hardware modifications.

IV. CONCLUSION: Sensitivity-driven quantization, Safe-FFD packing, and selective MSB protection jointly form the proposed reliability-aware weight-packing framework.The method targets DNN acceleration on systolic arrays.
IV. CONCLUSION: Safe-FFD consolidates heterogeneous-precision operand pairs at compile time, reducing MAC operations by up to 56% while preserving numerical correctness.Selective MSB protection applies TMR only to vulnerable layers identified through empirical fault injection.
IV. CONCLUSION: Up to 62% memory savings and significant RAP and Pdrop improvements are demonstrated across AlexNet, VGG-11, and ResNet-18 versus baseline approaches.The framework is reported as compatible with FPGA-based systolic-array accelerators.
IV. CONCLUSION: The framework requires no hardware modifications and supports efficient deployment in resource-constrained, fault-prone edge environments.Its stated compatibility is with FPGA-based systolic-array accelerators.