Bringing Chip Tapeout Into University Education

• ASIC fabrication is difficult to integrate into regular teaching because tapeout adds cost, fixed deadlines, restricted access, and substantial coordination.Source: §1 · p. 1
• The central scaling challenge is combining tapeout courses, fabrication services, open-source flows, and multi-university coordination into a recurring model across heterogeneous institutions.Source: §1 · p. 1
• The proposed federated model spans five European universities and combines aligned learning outcomes, local Master’s programs, a reusable chip platform, and shared design infrastructure.Edu4Chip also supports implementation through university courses, fabrication activities, mobility, and shared educational materials.Source: §1 · p. 1
• Rather than comparatively evaluating learning outcomes, the article examines what makes design-to-silicon education feasible, repeatable, and scalable across heterogeneous university environments.The authors state that comparative evaluation requires a longer time horizon.Source: §1 · p. 1

• Existing initiatives address end-to-end tapeout experience, lower-cost fabrication and design infrastructure, or coordination of chip-design education across institutions.Source: §2 · p. 2
• Unlike the compact, mature Croc RISC-V course platform, the shared-chip setting integrates independently developed subsystems and requires common interfaces, verification, distributed development, and chip-level integration.Source: §2 · p. 2
• Fabrication services and open infrastructure, including Europractice, CIME-P, and OpenLane, reduce cost, tooling, and access barriers for universities.OpenLane connects open-source tools into an automated RTL-to-GDSII flow.Source: §2 · p. 2
• Lane, Caravel, Tiny Tapeout, and SwissChips illustrate how implementation and fabrication access can function as shared infrastructure rather than being established independently by each university.Source: §2 · p. 2
• Although programs and initiatives cover complete flows, fabrication access, and curriculum coordination, scaling still requires these elements to work together across different curricula and regulations.The remaining model must also support reusable infrastructure, tool and fabrication access, distributed development, integration, and post-silicon testing.Source: §2 · p. 2

3.1 Edu4Chip in brief

• Edu4Chip coordinates Master’s-level chip-design education and practical design-to-silicon activities across five universities while leaving course structures, regulations, and technical emphases local.The four-year collaboration includes TUM, KTH, DTU, Tampere University, and IMT.Source: §3.1 · p. 3
• The competence-centric approach aligns practical chip-development skills without imposing a one-size-fits-all curriculum, accommodating local strengths and legal and administrative requirements.Students can take a design from specification to tapeout and, where possible, test it after manufacturing.Source: §3 · pp. 2–3, §3.1 · p. 3

3.2 Common outcomes, local implementations

• Common Master’s-level competences span integrated-circuit fundamentals, design tools, and applying that knowledge, while students can specialize in areas such as analog/mixed-signal, digital security, AI, and verification.The practical path progresses from tools and description languages to specification, functional and physical design, and tapeout; projects can include verification, hardware/software partitioning, FPGA validation, and post-manufacturing evaluation.Source: §3.2 · p. 3
• Figure 1 frames theoretical and practical skills as progressing from basic to specialized topics, with modules placed flexibly to suit local requirements.Table 1 describes implementations ranging from a single specification-to-tapeout course to laboratory sequences or labs integrated into other modules.Source: §3.2 · p. 3, Figure 1 · p. 3, Table 1 · p. 4

3.3 Learning through a shared silicon project

• The shared silicon project gives different local implementations a common practical experience, linking coursework and individual laboratory skills to a physical result.Teams specify and document subsystems for integration and encounter planning, review, coordination, and dependence on others’ work.Source: §3.3 · pp. 3–4

4 Technical foundations for scalable design-to-silicon education

• The educational flow addresses the complexity of the complete engineering cycle through a reusable chip platform, standardized integration mechanisms, and a path from specification to fabricated silicon.Source: §4 · p. 4

4.1 A reusable platform for distributed development

• Didactic SoC separates fixed staff-designed infrastructure from student subsystems, letting groups focus on defined designs without building a complete SoC from scratch.Its shared infrastructure remains operational independently of individual subsystem maturity.Source: §4.1 · p. 4
• Common IP-XACT-described interfaces, wrappers, and programmable connections support independently developed digital and mixed-signal subsystems across different local toolchains.Reset and clock-gating controls isolate subsystem faults, and backup designs are available when student subsystems miss integration or manufacturing requirements.Source: §4.1 · p. 4

4.2 From specification to fabricated silicon

• Students progress from specifications and RTL through subsystem and SoC verification, with FPGA prototyping used to validate boot, hardware/software interaction, and peripherals before fabrication.The account notes that successful subsystem simulation alone is not sufficient for a working chip.Source: §4.2 · p. 5
• Physical implementation covers synthesis, floorplanning, placement, routing, timing closure, and sign-off checks, while students learn how the PDK constrains the design.Fabrication uses multi-project wafer runs; post-silicon bring-up compares measurements with pre-silicon predictions and requires test firmware, board interfaces, packaging, and signal access to be considered before tapeout.Source: §4.2 · p. 5

5 First implementations and outcomes

• The first implementations moved the model into practice, spanning platform tapeouts, student designs submitted for fabrication, an electrically validated chip, and outreach activities.The common platform supported tapeout activities, while separate implementations used open-source and commercial flows.Source: §5 · p. 5, §5.1 · p. 5, §5.2 · p. 6

5.1 Platform validation and first tapeouts

• Implementations ranged from a commercial GF 22 nm platform-validation tapeout to an open-source SkyWater 130 nm student run and a fabricated, electrically validated student ASIC.KTH also took a student design through sign-off and submission in GF 22 nm; together, the implementations used advanced and legacy commercial processes as well as an open-source route.Source: §5.1 · p. 5

5.2 A practical implementation at DTU

• At DTU, 20 students in six groups developed a shared 10 mm2 SkyWater 130 nm design that passed DRC, LVS, and timing checks before fabrication submission in May 2026.Hierarchical hardening required stable interfaces as subsystems were incorporated into the larger design.Source: §5.2 · pp. 5–6

5.3 Summer schools and different entry points

• Summer schools offered compact design-to-silicon introductions, while Tiny Tapeout workshops and other outreach provided additional routes into chip-design education.The two summer schools attracted 45 and 51 participants, and the workshops attracted more than 80 participants in 2025 and 72 in 2026.Source: §5.3 · p. 6

Align outcomes, not curricula

• Align learning outcomes and deliverables rather than identical curricula, so universities can organize preparatory work around their local schedules and requirements.A shared tapeout deadline can fall at different points in each partner’s teaching period.Source: §6 · pp. 6–7

Use a reusable chip platform to manage complexity

• A reusable chip platform lets groups develop defined subsystems while still practicing interfaces, verification, physical implementation, and chip-level integration.The repositories, reference designs, tools, dependencies, documentation, and continuous-integration infrastructure also require maintenance between offerings.Source: §6 · p. 7

Shared tapeouts need explicit integration ownership

• Shared tapeouts need a designated integration owner to maintain the top-level design, track verification and dependencies, manage design freeze, and coordinate submission.The authors found this role best assigned to an experienced doctoral researcher, postdoctoral researcher, or staff member.Source: §6 · p. 7

Tool access must be considered from the start

• Commercial tools and processes can expose students to industrial practice, but licensing, NDAs, PDK restrictions, server access, and export controls can limit participation.Open-source flows can be run on students’ own machines and make designs, scripts, PDK interfaces, and teaching materials easier to share.Source: §6 · p. 7

Plan beyond tapeout

• Plan packaging, PCB design, firmware, bring-up, testing, and characterization alongside the chip project because they require additional infrastructure and time.For the Didactic SoC, low-voltage I/Os required level shifting on the test PCB to interface with standard 3.3-V peripherals.Source: §6 · p. 7

• At DTU Compute, associate professor Luca Pezzarossa studies reconfigurable systems and FPGA acceleration, while professor Martin Schoeberl focuses on time-predictable architecture, real-time, and safety-critical systems.Source: Biographies · p. 8
• Tampere doctoral researcher Matti K¨ayr¨a works on SoC design, RISC-V multiprocessors, and ASIC implementation; KTH postdoctoral researcher Nooshin Nosrati focuses on hardware design, reliability, and testability.Source: Biographies · p. 8
• DTU Compute associate professor Matthias Bo Stuart’s interests include computer architecture and system engineering.Source: Biographies · p. 8
• Jean-Max Dutertre is a professor at Mines Saint-Étienne whose interests include hardware security, fault-injection attacks, and countermeasures.Source: Biographies · p. 8
• Tampere professor Timo D. H¨am¨al¨ainen leads the SoC Hub Research Centre and studies SoC design, design automation, RISC-V, and edge architectures.Source: Biographies · p. 8
• TUM adjunct teaching professor Michael Pehl’s research interests include physical unclonable functions, side-channel and fault-injection analysis, and secure hardware.Source: Biographies · p. 8