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Energy-Oriented CGLA Mapping of a Memory-Polynomial Digital Predistortion Kernel

Takuto Ando, Yasuhiko Nakashima

arXiv:2609.27438v1cs.AR

TL;DR

DPD must compensate for power-amplifier nonlinearity while keeping digital processing overhead within the transmitter power budget. This paper maps the memory-polynomial reduction to an IMAX CGLA pipeline and evaluates its latency and modeled energy against GPU and ARM-NEON implementations. The RTX 4090 has the lowest reported end-to-end latency, while the projected IMAX energy comparison is based on stated platform power assumptions.

  • Problem

    DPD must correct power-amplifier nonlinearity without letting digital processing overhead offset RF-side efficiency gains.

    Source: §I · p. 1

  • Method

    The paper maps the odd-order memory-polynomial DPD reduction onto IMAX as a locally reused complex-MAC kernel in a one-dimensional CGLA pipeline.

    Source: §I · p. 2, §II · p. 2

  • Results

    0.484 ms is the RTX 4090 end-to-end latency, versus 3.14 ms for the projected IMAX ASIC configuration.

    Source: B. Latency and Correctness · p. 3

  • Takeaways & Limitations

    For the evaluated mapping, the 120 B coefficient set remains local in a 33-stage PE/LMM pipeline.

    Source: §V · p. 4

    The projected energy is a scenario-based estimate, not a workload-dependent runtime power measurement or direct silicon power measurement.

    Source: §V · p. 4

Abstract

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Memory-polynomial digital predistortion (DPD) evaluates a small fixed coefficient set over a sliding input history, so its reduction step is a complex-MAC workload with local reuse. We map this DPD reduction kernel onto In-Memory Accelerator eXtension (IMAX), a programmable CPU-Grounded Linear Array (CGLA) composed of a one-dimensional processing-element/local-memory pipeline. For a (P,M)=(5,5) odd-order memory-polynomial instance, the mapping keeps the 120 B coefficient set in local memory, advances the five-tap history over 1024-sample tiles, and realizes the 15 order-delay terms as a 33-stage streaming complex-MAC reduction. The evaluation measures kernel latency and modeled energy. All measured paths use the same single-precision complex workload of 32 sequences, each with 2048 complex samples, across an IMAX FPGA prototype, a CUDA implementation on an RTX 4090 system, and an ARM-NEON implementation on Jetson AGX Orin. With this 1024-sample tile configuration, the IMAX FPGA prototype reports 20.201 ms end-to-end latency and 1.948 ms kernel-only latency. Using the previously reported 28 nm IMAX frequency and power model, the projected IMAX configuration gives 3.14 ms end-to-end latency and 0.34 ms kernel-only latency. The RTX 4090 baseline has the lowest end-to-end latency at 0.484 ms. Under model-based platform power accounting and the stated power assumptions, the projected IMAX configuration gives 169.1 times smaller modeled end-to-end energy per batch than the RTX 4090 baseline. This value uses platform power assumptions rather than workload-dependent runtime power or a direct silicon power measurement. A controlled synthetic PA-model validation checks that the same 15-term form improves test-set NMSE by 26.1 dB and ACLR by 26.0 dB. These results characterize the mapped memory-polynomial DPD reduction on IMAX for the evaluated tile configuration and power model.

I. INTRODUCTION

DPD must correct power-amplifier nonlinearity without letting digital processing overhead offset RF-side efficiency gains. This paper maps the memory-polynomial reduction onto IMAX as a locally reused complex-MAC pipeline and compares measured and projected platform configurations.

I. INTRODUCTION

  • The reviewed literature contained no reported memory-polynomial DPD implementation on a programmable CGLA.In IMAX, the coefficient set and five-tap delay history fit in one 16 KB LMM bank.Source: §I · p. 1
  • The odd-order memory-polynomial form uses p ∈ {1, 3, 5} and five memory taps, yielding 15 complex order–delay terms per output sample.The reduction is treated as a streaming complex-MAC workload with local reuse.Source: §I · pp. 1–2
  • The study evaluates a kernel mapping rather than a complete real-time DPD transmitter, assuming fixed coefficients during execution.Continuous streaming integration, coefficient adaptation, fixed-point quantization, PA-specific measurement, and EVM-constrained deployment are outside its scope.Source: §I · pp. 1–2
  • The (P, M) = (5, 5) mapping keeps 120 B of coefficients in local memory and reduces 15 order–delay terms through a 33-stage PE/LMM pipeline.The coefficient set is fixed during execution, while the delay window advances with the input stream.Source: §I · pp. 1–2
  • The comparison uses the same single-precision workload across IMAX, CUDA, and ARM-NEON, and separates kernel-only latency from end-to-end latency.The separation distinguishes the CGLA reduction from host-side basis expansion, staging, DMA, and prototype boundary overhead.Source: §I · pp. 1–2

II. BACKGROUND AND RELATED WORK

The paper positions its memory-polynomial DPD mapping as a programmable-CGLA kernel study rather than a direct comparison with RF-DPD accelerators. IMAX's linear PE/local-memory pipeline supports local coefficient reuse and ordered streaming I/O.

II. BACKGROUND AND RELATED WORK

  • The study maps memory-polynomial DPD reduction onto a programmable CGLA, a mapping not reported in the reviewed literature.Its measured focus is kernel latency, data movement, and modeled energy, not direct RF-DPD accelerator comparison.Source: §II · p. 2
  • Prior ASIC, FPGA, and GPU DPD studies use differing models, RF conditions, precision choices, and metrics, so they serve as contextual rather than direct numerical baselines.The paper does not evaluate linearization quality relative to GMP, Volterra, or neural DPD models.Source: §II · p. 2
  • IMAX arranges processing elements and local memories along one pipeline; its FPGA prototype places ARM cores and DMA control in the PS and the IMAX array in the PL.The host configures the path and launches data through DMA toward the array.Source: §II · p. 2, Figure 1 · p. 2
  • The DPD reduction fits the linear pipeline because its 120 B coefficient set stays LMM-resident, its delay history supports ordered streaming, and each output is a one-dimensional dependence chain.Complex multiplication uses an OP_FMA/OP_FMS pair across two PEs per term.Source: §II · p. 2

III. IMAX MAPPING

The IMAX mapping consumes host-expanded order–delay terms in a pipeline that retains coefficients and delay-derived operands locally. Operand movement and fused updates use the IMAX schedule's specified operations.

III. IMAX MAPPING

  • Host-side basis expansion forms the order–delay terms before the IMAX pipeline consumes them.The placement is shown in Fig. 2.Source: §III · p. 2
  • The pipeline holds coefficients and delay-derived operands in LMM across the tile, while load and store mops move operands.Offset arithmetic uses OP_ADD and accumulator forwarding uses OP_NOP.Source: §III · p. 2
  • Fused floating-point updates use OP_FML, OP_FMS, and OP_FMA in the mapped schedule.Source: §III · p. 2

A. Streaming Dataflow

The streaming dataflow keeps tile-invariant coefficients and delay-derived state local while ordered input and output samples cross the host–accelerator boundary. Host-side basis expansion feeds an ordered complex-MAC reduction for each output.

A. Streaming Dataflow

  • Coefficients, delay-derived operands, and the per-output accumulator remain local to the PE/LMM pipeline as ordered input and output streams cross the host–accelerator boundary.For (P, M) = (5, 5), each output has 15 complex order–delay terms.Source: A. Streaming Dataflow · p. 2
  • A 1024-sample tile contains 512 packed complex-sample pairs, with host-side expansion preparing 15 basis terms for the two samples in each pair.The per-tile traffic is 122.88 KB of basis staging plus 8.192 KB each for input and output streams.Source: A. Streaming Dataflow · pp. 2–3
  • The 120 B coefficient set is initialized once in LMM and reused across all 512 packed pairs.Source: A. Streaming Dataflow · p. 3
  • Each output is one ordered reduction with no partial sum written back between polynomial orders or memory delays.For each delay and odd order, a pre-expanded basis value is multiplied by its coefficient and accumulated.Source: A. Streaming Dataflow · p. 3
  • Term 0 seeds the accumulator with OP_FML, then terms 1–14 repeat an OP_FMS real update and OP_FMA imaginary update for each packed pair.Source: A. Streaming Dataflow · p. 3

B. Pipeline Placement

The pipeline places each complex-MAC term in a spatial chain, with dedicated stages for offset advancement, seed loads, MAC work, and output writeback. For odd-only (P, M), the stage count is 2T + 3.

B. Pipeline Placement

  • For (P, M) = (5, 5), T = 15 terms occupy a 33-stage pipeline segment.The general odd-only instance uses T = ⌈P/2⌉M terms and 2T + 3 stages.Source: B. Pipeline Placement · p. 3
  • PE0 advances the per-pair basis offset, PE1 issues seed-term loads, PE2–PE31 host the 15 complex-MAC stages, and PE32 drains and stores outputs.Source: B. Pipeline Placement · p. 3
  • Because each term depends only on the preceding accumulator, the reduction maps as a one-dimensional spatial chain from local-state setup to writeback.Source: B. Pipeline Placement · p. 3

A. Setup and Power Model

The evaluation compares IMAX with RTX 4090 and Jetson AGX Orin on the same workload, separating measured platforms from the projected 28 nm IMAX configuration. The representative IMAX tile is 1024 samples.

A. Setup and Power Model

  • The batch contains 65,536 complex samples across 32 independent sequences, each with 2048 samples.The P = 5, M = 5 workload is compared across IMAX, RTX 4090, and Jetson AGX Orin.Source: A. Setup and Power Model · p. 3
  • The 1024-sample IMAX tile configuration records 20.201 ms end-to-end and 1.948 ms kernel-only latency on the FPGA prototype.End-to-end time includes host basis expansion, staging/DMA, register setup, IMAX execution, and output writeback; kernel-only time covers the reduction over pre-expanded values.Source: A. Setup and Power Model · p. 3
  • The 28 nm IMAX projection scales kernel-only latency to 0.336 ms and gives 3.14 ms end-to-end latency.The projection combines the scaled kernel time with 2.3 ms ARM preparation and 0.5 ms on-chip memory access.Source: A. Setup and Power Model · p. 3

B. Latency and Correctness

The 1024-sample configuration has the lowest measured end-to-end latency on RTX 4090, while the IMAX FPGA kernel-only measurement separates array reduction time from prototype overhead. Tile size changes the latency and buffering trade-off.

B. Latency and Correctness

  • 0.484 ms is the RTX 4090 end-to-end latency, compared with 3.14 ms projected IMAX, 4.478 ms Jetson, and 20.201 ms FPGA prototype.The projected IMAX figure is not a measured silicon result; the FPGA end-to-end value includes host boundary, register setup, and tile transfers.Source: B. Latency and Correctness · p. 3, Figure 3 · p. 4
  • 1.948 ms is the FPGA prototype's kernel-only latency, isolating the PE/LMM reduction from its 20.201 ms end-to-end time.The reported difference indicates most observed time is outside the PE/LMM reduction, in prototype host-boundary and DMA setup.Source: B. Latency and Correctness · p. 3
  • Against the same reference output, maximum absolute output differences remain in the 10−6 range for IMAX and the 10−7 range for GPU; IMAX differences come from FMA/FMS accumulation order.Source: B. Latency and Correctness · pp. 3–4
  • The 32-sample tile takes 66.984 ms end-to-end and 6.034 ms kernel-only, while the 2048-sample tile takes 19.740 ms and 2.905 ms, respectively.Both tile checks report no mismatches; the 2048-sample tile buffers a full block, while 1024 samples is the representative overhead-amortized point.Source: B. Latency and Correctness · p. 4

C. Energy per Batch

The energy comparison uses platform power assumptions and wall time to estimate energy per batch, rather than workload-dependent runtime power measurements. The projected IMAX estimate is lower than the RTX 4090 and Jetson estimates under this model.

C. Energy per Batch

  • The energy estimate is scenario-based platform-power accounting, not workload-dependent runtime power or a direct cross-platform silicon power measurement.Energy is computed as average power times wall time.Source: C. Energy per Batch · p. 4
  • 1.86 mJ per batch is projected for IMAX, versus 314.6 mJ for RTX 4090 and 67.2 mJ for Jetson AGX Orin.The reported comparison is 169.1× lower than RTX 4090 and 36.1× lower than Jetson AGX Orin.Source: C. Energy per Batch · p. 4
  • PA-specific RF measurement, fixed-point quantization, continuous streaming, and coefficient adaptation remain outside the accelerator evaluation.Source: C. Energy per Batch · p. 4

D. Synthetic PA Validation

The synthetic validation tests the 15-term correction form on a held-out waveform, while the conclusion characterizes the IMAX mapping and its model-based projection. The evaluation remains limited to the stated kernel mapping and power assumptions.

D. Synthetic PA Validation

  • 26.1 dB NMSE improvement and 26.0 dB ACLR improvement are reported for the 15-term correction on a held-out synthetic test waveform.NMSE changes from -18.75 dB to -44.87 dB, ACLR from -31.26 dBc to -57.24 dBc, and PAPR increases from 10.39 dB to 13.32 dB.Source: D. Synthetic PA Validation · p. 4

V. CONCLUSION

  • The conclusion describes a 33-stage PE/LMM mapping that keeps the 120 B coefficient set local for the (P, M) = (5, 5) reduction.Source: §V · p. 4
  • The projected IMAX result is 3.14 ms end-to-end and 1.86 mJ per batch under stated power values, not a workload-dependent or direct silicon measurement.The conclusion identifies coefficient adaptation and continuous-streaming integration as future work.Source: §V · p. 4
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