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Precision and resource scaling of real-time flux distortion compensation for superconducting quantum control
Qi Zhou, Zi-Hao Mei, Peng Duan, Peng Wang, Liang-Liang Guo, Hao-Ran Tao, Wei-Cheng Kong, Hui Yang, Guo-Ping Guo, Zhao-Yun Chen
TL;DR
Long-lived flux-line distortions make later gates depend on the pulse history, while dynamic circuits synthesize waveforms along conditional execution paths. The paper introduces compact real-time inverse filtering with FPGA parallelization; its implementation closely matches the software-reference gate-fidelity result, with modest resource growth as compensation timescale increases.
Problem
Flux-line distortions persist beyond a gate, so conditional pulse histories change the distortion experienced by later gates and fixed-sequence offline corrections cannot track dynamic execution paths.
Source: §I · p. 1Method
FDI-TDF reconstructs a compensation impulse response and fits it with a compact hybrid IIR/FIR filter, implemented using FPGA look-ahead parallelization.
Source: §I · p. 1, §V · p. 10Results
The fourth-order, 44-bit IIR configuration achieved a median CZ Pauli fidelity close to the 99.57% software reference; extending coverage to hundred-microsecond timescales adds about 14% LUT and 4% DSP resources below 10^-4 relative arithmetic error.
Source: §V · pp. 10–11Takeaways & Limitations
Hardware resource use grows approximately logarithmically with compensation timescale, and the reported resource and precision analysis provides a basis for scaling real-time compensation to processors with thousands of physical qubits.
Source: §I · p. 2, §V · p. 11
Abstract
from arXiv · showhide
Real-time waveform generation supports dynamic quantum circuits without pre-storing complete waveforms for every execution path. However, long-lived distortions in flux-control lines degrade gate fidelity, requiring compensation to account for the actual pulse history. A frequency-domain inversion and time-domain fitting method is proposed for resource-efficient real-time flux distortion compensation. The method fits the reconstructed compensation impulse response with a compact hybrid infinite impulse response (IIR) and finite impulse response (FIR) filter. Look-ahead parallelization enables this filter to process synthesized waveforms at 1.2GSa/s on a field-programmable gate array (FPGA). Two-qubit cross-entropy benchmarking shows that real-time IIR filtering achieves a median controlled-Z Pauli fidelity close to the software-reference value of 99.57%. Numerical analysis and FPGA synthesis indicate approximately logarithmic growth in hardware resource use with compensation timescale. Extending compensation from microsecond to hundred-microsecond timescales increases look-up table (LUT) and digital signal processing (DSP) resource use by only about 14% and 4%, respectively, while maintaining a relative arithmetic error below $10^{-4}$. This work provides a scalable hardware foundation for high-fidelity flux control in dynamic superconducting quantum circuits.
I. INTRODUCTION
Dynamic branching changes the flux-pulse history during execution, so compensation must follow synthesized waveforms rather than rely only on corrections precomputed for fixed sequences. The paper proposes compact real-time filtering and models flux-line responses from measured step responses using short- and long-time components.
I. INTRODUCTION
- Residual flux-line responses can affect later gates, and conditional pulses change the distortion history, making real-time inverse filtering after waveform synthesis essential for dynamic execution paths.Offline pre-distortion is tied to a predetermined pulse sequence.Source: §I · p. 1
- The proposed FDI-TDF method fits a reconstructed compensation impulse response with a compact hybrid IIR/FIR filter and uses FPGA look-ahead parallelization to sustain gigasample-per-second processing.The method builds on a prior characterization and calibration framework.Source: §I · pp. 1–2
A. LTI system modeling and time-domain mapping
- Flux-line behavior is modeled as an LTI system, with the measured step response used to capture edge dynamics and the subsequent settling tail.The input samples convolved with the impulse response give the on-chip flux waveform.Source: A. LTI system modeling and time-domain… · pp. 2–3
- Partial-fraction decomposition represents the response with a finite FIR term and first- and second-order IIR modes for short-time dynamics, monotonic relaxation, and damped oscillations.Recursive modes retain long-time response components using a small number of state variables rather than a separate FIR coefficient for every tail sample.Source: A. LTI system modeling and time-domain… · p. 3
- The step-response fit uses monotonic and oscillatory modes alongside a finite FIR component, whose tap count is S + 1.The modal time dependences parameterize the measured response for n ≥ 0.Source: A. LTI system modeling and time-domain… · p. 3
B. FDI-TDF algorithm and parallel model reconstruction
FDI-TDF addresses the hardware cost and finite-word-length sensitivity of direct inversion by reconstructing a target compensation response and fitting it with a compact hybrid filter. Regularized frequency-domain inversion limits high-frequency noise amplification before time-domain fitting.
B. FDI-TDF algorithm and parallel model reconstruction
- Direct inversion of a detailed forward model can produce a high-order IIR filter whose arithmetic and state requirements are costly, while poles near the unit circle increase finite-word-length sensitivity.For H(z) = B(z)/A(z), the exact inverse is A(z)/B(z).Source: B. FDI-TDF algorithm and parallel… · p. 3
- FDI-TDF reconstructs the target compensation impulse response by measuring the step response, differencing it to obtain the impulse response, and applying regularized frequency-domain inversion.A Gaussian weight suppresses high-frequency contributions, where direct inversion can amplify measurement noise.Source: B. FDI-TDF algorithm and parallel… · pp. 3–4
- The Gaussian width is set to 80%–90% of the Nyquist limit, suppressing high-frequency noise amplification while retaining inverse phase correction and approximately preserving low-frequency amplitude correction.The weighted inverse response is transformed back to the time domain to obtain g[n].Source: B. FDI-TDF algorithm and parallel… · p. 4
- Nonlinear least squares fits g[n] with a compact FIR branch and low-order recursive sections; the FIR handles short-time correction while SOS branches represent decay and oscillatory components.Three parallel SOS and a 43rd-order FIR branch are described as generally sufficient, with accuracy comparable to software pre-distortion.Source: B. FDI-TDF algorithm and parallel… · pp. 4–5, Figure 2 · p. 4
C. Parallel filter architecture via look-ahead transformation and sliding windows
The parallel architecture combines look-ahead IIR filtering with blockwise computation so consecutive outputs can be produced without within-block recursive dependence. This retains the IIR history while matching the DAC sampling rate at a lower FPGA clock frequency.
C. Parallel filter architecture via look-ahead transformation and sliding windows
- Look-ahead transformations for IIR sections and sliding-window computation for the FIR branch produce the same block of consecutive samples in parallel.The compact filter alone would still require serial recursive updates at the DAC sampling rate.Source: C. Parallel filter architecture via… · p. 5
1. IIR parallelization via look-ahead transformation
- Recursive substitution expresses each output in an L-way block using only the preceding block’s retained state and known feedforward terms, removing sequential dependence within the block.The block recurrence uses coefficient matrices A and B derived from the recursive expansion.Source: §1 · p. 5
- For second-order sections with L = 6, feedforward and feedback contributions combine to produce six outputs per FPGA cycle, with the final two outputs becoming the next cycle’s retained state.This block formulation exposes parallel arithmetic while preserving recursive history.Source: §1 · p. 5
2. FIR parallelization via a sliding window
The FIR branch computes consecutive outputs from overlapping input windows, complementing the block-parallel IIR path. The evaluation platform pairs a 1.2 GSa/s DAC with a 200 MHz FPGA clock and compares real-time filtering with bypass playback.
2. FIR parallelization via a sliding window
- A 43rd-order FIR branch uses a 49-sample input window to compute six consecutive outputs through six parallel 44-tap convolutions.The window advances by six samples each clock cycle as six new inputs enter and the six oldest samples leave.Source: §2 · p. 5
III. HARDWARE IMPLEMENTATION AND EXPERIMENTAL VALIDATION
- The experimental validation evaluates waveform measurements and two-qubit benchmarking, including comparisons of real-time compensation with double-precision software pre-distortion and of filter orders and word lengths.In situ qubit measurements assess cryogenic compensation at different IIR word lengths.Source: §III · p. 6
A. Hardware platform and filter architecture
- The FPGA platform uses a 16-bit, 1.2 GSa/s DAC and a 200 MHz fabric clock, processing six samples per clock with a fourth-order IIR and 44-tap FIR at 44-bit arithmetic.Both filter branches use 44-bit arithmetic in the primary chip experiments.Source: A. Hardware platform and filter… · p. 6
- Real-time mode filters synthesized samples before DAC conversion, while bypass mode plays stored waveforms that may be uncompensated or offline-compensated; both use the same DAC channel, cabling, and qubit flux line.The cryogenic response and two-qubit benchmarking data were acquired on the 102-qubit OriginQ Wukong processor.Source: A. Hardware platform and filter… · p. 6
B. Room-temperature waveform comparison
Real-time FPGA compensation reproduces the principal transient correction of software pre-distortion, and cryogenic 44-bit filtering approaches the software reference. In two-qubit benchmarking, its median CZ Pauli fidelity is close to the software-reference median.
B. Room-temperature waveform comparison
- Both software and FPGA compensation suppress the microsecond-scale settling tail, while the FPGA reproduces the software reference's edge shaping and ringing suppression.The FPGA-compensated plateau is about 0.2% lower than the software-compensated value; the offset can be absorbed into routine qubit operating-point calibration.Source: B. Room-temperature waveform comparison · pp. 6–7, Figure 3 · p. 6
C. Cryogenic distortion calibration
- At 44 bits, the cryogenic response is nearly flat and approaches the software reference, with measured fluctuations on the order of 10^-4; the 35-bit filter retains a tail beyond 10 µs.The 35-bit tail starts near 10^-3, while the 44-bit fitted-response deviations are also on the order of 10^-4.Source: C. Cryogenic distortion calibration · p. 7, Figure 4 · p. 8
D. Two-qubit gate benchmarking
- 99.53% median CZ Pauli fidelity for the primary fourth-order, 44-bit IIR configuration is close to the software-reference median of 99.57%.Across the four firmware configurations, XEB medians lie within the software-reference interquartile range; increasing order or word length does not produce monotonic median-fidelity improvement.Source: D. Two-qubit gate benchmarking · p. 7
- The SPB and XEB cycle metrics differ by 0.07–0.18 percentage points, indicating that incoherent errors account for most measured cycle error.Together with the absence of systematic fidelity gains at higher filter order or word length, the results suggest residual flux distortion is not the dominant limitation on measured gate fidelity.Source: D. Two-qubit gate benchmarking · p. 7
IV. NUMERICAL PRECISION AND RESOURCE SCALING
The section examines how arithmetic precision affects compensation accuracy and hardware cost across measured cryogenic channels. For native response models, comparable coefficient and state widths of at least 42 bits keep channel-averaged peak error below one DAC LSB.
IV. NUMERICAL PRECISION AND RESOURCE SCALING
- Longer inverse-filter time constants increase sensitivity to coefficient quantization and state rounding, while wider arithmetic increases hardware cost per channel.The analysis therefore varies coefficient and state precision jointly before relating a common word length to response timescale and hardware cost.Source: §IV · p. 8, A. Impact of arithmetic precision on… · p. 9
- The analysis uses cryogenic response models from 147 selected flux-control channels and compares fixed-point outputs against a double-precision reference while varying coefficient and state widths.The native models have a mean dominant inverse-pole time constant of 10.44 µs; most can be represented by two SOS, while a small minority require a third.Source: §IV · p. 8, A. Impact of arithmetic precision on… · p. 8
A. Impact of arithmetic precision on compensation outputs
- At least 42-bit coefficient and state word lengths keep native-model channel-averaged peak error below one LSB.The error map decreases overall as coefficient and state precision increase together; the diagonal pattern motivates equal word lengths in the FPGA datapath.Source: A. Impact of arithmetic precision on… · p. 9, Figure 6 · p. 9
B. Time-constant coverage versus word length
The analysis relates fixed-point precision to supported inverse-filter timescale, then quantifies FPGA resource scaling and reports real-time gate-fidelity performance. Extending compensation coverage to longer timescales requires comparatively modest resource growth over the superconducting-control range.
B. Time-constant coverage versus word length
- The analysis compares fixed-point output with high-precision software over records spanning at least 8τ and 20,000 samples, using one-LSB and normalized relative-error criteria.The relative-error threshold is ¯rmax < 10^-4; the model family varies the dominant time constant while retaining other modal properties.Source: B. Time-constant coverage versus word… · pp. 9–10, Figure 7 · p. 10
- At 44 bits, supported time constants exceed 100 µs under the relative-error threshold, while the one-LSB criterion supports up to 35 µs.At 56 bits, coverage reaches several hundred milliseconds under the relative-error criterion.Source: B. Time-constant coverage versus word… · p. 10
C. Resource scaling with compensation timescale
- At 44 bits, resource estimates indicate capacity for nine independent channels per FPGA; higher precision extends coverage to hundred-millisecond timescales at reduced channel parallelism.Assigning IIR order according to channel response complexity could improve resource use and multichannel scalability.Source: C. Resource scaling with compensation… · p. 10
V. DISCUSSION AND CONCLUSION
- The fourth-order, 44-bit IIR configuration on the OriginQ Wukong processor achieves median CZ Pauli fidelity close to the 99.57% software reference.The conclusion also describes a quantitative relation between timescale, precision, and implementation cost for a sixth-order IIR structure.Source: §V · pp. 10–11
C. Resource scaling with compensation timescale
- From approximately 1 µs to 138 µs coverage, LUT and DSP use rise only about 14% and 4%, respectively, while relative arithmetic error remains below 10^-4.Overall resource use grows approximately logarithmically with supported timescale, with DSP use progressing in discrete steps.Source: C. Resource scaling with compensation… · p. 10, Figure 8 · p. 11
Appendix A: Step-response characterization of the full flux-control chain
The full-chain characterization separates room-temperature response, cryogenic long-time settling, and cryogenic short-time transients. Measurements of these components provide the response information used to reconstruct the compensating filter.
Appendix A: Step-response characterization of the full flux-control chain
- The workflow measures room-temperature electronics, initializes and refines a cryogenic long-time model, then measures the remaining short-time response.The short-time measurement follows long-time compensation; together the stages provide information for reconstructing the compensating filter.Source: Appendix A · p. 11, Figure 9 · p. 12
1. Room-temperature electronic characterization
- An isolated room-temperature square-wave step is recorded and fitted to estimate HRT(z), whose inverse preprocesses later cryogenic probe waveforms.The long half-period isolates each edge, and waveform averaging reduces measurement noise.Source: §1 · p. 11
2. Characterization of cryogenic step response
- Qubit probing sweeps delay and bias after a flux step; the bias maximizing excited-state population estimates the residual tail for modal fitting.The fitted amplitudes, decay times, and any oscillation parameters initialize the long-time inverse model.Source: §2 · pp. 11–12
3. Closed-loop refinement of the cryogenic long-time inverse response using randomized benchmarking
- Closed-loop randomized benchmarking optimizes long-time inverse-filter parameters by maximizing mean Clifford fidelity after a pre-distorted flux pulse.A delay separates the RB block from short-time edge transients, and the optimized parameters define the calibrated inverse response.Source: §3 · pp. 12–13
4. Cryogenic short-time step response via pre-distortion-assisted Cryoscope
After long-time compensation, pre-distortion-assisted Cryoscope measures the remaining pulse-edge response. Ramsey phase measurements are differentiated to recover the transient frequency shift and convert it to flux response.
4. Cryogenic short-time step response via pre-distortion-assisted Cryoscope
- The long-time inverse filter preprocesses the step to suppress long-time components before Cryoscope measures the remaining short-time response.The preprocessed step is applied within a Ramsey sequence, with free-evolution time scanned to measure accumulated phase.Source: §4 · p. 13
- Differentiating reconstructed Ramsey phase yields the transient frequency response, which is converted to on-chip flux using the calibrated flux–frequency relation.Orthogonal analysis phases provide the quadratures used to reconstruct and unwrap accumulated phase.Source: §4 · p. 13
- The measured short-time response completes the FDI-TDF reconstruction, with IIR sections modeling long-time correction and an FIR branch capturing remaining short-time structure.Source: §4 · p. 13
Appendix B: Parallel IIR filter coefficient calculation
The appendix addresses the throughput limit imposed by recursive IIR dependence. Look-ahead block processing makes a group of outputs depend on retained prior outputs and current feedforward terms, enabling parallel computation.
Appendix B: Parallel IIR filter coefficient calculation
- Look-ahead block processing expands the recursive IIR relation so a block of L outputs depends on preceding state and current feedforward terms.The appendix derives coefficient matrices for this parallel computation.Source: Appendix B · p. 13
1. System definition
- The system definition distinguishes feedback coefficients a_k from feedforward coefficients b_k, with the latter forming the feedforward convolution.Source: §1 · p. 13
2. Objective of parallelization
The objective is to compute blocks of outputs in parallel rather than rely on the serial IIR recurrence. Each block is expressed using retained prior outputs and known feedforward terms.
2. Objective of parallelization
- L-way parallelization computes a block of outputs at each processing cycle, with n = kL.Here, k is the processing-cycle index and L is the parallelization factor.Source: §2 · p. 13
- The block recurrence uses the preceding N outputs and the current block's known feedforward terms.The retained outputs are ordered chronologically; the recurrence uses feedback and feedforward coefficient matrices A and B.Source: §2 · p. 13
- For each output y[n + m], coefficients α_m,k and β_m,ℓ multiply preceding outputs and feedforward terms, respectively.The indices range over the L outputs in the block.Source: §2 · p. 13
3. z-domain derivation of the look-ahead expansion
The derivation uses a look-ahead polynomial to remove low-order feedback terms and express block outputs through retained outputs and known feedforward terms. It then identifies the coefficients used in the block recurrence and its matrices.
3. z-domain derivation of the look-ahead expansion
- The look-ahead polynomial Q_m(z) is chosen to cancel the coefficients of z^-1 through z^-m in its product with A(z).Equating those coefficients to zero yields a lower-triangular Toeplitz system for the polynomial coefficients.Source: §3 · p. 14
- The first look-ahead coefficients are u1 = a1, u2 = a2 − u1a1, and u3 = a3 − u1a2 − u2a1.These relations follow from setting the low-order feedback coefficients to zero.Source: §3 · p. 14
- After the low-order feedback terms are annihilated, the transformed relation is inverse-z-transformed and evaluated at n + m to obtain look-ahead coefficients.The coefficients are identified by comparing the resulting expansion with the target block expansion.Source: §3 · p. 14
- The feedback matrix uses chronological state columns despite the reversed lag index, and its first row is [−aN, . . . , −a1].For second-order sections and six-sample blocks, the matrices have dimensions 6 × 2 for feedback and 6 × 6 for feedforward.Source: §3 · pp. 14–15