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Towards Energy-Neutral IoT Sensors: Low-Cost Chirp-Based Backscattering Node Using a COTS Microcontroller and Multi-Load Front-End
Tijl Schepens, Liesbet Van der Perre, Gilles Callebaut
TL;DR
Cost-efficient, widely available hardware is needed for large-scale backscatter deployments, but existing architectures trade simplicity against spectral efficiency. This paper develops a COTS microcontroller-based multi-load node and load-design approach; its prototype demonstrates a single-sideband signal with suppressed carrier.
Problem
Large-scale backscatter deployments need cost-efficient, widely available hardware, while existing solutions include FPGA-based designs or simpler two-load microcontroller designs that sacrifice spectral efficiency.
Source: §I · p. 1Method
The paper develops a multi-load backscatter architecture using a microcontroller and DMA, and selects loads through a two-port S-parameter design process that accounts for individual paths.
Source: §III · p. 2, §IV · p. 2Results
With eight loads, the measured backscatter concentrates more energy in a single sideband and suppresses the carrier by more than 10 dBm.
Source: A. Measurements · p. 3Takeaways & Limitations
COTS microcontrollers can build spectrally efficient backscatter solutions, although multi-load hardware requires higher IO switching speeds and the RF switch network poses a significant cost.
Source: §V · p. 3The RF switch network is a significant cost in the demonstrated multi-load architecture.
Source: §V · p. 3
Abstract
from arXiv · showhide
Backscatter communication has proven to be a key enabler for energy-neutral sensor nodes in the IoT. It allows ultra-low-power nodes to transmit sensor data by reflecting incident RF signals. Practical large-scale deployment requires hardware solutions that are both cost-efficient and widely available. This paper investigates the practical limits of implementing backscatter transmitters exclusively using COTS components. We compare a two-load and multi-load architecture in terms of hardware requirements, complexity and spectral efficiency highlighting the most important trade-offs. A multi-load backscatter architecture is developed using a resource constrained low-power microcontroller, levering DMA to achieve high switching speeds while minimizing processing overhead. Furthermore, we present a layout agnostic load design methodology based on scattering parameters, allowing precise control of the reflection coefficients. A prototype implementation demonstrates a successful backscatter transmission of a single-sideband chirp with reduced harmonic distortion. Measurement results show suppression of the backscattered carrier and the second sideband by 10 dBm. This demonstrates that low-cost sensor nodes can be built using COTS components enabling remote monitoring at extended lifetimes.
I. INTRODUCTION
Energy-neutral IoT sensor deployments need backscatter hardware that is low-cost and widely available, but existing approaches trade hardware requirements against spectral efficiency. This paper explores backscatter transmitters built solely from COTS components.
I. INTRODUCTION
- Mass deployment calls for low-cost, low-power backscatter hardware, while many research solutions rely on FPGAs and two-load microcontroller designs sacrifice spectral efficiency.The introduction frames COTS components as a route for lower-volume deployments.Source: §I · p. 1
- The paper explores backscattering solutions relying solely on COTS components, with a focus on availability and cost optimization.The solution is hosted on the Ambient-6G END Platform repository.Source: §I · p. 1
II. HARDWARE ARCHITECTURES
Two-load modulation offers simple microcontroller control but produces harmonics and lower spectral efficiency. Multi-load and IQ-modulator approaches provide alternatives with greater switching or signal-generation demands.
II. HARDWARE ARCHITECTURES
- Two-load GPIO switching can generate tones, 2-FSK, or chirps, but its square-wave-like modulation reduces spectral efficiency and creates harmonics that may disturb adjacent channels.A sufficiently high base switching speed can move backscattered signals out of band, avoiding complex carrier cancellation and boosting range.Source: §II · pp. 1–2
- Multi-load modulation gradually changes backscatter phase, requiring n^2 times faster load cycling than a two-load system for the same signal.For a 125 kHz-bandwidth chirp shifted 125 kHz, the stated maximum cycling rate rises from 500 kHz with two loads to 2 MHz with eight.Source: §II · p. 2
- IQ-modulator approaches vary backscatter impedance with RF transistors, driven by a DAC or GPIOs with sufficient oversampling.Quadrature operation uses two transistors with one signal branch shifted by 90 degrees.Source: §II · p. 2
III. MULTI-LOAD FRONT-END DESIGN
The multi-load front end uses a low-power microcontroller to select antenna loads, with DMA intended to sustain switching speed while reducing CPU workload.
III. MULTI-LOAD FRONT-END DESIGN
- The design considers the STM32U031 and MSPM0C1104 as low-power microcontroller candidates.Source: §III · p. 2
- Direct register access reaches 3 MHz on the STM32U031 and 4 MHz on the MSPM0C1104, but consumes excessive CPU time and slows when the CPU handles more complex logic.Source: §III · p. 2
- DMA offloads the CPU and maintains maximum switching speeds: the STM32U031 reaches 3.4 MHz, while the MSPM0C1104 is limited to 400 kHz by DMA restart time.The STM32U031 uses circular mode to reset its memory address counter in hardware.Source: §III · p. 2
IV. LOAD DESIGN
The load design targets reflection coefficients on a constant VSWR circle and accounts for differences among physical antenna-to-load paths. Measured input reflections closely follow theoretical points, with residual deviations attributed to parasitics and unequal, unoptimized PCB paths.
IV. LOAD DESIGN
- Loads are placed on a constant VSWR circle so cycling through them rotates reflected-wave phase and concentrates the signal in one sideband with fewer harmonics.Source: §IV · p. 2
- Unequal PCB traces and RF switches introduce load-specific phase shifts and attenuation, so each path is characterized as a two-port with a VNA before final load selection.If all paths have equal length, their effects only rotate the complete VSWR circle.Source: §IV · p. 2
- Measured antenna-port reflection points closely follow theoretical points, with remaining deviations attributed to parasitics and PCB paths not optimized for equal lengths.Source: §IV · p. 2
- The method uses two-port S-parameters to convert a desired antenna-port reflection coefficient Γin into the required load reflection coefficient ΓL.The wave convention defines incident waves ai and outgoing waves bi at each port.Source: §IV · p. 2
A. Measurements
The measurements test DMA-based switching on an STM32U031 and examine the resulting backscatter signal and load impedances. The reported 8-load transmission produces a single-sideband chirp and suppresses the backscattered carrier.
A. Measurements
- The spectrally efficient DMA solution was tested on an STM32U031 microcontroller running at 48 MHz.The GPIO-speed comparison covers direct register access and timer-triggered DMA on the STM32U031 and MSPM0C1104; the time scales differ.Source: A. Measurements · p. 2, Figure 2 · p. 3
- The impedance plot distinguishes theoretical points on a circle from practically measured points.Source: Figure 3 · p. 3
- The 8-load transmission produces a single-sideband signal with more energy concentrated in it and suppresses the backscattered carrier by more than 10 dBm.The measured signal is a linear chirp from 125 to 250 kHz; the RF front-end consumes 81.14 nW idle and 3.63 µW during transmission.Source: A. Measurements · p. 3
V. CONCLUSION
The 8-load architecture produces a single-sideband chirp and suppresses the backscattered carrier. The conclusion describes how DMA supports the switching demands of COTS microcontrollers while noting hardware cost and further architecture questions.
V. CONCLUSION
- Multi-load hardware produces single-sideband signals and reduces harmonics but requires higher IO switching speeds, which DMA and a stored waveform address.The conclusion describes a 48 MHz Cortex-M0+ microcontroller transmitting chirps shifted from the carrier; DMA requires repeated transfers and a sufficiently fast timer trigger.Source: §V · p. 3
- The 8-load architecture produces a single-sideband chirp while suppressing the backscattered carrier by 10 dBm.Source: Figure 4 · p. 3
- The eight-load RF switch network costs 7.5 euros, while seven SPDT switches offer a lower-cost option at 1.4 euros total.Source: §V · p. 3
- Further research could examine IQ-modulator architectures and whether simple microcontroller solutions can reach the required sample rates.Source: §V · p. 3