Power-MSE trade-off of Factorized Low-rank Approximated Computation Scheme with Memristors

1. INTRODUCTION

• Prior work left open how to add conductance scaling to FLAS and whether it would consume less power than baseline VMM.Earlier FLAS improved accuracy through low-rank factorization and stage-wise averaging, but did not address conductance scaling or power.Source: §1 · p. 1
• FLAS uses low-rank factorization and stage-wise averaging to improve VMM accuracy.In a memristor crossbar, matrix entries are represented by conductances, row voltages encode the input, and column currents perform parallel multiply-and-accumulate operations.Source: §1 · p. 1
• The paper extends FLAS with adjustable column-wise conductance scaling, derives closed-form MSE and power expressions, and jointly optimizes rank, replication, and scaling.The optimization minimizes power under an MSE tolerance, memristor-count budget, and conductance-scaling bounds, producing a power–MSE Pareto frontier as the tolerance varies.Source: §1 · p. 1
• The paper is organized around the crossbar model, baseline and FLAS MSE/power analyses, and numerical power–MSE trade-off examples.The power decomposition is also used to examine how TIA feedback resistance affects FLAS's relative advantage.Source: §1 · p. 1

2. SYSTEM MODEL

• A memristor crossbar implements c = bA by applying the input as row voltages and reading column outputs through TIAs.The TIA feedback resistance is rT.Source: §2 · p. 1
• Column-wise scaling fits matrix entries into the reliable conductance range using adjustable upper target conductances.The model assumes the input magnitude is within the allowable voltage amplitude and that each matrix column has a nonzero maximum absolute entry.Source: §2 · pp. 1–2
• Signed matrix entries use positive and negative crossbars whose currents are subtracted, canceling the common conductance offset under differential readout.The resulting output is rescaled to recover the VMM result.Source: §2 · p. 2
• Programmed conductances are modeled with additive, zero-mean programming noise that is independent across memristors and crossbars.The noisy conductances induce an effective noise matrix in the baseline VMM output.Source: §2 · p. 2

3. MSE AND POWER ANALYSIS FOR BASELINE

• Baseline total mean power is decomposed into memristor and TIA contributions, with separate expressions for each component.The component results are combined into the total-power expression in Theorem 2.Source: §3 · pp. 2–3
• The analysis assumes deterministic input and matrix, takes expectations only over programming noise, and uses separate TIAs for positive and negative crossbars at each output.The mean memristor-power derivation sums contributions across rows and columns; the TIA expression is given for all 2n TIAs.Source: §3 · pp. 2–3
• The baseline aggregate MSE follows from output errors caused by programming noise, with cross terms vanishing under the assumed independence.The paper defines aggregate output MSE as its accuracy measure and states the baseline MSE expression in Theorem 1.Source: §3 · p. 2

4.1. Extended FLAS of VMM

• Two successive VMMs implement the rank-k factorization, with replicas whose averaged outputs suppress programming errors under the same hardware budget.The factors are mapped to separate crossbar pairs with adjustable column-wise conductance scaling.Source: §4.1 · p. 3, §4 · p. 3

4.2. Second-stage input statistics

• Deterministic second-stage input statistics include the contribution from first-stage programming noise and require only independence and the first two noise moments.The statistics include the second-stage input's noise covariance and second moment.Source: §4.2 · p. 4

4.3. MSE of FLAS

• The aggregate FLAS MSE accounts for interaction between the two stages’ programming noises through the expected squared norm of the second-stage input.The theorem's derivation uses the zero-mean and independence properties of the stage noises to eliminate cross terms.Source: §4.3 · p. 4

4.4. Power consumption analysis of FLAS

• The aggregate FLAS power is the sum of four component mean powers covering first- and second-stage memristors and TIAs.The section separately gives propositions for first-stage memristor and TIA power, and second-stage memristor and TIA power.Source: §4.4 · pp. 4–5

5.1. Optimization Problem

• The baseline problem minimizes power subject to an aggregate MSE tolerance and conductance bounds, and its convex formulation can be solved globally whenever feasible.The FLAS problem jointly selects rank, replication counts, and scaling factors under MSE, memristor-budget, and scaling constraints; the mixed-integer search enumerates feasible rank-and-replication triples and optimizes scaling for each.Source: §5.1 · p. 5
• Tightening the MSE tolerance cannot decrease optimal power because it shrinks the feasible set.Varying the tolerance traces the power–MSE trade-off.Source: §5.1 · p. 5

5.2. Numerical results

• FLAS reduces power by 61.7% for fast decay and 32.5% for moderate decay at marked operating points, but baseline uses less below NMSE 0.074 for moderate decay.The comparisons use a common memristor budget; the marked savings occur without replication.Source: §5.2 · p. 5, Figure 2 · p. 6
• For moderate decay, NMSE 0.10 gives FLAS the smaller TIA power fraction, while at NMSE 0.06 baseline has the smaller fraction.As feedback resistance increases, the relative total-power advantage grows for whichever scheme has the smaller TIA fraction.Source: §5.2 · pp. 5–6, Figure 3 · p. 6

• The paper extends FLAS with adjustable conductance scaling and analyzes its power–MSE trade-off against baseline VMM.Source: §6 · p. 6
• FLAS's power advantage over baseline depends on matrix spectral decay and MSE.Source: §6 · p. 6
• TIA power fractions explain how the advantage changes with feedback resistance.Source: §6 · p. 6