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An Open-Source Standard-Cell Library for IHP 130nm Developed by Students
Oscar Castañeda, Lavinia Recchioni, Tobias Senti, Flurin Cahenzli, Marco Ferroni, Thorben Heekenjann, Robert Kenter, Stefan Odermatt, Daniel Richner, Gabriel Altendorfer, Davide Cannone, Miguel Correa, Ivan Herger, Lars Kröger, Nicolas Nanzer, Darja Nonaca, Christopher Reinwardt, Lukas Winklhofer, Enrico Zelioli, Yiheng Zhang, Yingxue Zhang, Domenic Keller, Seyed Hadi Mirfarshbafan, Zerun Jiang, Beat Muheim, Arianna Rubino, Jérémy Guichemerre, Frank K. Gürkaynak, Christoph Studer
TL;DR
Digital VLSI courses rarely let students design, characterize, and integrate their own standard cells, and proprietary PDKs limit sharing and reproduction of course infrastructure and student-created libraries. VLSI 5 has students design, lay out, characterize, and integrate custom standard cells using IHP’s open-source SG13G2 process. EZ130 8T v1.1 is within 120 ps of SG13G2 in clock period for all benchmarks; it reduces area by 35% and energy consumption by 39% at a 3% larger period.
Problem
Digital VLSI courses rarely let students design, characterize, and integrate their own standard cells, and proprietary PDKs limit sharing and reproduction of course infrastructure and student-created libraries.
Source: §I · p. 1Method
VLSI 5 has students design, lay out, characterize, and integrate custom standard cells using IHP’s open-source SG13G2 process.
Source: Contributions · p. 1Results
EZ130 8T v1.1 is within 120 ps of SG13G2 in clock period for all benchmarks; it reduces area by 35% and energy consumption by 39% at a 3% larger period.
Source: C. Synthesis Results · p. 4, D. Place-and-Route Results · p. 4Takeaways & Limitations
The student-created EZ standard-cell library is released as an open library and is available at ez.ethz.ch.
Source: D. Course Results · p. 3
Abstract
from arXiv · showhide
Standard-cell libraries form the critical interface between transistor-level circuit design and automated digital design flows, yet their design and characterization are rarely covered in depth in digital VLSI courses. This paper presents VLSI 5, a graduate-level course at ETH Zurich in which students design, lay out, characterize, and integrate their own standard cells using IHP's open-source 130nm SG13G2 process design kit. In the first course offering, 19 students developed EZ130 8T, an open-source eight-track standard-cell library comprising 220 cells. We evaluate successive library versions using eight synthesis benchmarks, across which EZ130 8T achieves significant area reduction compared to the SG13G2 library at competitive timing. For a postlayout 8x8 matrix-vector multiplier, EZ130 8T reduces cell area by 35% and energy by 39% while maintaining virtually the same clock period. The library has already been adopted in other ETH Zurich VLSI courses, enabling the creation of chips entirely designed by students down to the transistor level.
I. INTRODUCTION
Standard-cell design and characterization are rarely integrated into digital VLSI courses, and proprietary PDKs constrain sharing and reproduction. VLSI 5 addresses this gap with a student-built open-source library for IHP SG13G2.
I. INTRODUCTION
- Few courses let students design, characterize, and integrate their own cells, while proprietary PDKs limit sharing and reproducibility of course infrastructure and student-created libraries.Open PDKs for foundry processes, including SG13G2, make educational artifacts shareable, reproducible, and fabricable.Source: §I · p. 1
- 19 students developed EZ130 8T, an open-source eight-track standard-cell library with 220 cells for IHP’s open-source 130 nm SG13G2 process.The course has students design, lay out, characterize, and integrate their cells into a digital IC design flow.Source: Contributions · p. 1
Contributions:
- The open-source EZ130 8T standard-cell library is available at ez.ethz.ch.The paper identifies the library as a student-developed course artifact.Source: Contributions · p. 1
A. Course Context
VLSI 5 completes ETH Zurich’s course sequence by connecting transistor-level design with HDL-based digital IC design. Students learn custom-cell design and characterization through paired instruction and practical tutorials, followed by a project.
A. Course Context
- Earlier courses covered HDL synthesis, back-end design, testing, and transistor-level foundations, but did not connect students’ transistor-level work to HDL designs.The earlier courses prepared students to design, fabricate, and test their own ICs.Source: A. Course Context · pp. 1–2
- VLSI 5 fills a remaining gap in ETH Zurich’s course sequence: students had no course for interfacing transistor-level designs with high-level HDL designs.The course was designed in 2025 after VLSI 3 introduced MOSFET, CMOS, standard-cell design, and digital-layout foundations.Source: A. Course Context · p. 2
B. Course Organization
- Master’s students learn to design and characterize custom standard cells and generate LIB, LEF, Verilog, SPICE/CDL, and GDSII files for design-flow integration.The course runs weekly for 12 weeks, totals 4 ECTS, and is ungraded with pass/fail outcomes.Source: B. Course Organization · p. 2
- The first six weeks pair theoretical lectures with hands-on tutorials, and the final six weeks are devoted to the course project.Tutorials cover generating interface files from cell schematics and layouts and integrating cells into a digital IC design flow.Source: B. Course Organization · p. 2
C. Course Project
The course project required each student to create and validate new standard cells, with starter materials and weekly review supporting the work. Instructors progressively automated checks and compiled student datasheets into a library datasheet.
C. Course Project
- Each student had to create six cells, including schematic and layout design, functional and physical characterization, file generation, and digital-flow integration checks.The flow used commercial tools for synthesis, back-end design, physical verification, and functional verification.Source: C. Course Project · p. 2
- A 39-cell seed library, layout templates, reference HDL designs, and automation scripts gave students a starting point; weekly submissions received instructor review and corrections.Each student implemented six cells distinct from their peers’ assignments, prompting personalized in-class feedback.Source: C. Course Project · p. 2
- Instructors developed scripts and custom DRC decks to automate most checks, then combined student-created cell datasheets into the complete library datasheet.At first, most cell evaluation was performed manually.Source: C. Course Project · p. 2
D. Course Results
The first VLSI 5 offering produced an open standard-cell library from student work and received positive course evaluations. Its reported results include the number of students and cells created, alongside example cell layouts.
D. Course Results
- The paper includes layouts of two example standard cells from the EZ130 8T library.The figure caption identifies them as example standard-cell layouts.Source: Figure 3 · p. 3
- 19 students took the first offering, and the students created 164 cells—more than the 114 required—with course satisfaction rated 4.7 out of 5.0, far above the department average.The number of students was limited because it was the first offering and required highly personalized feedback; one student created 40 additional cells.Source: D. Course Results · pp. 2–3
- The students’ cells were released, with their consent, as the open standard-cell library EZ.EZ is short for ETH Zurich.Source: D. Course Results · p. 3
III. THE EZ130 8T OPEN STANDARD-CELL LIBRARY
EZ130 8T is a 220-cell, eight-track library designed for IHP’s open-source SG13G2 process. Its specification spans routing and cell geometry as well as a broad range of logic and physical cells.
A. Technical Specifications
- The 220-cell library combines 39 seed cells, 164 student-created cells, and additional instructor-created cells.Cells are designed for SG13G2 on a 0.42 µm grid, at an eight-track height of 3.36 µm.Source: A. Technical Specifications · p. 3
- Metal 1 is the only routing layer used within cells; well taps are separate dedicated cells rather than integrated beneath each cell’s power rails.Cell pins are placed on grid points, with Metal 1 and Metal 3 routing grids aligned.Source: A. Technical Specifications · p. 3
- The library includes combinational and sequential logic, physical cells, and gates with up to four inputs across monolithic CMOS topologies.It also includes non-monolithic gates, tristate cells, flip-flops, latches, clock gates, fillers with decoupling, antenna diodes, and tie cells.Source: A. Technical Specifications · p. 3
- Most cells are available in X1 and X2 strengths, while buffers and inverters reach X64.X2 NMOS and PMOS widths are 0.64 µm and 0.98 µm, respectively.Source: A. Technical Specifications · p. 3
B. Benchmarks
The benchmark suite covers arithmetic, stateful, combinational-logic, memory, and signal-processing designs. It combines quick-to-evaluate cases with more complex applications.
B. Benchmarks
- Benchmarks were chosen to permit quick evaluation while covering a meaningful, broad range of use cases.The more complex designs were included for comprehensive applications despite slower implementation.Source: B. Benchmarks · p. 3
- The arithmetic and state benchmarks include a registered 32-bit adder, a registered signed 32-bit-by-32-bit multiplier, a resettable or disableable 24-bit counter, and ten 24-bit registers in series.The multiplier has a registered 64-bit output; the adder discards its carry-out.Source: B. Benchmarks · p. 3
- The suite also includes a random 256-entry, 8-bit LUT synthesized as combinational logic and a registered-input/output latch array storing 32 words of 32 bits.The latch array follows.Source: B. Benchmarks · p. 3
- More complex cases include a fully unrolled, multiplierless 64-point radix-4 FFT and the 8×8 matrix-vector multiplier.The FFT uses complex-valued 7-bit inputs and an architecture from; these slower-to-implement designs support more comprehensive evaluation.Source: B. Benchmarks · p. 3
- The matrix-vector multiplier fully unrolls eight complex-valued inner-product engines to compute one 8×8 product per clock cycle.Each engine pointwise multiplies two complex vectors with eight 8-bit entries and sums the partial products.Source: B. Benchmarks · p. 3
C. Synthesis Results
Across eight benchmarks, EZ130 8T v1.1 approaches SG13G2 timing while retaining the library’s smaller synthesized area. The comparison uses Pareto-optimal area–clock-period results across successive library versions.
C. Synthesis Results
- The synthesis comparison spans eight benchmarks and sweeps clock constraints to find Pareto-optimal area and achievable-clock-period designs.The reported envelope selects the lowest-area design at a given period or the lowest-period design at a given area.Source: C. Synthesis Results · p. 3
- The comparison tracks the 39-cell seed library through weekly accepted-cell additions to semester-end v1.0 and lecturer-optimized v1.1, against SG13G2 revision 0.1.4.SG13G2 has 84 cells; it was re-characterized with the authors’ Cadence Liberate flow for comparison.Source: C. Synthesis Results · p. 3
- Within 120 ps of SG13G2’s clock period on all benchmarks, EZ130 8T v1.1 retains the smaller-area trend as successive versions become smaller and overall faster.The initial v0 library is already smaller after synthesis than SG13G2, though slower.Source: Figure 4 · p. 4, C. Synthesis Results · p. 4
D. Place-and-Route Results
For the 8×8 matrix-vector multiplier, EZ130 8T v1.1 reduces area and energy relative to SG13G2, with a slightly larger clock period. The reported area-delay-energy product is also smaller.
D. Place-and-Route Results
- Place-and-route evaluates the lowest-area-delay-product synthesized netlist, sweeping clock constraints in 100 ps steps at 50% density across TT, FF, and SS corners.The reported clock period is met across all three corners; energy is evaluated at TT using a fixed random matrix and 100 random input vectors.Source: D. Place-and-Route Results · p. 4
- 35% less area and 39% less energy, at a 3% larger clock period, give EZ130 8T a 59% smaller area-delay-energy product than SG13G2.The authors attribute the area and energy savings to smaller transistors.Source: D. Place-and-Route Results · p. 4
IV. CONCLUSIONS
VLSI 5 teaches students to create standard cells and integrate them into a digital design flow, producing an open-source library for IHP’s SG13G2 process. The library achieved smaller area and lower energy than SG13G2 in a matrix-vector multiplier, and its cells were used in peer-designed chips.
IV. CONCLUSIONS
- 35% smaller area and 39% lower energy than the SG13G2 library, at the same speed, in post-layout matrix-vector multiplier results.The course’s EZ130 8T library was used in the comparison.Source: §IV · p. 4
- EZ130 8T cells were adopted in VLSI 2, where students implemented and taped out ICs using cells created by their peers.The authors report that every component in those ICs was designed by students.Source: §IV · p. 4
- Two chips using EZ130 8T cells, one with v0 and one with v0.12, returned from fabrication and passed initial tests; complete characterization remains ongoing.Source: §IV · p. 4
- VLSI 5 teaches custom-cell design and integration within a digital IC flow, and the course was offered again in spring 2026 after a positive student reception.It is part of a course sequence spanning physical devices through IC design, implementation, and testing.Source: §IV · p. 4