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GRACIDIT: Graph-Circuit Digital Twin for Configuration-Induced Routing Delay Prediction in Zynq UltraScale+ FPGAs

Mostafa Darvishi

arXiv:2609.30534v1eess.SYcs.ARcs.ETcs.SYeess.SP

TL;DR

Existing approaches do not jointly predict delay from dormant routing attachments and assess the affected path’s slack. GRACIDIT combines device-native routing graphs, calibrated electrical modeling, and hardware measurements to estimate vulnerability. On the representative XCZU7EV dataset, it reports a held-out MAE of 7.8 ps and Recall@10 of 0.90.

  • Problem

    Existing methods do not jointly identify candidate inactive branches, predict their delay distributions, and account for the affected path’s available slack.

    Source: §I · p. 2

  • Method

    The framework extracts XCZU7EV routing graphs, models dormant branches with a calibrated reduced-order electrical representation, and combines predicted delay with slack and hardware calibration.

    Source: §I · p. 2, B. Graph-to-Circuit Transformation · p. 10, §VII · p. 24

  • Results

    For the representative XCZU7EV dataset, the model achieved a held-out MAE of 7.8 ps and Recall@10 of 0.90.

    Source: §VII · p. 24

  • Takeaways & Limitations

    The resulting PIP-, net-, frame-, and region-level vulnerability scores can support targeted monitoring, selective scrubbing, reliability-aware routing, and adaptive route recovery.

    Source: §VII · p. 24

    The model is specific to the locked XCZU7EV device and Vivado release, and transfer to another UltraScale+ part requires graph re-extraction and partial electrical recalibration.

    Source: J. Discussion and Limitations · p. 24

Abstract

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Configuration-induced perturbations in SRAM-based FPGAs may activate dormant programmable routing branches and increase path delay without immediately producing a functional error. Although prior studies have separately investigated the electrical origin of these delay changes, their in-situ detection, and the topology of commercial routing fabrics, a scalable method for predicting their timing impact at the granularity of programmable interconnect points and routed nets remains unavailable. This paper presents GRACIDIT, a graph-circuit digital twin framework for predicting configuration-induced routing delay degradation in Zynq UltraScale+ FPGAs. The proposed framework extracts the routing-resource graph of the XCZU7EV programmable fabric from the vendor design database, identifies inactive programmable interconnect points adjacent to active routes, and represents each candidate perturbation through its branch topology, geometric span, fan-out, physical region, and downstream loading. These graph features are combined with a calibrated reduced-order electrical model to estimate the delay introduced by single and cumulative routing-branch activations. Controlled configuration-equivalent perturbations are generated on a ZCU104 platform and characterized using complementary routing-domain oscillators and phase-sweep probes. The resulting model associates predicted delay shifts with available timing slack to rank vulnerable programmable interconnect points and routed nets and to construct a spatial vulnerability atlas of the programmable fabric. Experimental evaluation demonstrates a mean absolute prediction error of 7.8 ps, achieves 87.4 percent recall for slack-violating perturbations, and attains a Recall at 10 value of 0.90 for the most vulnerable routing resources.

I. INTRODUCTION

Configuration changes can add parasitic routing branches and delay without changing intended logic, but existing tools do not predict each branch’s delay impact against path slack. GRACIDIT combines device-native routing topology, calibrated electrical modeling, and hardware measurements to assess this timing vulnerability.

A. Configuration-Memory Upsets and Routing-Delay

  • An activated dormant routing branch can add parasitic capacitance and switch or downstream loading while leaving intended logic apparently unchanged.Prior circuit, monitoring, and irradiation work establishes routing-delay degradation as a measurable failure precursor.Source: §I · p. 1, A. Configuration-Memory Upsets and… · p. 3

I. INTRODUCTION

  • Existing methods do not jointly identify harmful inactive PIPs, predict their delay increments, and compare those increments with path slack.Monitoring detects shifts after implementation or during operation, while circuit simulation does not scale across the many resources around a design.Source: §I · p. 2
  • The paper introduces a graph–circuit digital twin that extracts XCZU7EV active routes and neighboring inactive PIPs, then predicts delay from graph features and a calibrated electrical model.The model addresses single and cumulative branch activations using controlled configuration-equivalent perturbations and complementary hardware measurements.Source: §I · p. 2

A. Configuration-Memory Upsets and Routing-Delay

  • Controlled configuration-equivalent perturbations reproduce routing-attachment loading deterministically, but are not claimed to be radiation-induced events.Prior fault-emulation work motivates explicit validation of configuration effects and observed failure modes.Source: A. Configuration-Memory Upsets and… · p. 4

B. In-Situ Timing Observation and Timing-Error Resilience

  • In-situ timing monitors detect or tolerate timing errors but do not identify the dormant routing resource or rank vulnerable routes before deployment.Monitor loading and resolution vary with physical distance, and routing-dominated oscillators measure aggregate loop changes rather than localizing a path segment.Source: B. In-Situ Timing Observation and… · p. 4
  • Ring oscillators provide sensitive aggregate calibration measurements, while phase-swept monitors provide path-local timing displacement for the predeployment predictor.Neither channel serves as the final vulnerability indicator.Source: B. In-Situ Timing Observation and… · p. 4

C. Routing-Architecture Representation and Commercial-

Commercial routing graphs expose connectivity and physical context, while reliability-aware CAD generally targets functional-failure metrics rather than continuous delay impact. The paper combines device-native graph extraction with path slack and calibrated electrical prediction for design-time vulnerability assessment.

C. Routing-Architecture Representation and Commercial-

  • Commercial routing graphs expose connectivity, direction, fan-in, fan-out, and spatial diversity, but do not assign delay consequences to activating specific dormant branches.The proposed method pairs XCZU7EV graph extraction with electrical parameters calibrated on that device.Source: C. Routing-Architecture Representation… · pp. 4–5

D. Reliability-Aware FPGA Physical Design

  • Prior reliability-aware CAD targets configuration-bit sensitivity, functional failure probability, bridging-fault exposure, or redundancy, rather than differentiating nonfunctional perturbations by delay magnitude.The distinction matters because two such perturbations may add very different amounts of delay.Source: D. Reliability-Aware FPGA Physical… · p. 5
  • Timing-vulnerability assessment requires candidate branches, their delay distributions, and the affected synchronous path’s available slack.Without all three, structural exposure may overstate risk while near-critical paths may be underestimated.Source: D. Reliability-Aware FPGA Physical… · p. 5

III. ULTRASCALE+ ROUTING AND CONFIGURATION PERTURBATION MODEL

  • The formulation separates implemented routes, inactive resources that can attach to them, and path-specific timing margin.The target is the ZCU104 board with an XCZU7EV device, and extraction obtains physical-resource relationships from the vendor database.Source: §III · p. 6, A. Target Fabric and Physical-Routing… · p. 6

A. Target Fabric and Physical-Routing Objects

  • The device graph represents routing nodes and terminals, programmable PIP edges, fixed connections, and physical attributes including location, region, displacement, fan-in, and fan-out.The scope is the programmable-logic interconnection network; the processing system is used for experiment control and data acquisition.Source: A. Target Fabric and Physical-Routing… · p. 6

B. UltraScale+-Native Routing Taxonomy

GRACIDIT derives routing classes from the UltraScale+ fabric rather than transferring older-device taxonomies. It analyzes sink-specific routes and enumerates electrically visible dormant branches while excluding candidates that do not meet the delay-only criteria.

B. UltraScale+-Native Routing Taxonomy

  • The taxonomy is derived from extracted graph descriptors because vendor names alone may omit geometric span, secondary destinations, or spatial variation.Older-device resource classes are not transferred to UltraScale+.Source: B. UltraScale+-Native Routing Taxonomy · p. 6
  • The UltraScale+-native taxonomy groups routing resources by local junction, geometric wire, terminal, and spatial-context classes.This hierarchy supports region-specific correction without fragmenting calibration across thousands of vendor-specific wire names.Source: B. UltraScale+-Native Routing Taxonomy · p. 6

C. Active Routes and Sink-Specific Path Representation

  • Perturbation analysis is sink-specific because shared-trunk attachments can affect several sinks, while attachments beyond a branch point affect only downstream sinks.The extraction records route resources, shared branch points, pins, delays, slack, clock context, route composition, and incident inactive PIPs.Source: C. Active Routes and Sink-Specific… · p. 7

D. Dormant-Branch Candidate Enumeration

  • A dormant-branch candidate attaches an otherwise unused routing component to an active signal path while preserving the intended source-to-sink connection.Candidates are filtered by electrical visibility: passive or bidirectional resources are retained when they expose branch impedance, while directionally buffered resources that prevent loading are rejected.Source: D. Dormant-Branch Candidate Enumeration · p. 7
  • Dormant components are extracted by deterministic breadth-first traversal, with expansion stopping at terminals, active resources or drivers, isolation boundaries, or a depth limit.The fixed limit is eight routing hops; increasing it to 12 changes retained branch descriptors by less than 1.8%.Source: D. Dormant-Branch Candidate Enumeration · p. 7
  • The delay-only candidate scope excludes open PIPs, shorts between driven nets, logic-function corruption, and state-element upsets.Candidates preserve intended routing and avoid shorting another actively driven net.Source: D. Dormant-Branch Candidate Enumeration · p. 7

E. Single and Cumulative Perturbation Classes

The model distinguishes dormant-branch activations by topology, from single attachments to parallel and serial cumulative perturbations. Cumulative delay is evaluated on the combined attached structure rather than assumed to equal the sum of isolated effects.

E. Single and Cumulative Perturbation Classes

  • Four perturbation classes distinguish single leaf, single loaded, parallel cumulative, and serially extended cumulative attachments.A single loaded attachment can expose downstream configured junctions or terminal loads even though only one new PIP is activated.Source: E. Single and Cumulative Perturbation… · p. 8
  • Serial extension makes additional downstream resources electrically relevant, so cumulative delay is evaluated as a unified structure rather than summed from isolated PIP effects.Attachment locations, shared wires, distributed resistance, transition slew, and combined-network topology shape branch interactions.Source: E. Single and Cumulative Perturbation… · p. 8

F. Configuration-State and Frame Association

  • PIP-to-configuration mapping is established through controlled differential builds, with repeated state changes, route reversal, locked unrelated resources, readback, and consistent behavior used as checks.The mapping does not assume a one-to-one correspondence between a PIP and a configuration bit.Source: E. Single and Cumulative Perturbation… · p. 8
  • The mapping covers only PIPs needed for calibration and validation; complete XCZU7EV bitstream reverse engineering is not required.UltraScale+ frames contain 93 32-bit words, but frame organization alone does not identify which PIP a bit controls.Source: E. Single and Cumulative Perturbation… · pp. 8–9

G. Timing-Failure Condition

Timing risk depends on whether a perturbation exhausts sink-specific slack, not on delay increase alone. The model is bounded to persistent configuration changes that preserve the intended route, and its device-specific digital twin predicts delay and slack-related outcomes.

G. Timing-Failure Condition

  • A 100 ps delay increase can be harmless with 1 ns slack but critical with 20 ps, so perturbation severity depends on both delay and available slack.Ranking by nominal slack alone also overlooks differences in adjacent dormant-branch structure.Source: G. Timing-Failure Condition · p. 9

H. Model Scope and Assumptions

  • The modeled perturbation is persistent until configuration correction or reconfiguration; transient pulses, opens, and contention between active drivers are outside scope.PIP association is selected rather than exhaustive, and database extraction is tied to the locked target part and Vivado release.Source: H. Model Scope and Assumptions · pp. 9–10
  • Fig. 2's single shared-trunk attachment can affect both sink paths, while a post-fan-out attachment primarily affects its sink-local route.Parallel attachments may load different route portions; serial extension can expose a larger component whose delay is not generally the sum of isolated effects.Source: H. Model Scope and Assumptions · p. 10

IV. PROPOSED GRAPH–CIRCUIT DIGITAL TWIN

  • GRACIDIT is an offline, device-specific, measurement-calibrated surrogate that predicts delay increment, residual slack, prediction interval, and slack-exhaustion probability for sink-specific perturbations.Its parameters are updated when new calibration data are incorporated.Source: §IV · p. 10

A. Model Inputs and Prediction Outputs

The twin combines sink-specific route and attached-component graphs with timing and physical context, then transforms the topology into an effective RC circuit. It estimates perturbation delay from the change between reference and perturbed networks.

A. Model Inputs and Prediction Outputs

  • Inputs combine the active sink-specific route, attached dormant component, nominal post-route timing quantities, and route operating and physical context.Timing quantities come from the same implemented checkpoint used to construct the routing graph.Source: A. Model Inputs and Prediction Outputs · p. 10
  • Descriptors encode branch topology, geometry, reachable loads, physical context, and STA quantities; outputs include delay increment, residual slack, failure probability, and a prediction interval.The context includes clock region, neighboring resource type, congestion, voltage, temperature, and transition polarity.Source: A. Model Inputs and Prediction Outputs · p. 10

B. Graph-to-Circuit Transformation

  • The graph-to-circuit transformation uses extracted topology with UltraScale+-calibrated electrical parameters, attaching the dormant component without replacing or interrupting the intended route.Effective resistance and capacitance represent routing-class span, PIP switch resistance, junction loading, and terminal or downstream loads; these are not reconstructions of proprietary device dimensions.Source: B. Graph-to-Circuit Transformation · pp. 10–11
  • For tree-structured RC networks, the model uses the Elmore first-moment delay and computes perturbation delay as the difference between perturbed and reference moments.Capacitance nearer the source is weighted by more shared upstream resistance, and non-tree networks are evaluated using modified nodal analysis.Source: B. Graph-to-Circuit Transformation · p. 11

C. Physics-Informed Residual Correction

The framework corrects its reduced-order RC prediction for secondary physical effects, calibrates parameters with grouped validation, and combines two complementary measurement channels while retaining their separate estimates.

C. Physics-Informed Residual Correction

  • A low-dimensional residual correction addresses secondary effects that the reduced-order RC model cannot recover exactly, including slew, buffer strength, junction capacitance, PVT dependence, and regional variation.The graph-circuit and residual contributions are reported separately, and the correction calibrates the physical model to UltraScale+ rather than scaling 7-Series values.Source: C. Physics-Informed Residual Correction · pp. 11–12

D. Parameter Calibration

  • Calibration uses grouped 5-fold cross-validation by physical route group and tests in-class, cross-region, and cross-class validation regimes.Repeated observations of the same route–sink–perturbation tuple remain in one subset, avoiding testing on a route effectively identical to training data.Source: D. Parameter Calibration · p. 12

E. Fusion of the Two Measurement Channels

  • Routing-dominated oscillators and phase-swept path monitors provide complementary observations, and their fusion accounts for covariance when channel errors are not negligible.The two raw channel estimates are retained so fusion does not conceal systematic disagreement.Source: E. Fusion of the Two Measurement… · p. 12

F. PVT and Spatial Normalization

Paired measurements and hierarchical spatial normalization account for operating-point and region-dependent effects. Prediction uncertainty is estimated from grouped model resampling and used to assess slack exhaustion without assuming Gaussian errors.

F. PVT and Spatial Normalization

  • Paired reference and perturbed measurements suppress common-mode clock, supply-voltage, and temperature variation, while remaining PVT dependence is modeled relative to a nominal operating point.Spatial normalization uses routing-class behavior and a local-region correction only when it generalizes to held-out routes; otherwise, variation contributes to prediction uncertainty.Source: F. PVT and Spatial Normalization · p. 13

G. Prediction Uncertainty and Failure Probability

  • Grouped bootstrap resampling produces prediction intervals while keeping repeated measurements from the same reference–perturbation route group together.The model's uncertainty includes parameter estimation, repeatability, route-to-route variation, and PVT residuals.Source: G. Prediction Uncertainty and Failure… · p. 13
  • Slack-exhaustion probability is estimated from the prediction ensemble without requiring Gaussian prediction errors, including when uncertainty is asymmetric.The probability evaluates whether a perturbation exhausts nominal path slack.Source: G. Prediction Uncertainty and Failure… · p. 13

H. Candidate and Net-Level Vulnerability Scores

The framework distinguishes timing susceptibility from mission-level reliability risk and aggregates candidate vulnerability at net and spatial levels. Its atlas reports multiple quantities so candidate severity can be distinguished from candidate density.

H. Candidate and Net-Level Vulnerability Scores

  • When perturbation-occurrence information is unavailable, candidates are ranked using the structural score; when available, occurrence probability can be derived from device- and environment-specific reliability data.The combined reliability-weighted vulnerability assumes candidate events are sufficiently rare and conditionally independent.Source: H. Candidate and Net-Level… · p. 13
  • The candidate vulnerability score ranks routing attachments by the conditional probability that a perturbation exhausts a sink's nominal slack, not by the probability that the perturbation occurs.When occurrence probability is available, a reliability-weighted score combines occurrence probability with conditional slack-exhaustion probability.Source: H. Candidate and Net-Level… · p. 13
  • Net-level assessment reports maximum predicted delay increment, maximum conditional failure probability, exposed-PIP count, and configuration-frame associations to distinguish many low-severity candidates from one critical candidate.The score can be aggregated by physical attachment location for spatial analysis.Source: H. Candidate and Net-Level… · p. 14
  • The spatial atlas distinguishes total aggregated score, mean candidate severity, and normalized visualization, and supports display at tile, clock-region, frame, or user-defined-region granularity.Density normalization addresses the increase in summed score that can result simply from more candidates in a region.Source: H. Candidate and Net-Level… · p. 14

I. Computational Scalability

The workflow limits analysis to active-route neighborhoods and prunes cumulative perturbation exploration. Controlled paired implementations and configuration changes are used to generate and validate routing perturbations while preserving the intended route.

I. Computational Scalability

  • Device-graph extraction is linear in exported vertices and edges, and candidate enumeration traverses active-net neighborhoods rather than repeatedly analyzing the full device.Individual perturbation evaluation is linear in the active-path prefix and attached component; cumulative exploration is pruned to physically related branches and highly ranked candidates.Source: §I · pp. 14–15

V. EXPERIMENTAL METHODOLOGY

  • The automated experimental flow preserves placement, intended routing, clocking, and logic while repeating evaluations across routing classes and physical regions.It records implementation details and automates synthesis through routing extraction, bitstream generation, and report collection.Source: §V · p. 15

B. Test-Route and Perturbation Generation

  • Perturbations are generated as paired legal implementations with a preserved dummy endpoint, while confirmed PIP-to-configuration associations enable a separate direct-configuration validation subset.Direct configuration changes are restricted to isolated test regions, and the intended active route remains fixed in both mechanisms.Source: B. Test-Route and Perturbation… · p. 16

C. Configuration Association and Readback Verification

Configuration differences are verified by readback and assigned confidence levels, with only confirmed associations used for direct validation and exposure-weighted estimates. Phase-swept measurements and paired acquisitions provide complementary timing observations while controlling environmental drift.

C. Configuration Association and Readback Verification

  • Readback compares each configuration pair with its generated bitstream, and associations are classified as confirmed, probable, or unresolved according to repeatability and separability.Only confirmed associations support direct dangling-branch validation and exposure-weighted vulnerability estimation.Source: C. Configuration Association and… · p. 16

E. Phase-Swept Path Monitor

  • The phase-swept path monitor estimates perturbation delay from the difference between fitted reference and perturbed transition phases, using an experimentally calibrated phase-to-time conversion.The monitor uses a local replica to reduce observation-side disturbance.Source: E. Phase-Swept Path Monitor · p. 17

F. Environmental Control and Measurement Sequencing

  • Alternating reference–perturbation acquisitions suppress gradual thermal or supply drift, and restoration checks verify recovery of nominal timing response.Pairs with unresolved drift, incomplete restoration, or unstable measurement behavior are excluded from calibration.Source: F. Environmental Control and… · pp. 17–18

G. Dataset Partitioning and Evaluation Protocol

The evaluation partitions measurements by physical route group to test generalization across routing classes, regions, cumulative perturbations, and designs. It reports repeatable, cross-channel measurements and held-out prediction accuracy across three perturbation classes.

G. Dataset Partitioning and Evaluation Protocol

  • Route groups—not individual observations—are assigned to training, validation, and test sets, keeping repeated measurements of each physical route together and preventing leakage across splits.Evaluation includes in-class, cross-region, cross-class, cumulative, and design-level testing.Source: G. Dataset Partitioning and Evaluation… · p. 18

A. Experimental Dataset and Routing Coverage

  • The dataset contains 144 reference routes and 864 candidates across nine physical regions, with 612 single-branch, 144 parallel cumulative, and 108 serially extended perturbations retained.The study collected 9720 paired hardware observations at nominal and selected voltage–temperature conditions.Source: A. Experimental Dataset and Routing… · p. 18
  • Candidate branches spanned local and long routing resources and attachment locations along source-to-sink paths; confirmed PIP-to-configuration associations covered 63.1% of extracted route pairs.Only confirmed associations contributed configuration exposure to the vulnerability score; topology-calibrated candidates remained eligible for delay evaluation when routes and branches were unambiguous.Source: A. Experimental Dataset and Routing… · pp. 18–19

B. Repeatability and Cross-Channel Agreement

  • Oscillator frequency variation had a median within-pair coefficient of variation of 0.031%, while phase-boundary locations had a median standard deviation of 3.8 ps across repeated sweeps.After restoring the reference configuration, 96.9% of experiments returned within 4.1 ps of the initial response; failures of the reversibility criterion were excluded before calibration.Source: B. Repeatability and Cross-Channel… · p. 19
  • The oscillator and phase-monitor delay estimates correlated at 0.936, with a median absolute disagreement of 6.2 ps; inverse-variance fusion reduced median measurement uncertainty from 7.4 ps to 4.6 ps.The largest differences arose for long directional wires crossing clock-region boundaries, where the oscillator accumulated multiple loop instances while the phase monitor measured a sink-local path.Source: B. Repeatability and Cross-Channel… · p. 19
  • 7.8 ps MAE, 11.2 ps RMSE, and R^2 = 0.908 summarize held-out prediction accuracy across single-branch and cumulative perturbations.Fig. 5 compares measured and predicted delay increments and plots signed residuals.Source: Figure 5 · p. 20

C. Delay-Prediction Accuracy

The model predicts routing-delay increments with low error and calibrated uncertainty, while generalization weakens for unseen routing classes. Cumulative branches can interact non-additively, and slack-based prediction identifies timing risks that nominal critical-path ranking can miss.

C. Delay-Prediction Accuracy

  • 7.8 ps MAE, 11.2 ps RMSE, and R^2 = 0.908 were achieved across single-branch and cumulative perturbations.Cumulative perturbations extended toward larger delay increments; their residuals showed moderately greater dispersion than isolated branches.Source: C. Delay-Prediction Accuracy · p. 20
  • Adding constrained residual correction reduced MAE from 12.2 ps to 7.8 ps, an improvement of 36.1%.Ablating attachment-position features increased test MAE by 41.0%; removing routing-class descriptors increased it by 29.5%, and omitting nominal transition and STA context increased error by 17.9%.Source: C. Delay-Prediction Accuracy · p. 20

D. Prediction-Interval Calibration

  • 89.8% and 94.4% empirical coverage were achieved for nominal 90% and 95% prediction intervals, respectively.Intervals widened for unseen routing classes and regions excluded during calibration; random measurement splits yielded an apparently improved 5.4 ps MAE but overly narrow intervals.Source: D. Prediction-Interval Calibration · p. 20

E. Cross-Region and Cross-Class, and PVT Generalization

  • Cross-region MAE rose from 7.3 ps to 9.7 ps, while withholding an entire routing class yielded 14.1 ps MAE.Region corrections reduced systematic residuals near heterogeneous-resource boundaries from 8.6 ps to 2.9 ps; PVT correction reduced the maximum mean residual from 18.2 ps to 4.7 ps at 70°C and 0.825 V.Source: E. Cross-Region and Cross-Class, and… · p. 21, Figure 6 · p. 21

F. Single and Cumulative Perturbations

  • The complete attached-graph RC model reduced cumulative-candidate RMSE from 17.4 ps for the additive baseline to 10.1 ps.Median interaction was 0.047 for separated parallel branches and 0.192 for serially extended components.Source: F. Single and Cumulative Perturbations · p. 21

G. Slack-Exhaustion Prediction

  • At P_th = 0.50, slack-exhaustion prediction achieved 0.908 precision, 0.874 recall, and F1 = 0.890.Across application designs, 71.6% of analyzed sink paths had an adjacent dormant branch, but only 8.3% had a candidate with P_fail ≥ 0.50; some high-risk candidates were not on nominal longest-delay paths.Source: G. Slack-Exhaustion Prediction · p. 22

H. Design-Level Vulnerability Analysis

Across four XCZU7EV benchmarks, predicted vulnerability was concentrated in spatial hotspots that persisted after candidate-density normalization. The evaluation reports strong held-out delay prediction and top-candidate ranking, while the model and cumulative search remain bounded by device-specific calibration and structurally related perturbations.

H. Design-Level Vulnerability Analysis

  • Recall@10 was 0.90 and Recall@25 was 0.88 for identifying the most consequential routing resources; the RISC-V core had the highest fraction of candidates capable of exhausting slack.The RISC-V risk was concentrated primarily along tightly constrained control, forwarding, and pipeline-boundary paths.Source: H. Design-Level Vulnerability Analysis · p. 22
  • The raw atlas shows concentrated timing-risk hotspots, and the same dominant regions persist after normalization by candidate count, indicating the pattern is not explained solely by candidate density.The atlas aggregates candidate-level scores over the implemented benchmark set; Fig. 7 identifies 16 highest-risk configuration-frame locations and marks hotspots H1–H7.Source: H. Design-Level Vulnerability Analysis · p. 23, Figure 7 · p. 23

I. Runtime and Scalability

  • Millisecond-scale cumulative evaluation and submillisecond single-candidate prediction allow large routed designs to be screened without rerunning implementation.One-time device-graph extraction and model-fitting costs are reported as practical for offline analysis.Source: §I · p. 23

J. Discussion and Limitations

  • The model does not recover proprietary transistor-level interconnect; its effective resistance and capacitance parameters are identified from controlled hardware measurements.The reported model is specific to the locked XCZU7EV device and Vivado release; transfer to another UltraScale+ part requires graph re-extraction and partial electrical recalibration.Source: J. Discussion and Limitations · pp. 23–24
  • Cumulative search considers structurally related perturbations rather than every configuration-change combination because unrestricted enumeration is exponential.The retained cases cover physically relevant parallel and serial attachments likely to compound loading on the same active route.Source: J. Discussion and Limitations · p. 24

VII. CONCLUSION AND FUTURE WORK

  • On 864 XCZU7EV routing perturbations, held-out MAE was 7.8 ps, RMSE was 11.2 ps, R^2 was 0.908, slack-exhaustion F1 was 0.890, and Recall@10 was 0.90.The cumulative evaluation treats serially extended branches as unified graph–circuit structures rather than sums of isolated PIP effects.Source: §VII · p. 24
  • Candidate-level vulnerability scores can support targeted monitoring, selective scrubbing, reliability-aware routing, and adaptive route recovery.Spatial aggregation identifies concentrated vulnerability regions rather than treating configuration resources as uniformly critical.Source: §VII · p. 24
  • Future work will extend evaluation to additional UltraScale+ devices, incorporate measured configuration-bit upset cross sections, and validate under representative radiation environments.The authors also plan to integrate vulnerability scores into placement and routing objectives and investigate efficient multi-event analysis.Source: §VII · p. 24
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