Highly Scalable Selectorless Cryogenic Memory Array Using Ferroelectric Josephson Field-Effect Transistors

I. INTRODUCTION

• Memory kept at room temperature, far from millikelvin superconducting qubits, increases wiring, thermal leakage, latency, and wiring complexity.Large quantum algorithms also need memory for instructions, calibration data, intermediate results, and error correction.Source: §I · p. 1
• Emerging superconducting memories can pair density with circuit speed, but still require access devices for random access.Conventional superconducting memories also often rely on large cells, inductive coupling, transformers, or auxiliary junctions.Source: §I · p. 1
• Fe–JoFET gate-controlled polarization changes the channel between superconducting and resistive states, enabling nonvolatile storage and direct state identification without sensing circuitry.The superconducting channel supports high-speed, energy-efficient transport, while the ferroelectric gate provides voltage control.Source: §I · p. 1
• The proposed array uses Fe–JoFETs for nonvolatile, selectorless cryogenic memory, with a physics-based compact model developed to verify its functionality.The ferroelectric polarization stores state; the model combines polarization, superconducting, critical-current, and current-voltage descriptions.Source: §I · pp. 1–2
• During writes, all cells remain superconducting; during reads, only the accessed cell may become resistive for logic 1.The design is intended to minimize voltage drops and resistive dissipation and reduce the risk of disturbing unaccessed cells.Source: §I · p. 1

II. FE–JOFET AND DEVICE CHARACTERISTICS

• The Fe–JoFET is built on an InAs-on-insulator platform with an HfO2 ferroelectric gate and aluminum superconducting source and drain layers.The insulating stack includes GaAs, an InxAl1−xAs metamorphic buffer, and an intrinsically n-type InAs epilayer.Source: §II · p. 2
• Remnant polarization is set by the applied electric field across the ferroelectric layer, with opposite field polarities producing positive or negative polarization states.The field is described as E = −VGS/d, where VGS is gate-to-source voltage and d is ferroelectric thickness.Source: §II · p. 2
• Negative remnant polarization enhances InAs-channel electrons, whereas positive remnant polarization promotes charge trapping and depletes electrons.The negative-polarization state has higher critical current Ic and lower normal-state resistance RN than the positive-polarization state.Source: §II · p. 2
• The device’s measured characteristics include polarization, critical current, normal-state resistance, and current-voltage behavior; the cited validation device operated at 50 mK.The device used for the experimental data had a width of 5 µm and length of 600 nm; the work uses gate-voltage scans of [-3,3] V.Source: Figure 2 · p. 3, §II · p. 3

III. MODELING METHODOLOGY, VALIDATION, AND DESIGN SPACE EXPLORATION

• A Preisach model represents the device’s polarization-voltage hysteresis, with its parameters extracted from experimental data and used to calibrate the model.The polarization description uses saturation, remnant, and initial polarization values, plus the coercive field.Source: A. Methodology · p. 3
• The two remnant-polarization states change channel carrier density and critical temperature, producing distinct superconducting energy gaps.The gap is calculated using BCS theory; the critical temperature change follows from polarization-dependent carrier density.Source: A. Methodology · p. 3
• The model modifies the Ambegaokar–Baratoff equation to capture gate-voltage dependence of critical current Ic, using fitting parameters for that dependence.The gate-voltage offset is Vo; γ, k, and ν are fitting parameters.Source: A. Methodology · p. 3
• An RCSJ-based current-voltage model gives zero resistance below Ic and non-zero resistance above Ic, enabling the two polarization states to produce distinct read responses.For Ic,′1′ < IDS < Ic,′0′, the P−R state has zero voltage while the P+R state has non-zero voltage.Source: A. Methodology · pp. 3–4

B. Validation

• Experimental parameters were extracted first, after which the Preisach block reproduced the measured polarization-voltage behavior.The validation used reported data from a 5 µm-wide, 600 nm-long Fe–JoFET measured at 50 mK.Source: B. Validation · p. 4
• The modified Ambegaokar–Baratoff model mimicked measured gate-voltage effects on Ic, while a lookup-table approach modeled gate-voltage effects on RN.Both comparisons were reported as reproducing experimental behavior.Source: B. Validation · p. 4
• The RCSJ model reproduced the Fe–JoFET current-voltage characteristics at zero gate voltage, and the authors judged the overall model suitable for circuit-level use.The reported validation compares simulated behavior with experimental measurements from Ref.20.Source: B. Validation · p. 4

C. Design Space Exploration

• The model predicts how critical current and normal resistance vary with gate voltage across polarization states.Critical current and normal resistance vary strongly with gate voltage, but in opposite directions.Source: C. Design Space Exploration · p. 4
• Both polarization states share superconducting and resistive regions but have distinct critical currents.The distinct critical currents differentiate the states and support selecting a specific operating point.Source: C. Design Space Exploration · p. 4
• The response curves guide selection of gate voltages and read/write biases for circuit- and system-level applications.The paper uses these insights to choose biases for its memory array.Source: C. Design Space Exploration · p. 4

A. Design Principle

• Two distinct ferroelectric polarization states define binary logic: P− and R states correspond to logic 0 and logic 1, respectively, and stored logic 0 has higher Ic and lower RN.Source: A. Design Principle · p. 4
• Positive and negative gate voltages write the two logic states, while an intermediate gate-voltage region is used for reading.The read voltage lies between the switching voltages.Source: A. Design Principle · p. 4
• A read current between the state-dependent critical currents yields zero voltage for one state and nonzero voltage for the other.The current distinguishes the superconducting and resistive channel states.Source: A. Design Principle · p. 4
• The m × n series-connected array selects cells through word-, bit-, and source-line biases, without an additional selector or sensing circuitry.The stored state is read from the bit-line voltage.Source: A. Design Principle · p. 4

B. Working Principle

• Writing uses a V/2 biasing scheme: the addressed cell receives ±Vwrite, while half-selected cells receive ±Vwrite/2 and unselected cells receive 0 V.Vwrite exceeds the absolute switching voltage, whereas Vwrite/2 is below it.Source: B. Working Principle · p. 4
• During read, the addressed word line receives Vread and its bit line receives Iread; other word and source lines are grounded and other bit lines carry no current.The read biases are chosen so only the addressed cell gets the required read conditions.Source: B. Working Principle · pp. 4–5
• Other cells remain superconducting, so the addressed cell’s bit-line voltage distinguishes logic 0 from logic 1 without peripheral sensing circuits.Zero voltage indicates logic 0; nonzero voltage indicates logic 1.Source: B. Working Principle · p. 5

V. MEMORY OPERATION

• Write simulations apply full ±Vwrite to the addressed cell, half voltage to half-accessed cells, and 0 V to unaccessed cells while all bit lines carry zero current.These conditions keep the cells superconducting during writing and allow only the addressed cell to switch.Source: §V · p. 6
• Only the addressed cell changes polarization and critical current during writing; every other cell retains its previous state after the biases are removed.The demonstrated write operations use Vwrite = 3 V and can target a specific cell without a selector.Source: §V · p. 6
• During read, only the addressed cell receives gate voltage and bit-line current, producing a zero or nonzero bit-line voltage according to its memory state.All other cells receive 0 V and remain superconducting.Source: §V · p. 6

• Existing cryogenic-memory approaches face trade-offs including volatility, high power, selectors, magnetic biasing, inductive elements, and sensing circuits that increase complexity and limit scalability.The SC memristor and FeSQUID examples retain access-device requirements; the SC memristor also requires magnetic-flux bias and cryogenic sensing.Source: §VI · pp. 6–7
• The proposed array has lower cell-level operating power than any existing technology and smaller cell area than any existing superconducting or hybrid technology.Source: §VI · p. 7
• Remnant ferroelectric polarization controls the superconducting channel, providing storage and intrinsic cell selection; readout from bit-line voltage avoids dedicated cryogenic sensing.Source: §VI · p. 7

• An experiment-calibrated physics-based Verilog-A compact model was developed and used to verify the proposed memory array’s functionality.Source: §VII · p. 7
• Remnant polarization provides nonvolatile storage, while Fe–JoFETs provide intrinsic selection and superconducting unselected cells avoid additional selectors, inductors, magnetic biasing, and dedicated sensing circuits.Source: §VII · p. 7
• The architecture is presented as potentially useful for quantum computing, superconducting computing, energy-constrained systems, and cryogenic neuromorphic systems.Source: §VII · p. 7
• Retention and disturb analysis, plus experimental validation of the complete memory architecture, remain imperative future work.Source: §VII · p. 7