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Simulation-Efficient Analog Circuit Yield Optimization via Monte Carlo Zeroth-Order Gradient Estimation

Liyan Tan, Yequan Zhao, Ben F. Jamroz, Ari Feldman, Zheng Zhang

arXiv:2609.30678v1cs.CE

TL;DR

Yield optimization is costly because Monte Carlo estimates are piecewise constant in design parameters and can require many SPICE simulations. ZO-MC-SGD turns specification margins into stochastic descent directions using paired perturbations and shared process samples. Across five analog-circuit benchmarks, it reaches the empirical yield ceiling on one circuit and reduces simulation budgets by up to eightfold relative to the best baseline.

  • Problem

    Finite-sample Monte Carlo yield is piecewise constant in design parameters, providing little local information, while evaluating candidates requires costly SPICE samples.

    Source: D. Zeroth-Order Optimization · p. 3, §III · p. 3

  • Method

    ZO-MC-SGD uses a smooth specification-margin loss and paired zeroth-order perturbations under shared process samples to estimate stochastic descent directions.

    Source: §I · pp. 1–2

  • Results

    Across five benchmarks, ZO-MC-SGD reaches mean yield 0.95 on four circuits within 50–200 simulations and the empirical yield ceiling on the fifth, reducing required budget by up to eightfold versus the best baseline.

    Source: §I · p. 2

  • Takeaways & Limitations

    The results support stochastic zeroth-order updates when simulation budgets are tight and the process distribution is available for sampling.

    Source: §VIII · p. 9

Abstract

from arXiv · show

Yield optimization under process variation is expensive because each candidate design must be evaluated across many Monte Carlo SPICE samples. The resulting finite-sample yield is also piecewise constant in the design parameters, providing little local information for optimization. We introduce zeroth-order Monte Carlo stochastic gradient descent (ZO-MC-SGD), a black-box method that converts continuous specification margins into stochastic descent directions. Each update evaluates opposite design perturbations under shared process samples, allowing a small simulation batch to estimate a local direction without differentiating SPICE or fitting a global surrogate model. A Spearman rank-correlation test checks that the margin-based loss orders designs consistently with empirical yield. We prove that the estimator is unbiased for a Gaussian-smoothed surrogate and derive variance and sample-complexity bounds with no explicit dependence on process dimension. Across five analog circuit benchmarks with up to 30 design variables and 42 process variables, ZO-MC-SGD reaches a mean yield of 0.95 on four circuits within 50--200 simulations and the empirical yield ceiling on the fifth. Relative to the best of five black-box and learning-based baselines, it reduces the required simulation budget by up to a factor of eight.

I. INTRODUCTION

Process variation makes nominally compliant circuits vulnerable to specification failures, so yield—not nominal performance—is the relevant design objective. ZO-MC-SGD uses margin-based stochastic updates to search for high-yield designs with limited simulator evaluations.

I. INTRODUCTION

  • Yield is the probability that a fabricated instance satisfies all specifications under process variation, making it more relevant to manufacturability than nominal performance.Process variations perturb device characteristics and can cause violations of gain, bandwidth, or power requirements.Source: §I · p. 1
  • Existing black-box, population-based, and learning-based optimizers face costly model-building, initialization, or policy-training requirements under small simulation budgets.Adjoint methods can provide efficient gradients but often require simulator derivatives unavailable in proprietary flows.Source: §I · p. 1
  • ZO-MC-SGD estimates a descent direction from finite differences of paired black-box simulations, using a smooth specification-margin loss rather than piecewise-constant empirical yield.A rank-correlation check assesses whether lower loss aligns with higher yield.Source: §I · pp. 1–2
  • Across five benchmarks, ZO-MC-SGD reaches mean yield 0.95 on four circuits within 50–200 simulations and the empirical yield ceiling on the fifth, reducing budget by up to eightfold versus the best baseline.The estimator is unbiased for a smoothed surrogate, with bounds having no explicit process-dimension dependence.Source: §I · p. 2

II. BACKGROUND AND RELATED WORK

  • Monte Carlo estimates yield from independent process samples, but by itself does not specify how to choose the next design update.The paper distinguishes evaluating circuit performance under variation from deciding how simulator results guide the search.Source: A. Monte Carlo Yield Estimation · p. 2, §II · p. 2

A. Monte Carlo Yield Estimation

  • Finite-sample Monte Carlo yield is piecewise constant over design regions, while accurate estimation can require many simulations, especially for rare failures.Variance-reduction methods improve estimates at a fixed design but do not determine how evaluations should update the design.Source: A. Monte Carlo Yield Estimation · p. 2

B. Model-Based Yield Optimization

Prior model-based and learning-based approaches use simulator data to guide design search, while zeroth-order methods offer local updates from function evaluations. ZO-MC-SGD combines these updates with a smooth, yield-aligned loss built from specification margins.

B. Model-Based Yield Optimization

  • Bayesian and related model-based methods construct representations of performance or yield to guide search, with simulation costs tied to the data and computation needed to build and optimize those models.Approaches include probabilistic objective models, direct yield models, pass/fail classifiers, joint PVT models, robust optimization, and polynomial-chaos approximations.Source: B. Model-Based Yield Optimization · p. 2

C. Variation-Aware Learning-Based Design

  • Variation-aware learning methods train sizing policies through repeated simulator interactions, but typically target robustness or specification satisfaction rather than Monte Carlo yield directly.Training is generally repeated for each circuit or topology.Source: C. Variation-Aware Learning-Based Design · p. 3

D. Zeroth-Order Optimization

  • Zeroth-order methods estimate local descent directions from function evaluations, retaining gradient-based updates without objective derivatives; prior circuit use was nominal and deterministic.ZOAF applies two-point estimates to analog/RF sizing at a fixed process condition.Source: D. Zeroth-Order Optimization · p. 3
  • Empirical yield is a poor zeroth-order signal because binary outcomes discard performance margins and remain piecewise constant across large design regions.The proposed method addresses this by combining a smooth margin-derived loss with Monte Carlo zeroth-order estimation under process variation.Source: §III · p. 3, D. Zeroth-Order Optimization · p. 3

III. METHOD

  • ZO-MC-SGD converts continuous specification margins into a smooth loss and averages paired perturbation differences over process samples to obtain stochastic descent directions.Yield remains the returned design's evaluation metric, while the expected loss supplies the optimization signal.Source: §III · p. 3

A. From Specification Margins to a Yield-Aligned Loss

  • The loss uses signed, scaled shortfalls and softplus penalties, with weights balancing specifications and a mild preference for gain headroom.Softplus sharpness controls how far a specification influences loss around its boundary; larger values approach a hinge, while smaller values reward margin farther into feasibility.Source: A. From Specification Margins to a… · pp. 3–4
  • Spearman rank correlation checks whether lower mean loss orders designs with higher empirical yield; alignment is accepted at ρs ≤ −0.7.Circuit-specific sharpness settings are selected by the most negative correlation on a fixed calibration set.Source: A. From Specification Margins to a… · p. 4

B. Monte Carlo Zeroth-Order Descent

The descent step uses paired, opposite design perturbations evaluated on shared process samples to estimate a stochastic gradient of the loss. The algorithm combines these estimates with a warm start and constrained, coordinate-scaled updates.

B. Monte Carlo Zeroth-Order Descent

  • Each gradient estimate averages K paired differences from opposite design perturbations under shared process samples, costing 2K SPICE simulations.The perturbation radius ϵ sets the finite-difference scale, while K controls Monte Carlo averaging.Source: B. Monte Carlo Zeroth-Order Descent · p. 4
  • ZO-MC-SGD begins from the best of a random-search warm start, then uses Adam-rescaled stochastic-gradient updates projected onto the design box.Physical design bounds are mapped to [0, 1]^n to give perturbation and step sizes a common coordinate scale.Source: B. Monte Carlo Zeroth-Order Descent · p. 4
  • The warm start counts toward budget B, and the algorithm takes another descent step only when 2K simulations remain in the budget.The warm-start simulations are the number of designs times the Monte Carlo samples used to score each design.Source: B. Monte Carlo Zeroth-Order Descent · p. 4

IV. THEORETICAL ANALYSIS

The analysis characterizes the zeroth-order estimator’s accuracy and the simulation cost of approaching stationarity for its smoothed surrogate. Under the stated regularity conditions, paired process samples yield dimension-independent variance and a sample-complexity bound.

A. Estimator Guarantees and Sample Complexity

  • The estimator is unbiased for the Gaussian-smoothed objective’s gradient, with an O(ε²) discrepancy from the original objective.The analysis assumes smooth per-sample losses; the softplus construction is C∞, and the Gaussian perturbations motivate an unconstrained domain.Source: A. Estimator Guarantees and Sample… · pp. 4–5, §IV · p. 4
  • With common random numbers within each pair, variance falls as 1/K and has no explicit process-dimension factor dξ.Process variation enters through σ²g(x), while sharing each process realization prevents noise amplification as ε becomes small.Source: A. Estimator Guarantees and Sample… · p. 5
  • Under the theorem’s assumptions and parameter conditions, ZO-MC-SGD reaches ν-stationarity with O(n/ν²) simulator evaluations, independent of dξ.This guarantee concerns the surrogate objective F; its link to yield is established separately by rank alignment.Source: A. Estimator Guarantees and Sample… · p. 5

B. Numerical Validation of the Estimator

Two synthetic problems test the estimator against reference gradients, including a softplus-based objective closer to the circuit surrogate. The reported S2 error reaches 0.57% at M = 1.28×10⁵, with no visible bias floor when ε varies fourfold.

B. Numerical Validation of the Estimator

V. EXPERIMENTAL SETUP

The experimental setup evaluates ZO-MC-SGD on five SPICE-simulated analog circuits and compares methods under common simulation budgets. Benchmarks are screened for meaningful yield-optimization conditions and span two circuit topology families with increasing stage counts.

V. EXPERIMENTAL SETUP

  • The evaluation compares five black-box and learning-based baselines under the same SPICE optimization budgets across circuits with design dimensions 6–30 and process dimensions 10–42.Implementation details are collected in Appendix B.Source: §V · pp. 5–6

A. Circuit Benchmarks

  • Each benchmark is screened for nominal feasibility, process-sensitive specifications, initial yield between 0.30 and 0.85, and rank alignment ρs ≤ −0.7.Each rank-alignment test uses Ncal = 81 perturbed calibration designs.Source: A. Circuit Benchmarks · p. 6
  • The five benchmarks comprise common-source cascades with one, three, and five stages, and Miller-compensated amplifiers with two and three stages.Adding stages increases both design dimension n and process dimension dξ; Table II summarizes the benchmarks.Source: A. Circuit Benchmarks · p. 6, Table II · p. 6
  • The circuits are simulated in ngspice with LEVEL-1 device models and independent zero-mean Gaussian mismatch; a sample passes only if gain, bandwidth, and static power all meet their circuit-specific limits.Table I presents per-circuit yield specifications at VDD = 1 V.Source: A. Circuit Benchmarks · p. 6, Table I · p. 6
  • All methods share a separate starting design, while the nominal reference design is reserved for screening and calibration.The shared starting design’s initial yield yinit is reported in Table II.Source: A. Circuit Benchmarks · p. 6, Table II · p. 6

B. Baselines and Objectives

The results test whether stochastic descent directions reduce circuit-level simulation cost, using objective-specific baselines and a common SPICE-budget evaluation. ZO-MC-SGD reaches mean yield 0.95 on all five benchmarks within 50–200 simulations, with high-precision re-estimates indicating an empirical ceiling on one circuit.

B. Baselines and Objectives

  • Five baselines—BO,, [6], CMA-ES, [11], PSO, TuRBO, and RobustAnalog —use suited objectives, with comparisons matched by SPICE budget, not iterations.ZO-MC-SGD uses a smooth loss; the four direct-yield baselines obtain better final designs with direct yield than with that smooth loss, while RobustAnalog uses a specification-margin reward. Table III summarizes SPICE cost per query or update.Source: B. Baselines and Objectives · p. 6, Table III · p. 6

C. Evaluation Protocol

  • The primary efficiency measure is the minimum SPICE budget reaching mean yield 0.95; five-seed runs use a separate 80-sample held-out evaluation set, with rank-alignment calibration outside the budget.Source: C. Evaluation Protocol · p. 6

A. Sample Efficiency

  • 50–200 simulations suffice for ZO-MC-SGD to reach mean yield 0.95 across all five benchmarks; on 3- and 5-stage CS, 200 and 100 beat strongest baselines’ 800.It ties the best baseline on 1-stage csamp and 2-stage csmiller; the strongest baselines require four and eight times the budget on the 3- and 5-stage CS circuits, respectively.Source: Table IV · p. 7, A. Sample Efficiency · p. 7
  • With 1,000 fresh samples, four circuits’ five-seed mean yields are 0.976, 1.000, 0.976, and 1.000; 1-stage csamp estimates 0.934 (95% interval [0.917, 0.949]).No method exceeds 0.95 on 1-stage csamp under the common protocol at any tested budget, suggesting an empirical yield ceiling within the tested design space.Source: Table V · p. 7, A. Sample Efficiency · p. 7

B. Ablations and Robustness

The ablations test objective alignment, softplus calibration, and correlated process variation, while the discussion and conclusion identify the method’s operating regime and scope. The reported results favor direct-yield baselines, show no measurable benefit from circuit-specific sharpness settings, and retain sample-efficiency under the tested correlated process model.

B. Ablations and Robustness

  • Across circuits, direct Monte Carlo yield outperforms the softplus surrogate for all four tested optimizers, with average gains ranging from 0.24 to 0.41.RobustAnalog is excluded from this comparison because it optimizes its own specification-margin reward.Source: B. Ablations and Robustness · pp. 7–8
  • All 25 circuit–sharpness combinations satisfy ρs ≤−0.7, and a shared default leaves target-reaching budgets unchanged with average yield difference below 0.001.Circuit-specific calibration provides no measurable sample-efficiency advantage on these benchmarks.Source: B. Ablations and Robustness · p. 8
  • Under correlated process variation, ZO-MC-SGD reaches the 0.95 target on 3-stage csamp in 200 simulations and 2-stage csmiller in 25, versus 400 and 100 for CMA-ES.On 3-stage csamp, BO takes more than 400 simulations; on 2-stage csmiller, it takes 200. The estimator requires independent samples from the joint process distribution, not independent process components.Source: B. Ablations and Robustness · p. 8

VII. DISCUSSION

  • ZO-MC-SGD is positioned for expensive-SPICE yield optimization when the simulation budget is small relative to design dimension, using small batches for local updates without fitting a global model.Its growing advantage on larger benchmarks is consistent with that distinction mattering more as design dimension increases.Source: §VII · p. 8
  • The experiments cover process dimension dξ up to 42; behavior in production-scale circuits with hundreds of mismatch variables remains unestablished.Variance reduction or structure-exploiting zeroth-order estimators may be needed for that regime.Source: §VII · p. 9

VIII. CONCLUSION

  • Across five analog circuit benchmarks, ZO-MC-SGD reaches mean yield 0.95 on four circuits within 50–200 simulations and the empirical yield ceiling on the fifth, reducing budget by up to eightfold versus the best baseline.The stated conclusion is scoped to tight simulation budgets when the process distribution is available for sampling.Source: §VIII · p. 9

APPENDIX A PROOFS OF SECTION IV

The proof uses Gaussian smoothing to relate a two-point finite-difference estimator to the gradient of a smoothed objective. Shared process samples cancel loss noise, and the resulting estimator is unbiased with a variance bound.

APPENDIX A PROOFS OF SECTION IV

  • Gaussian smoothing defines hϵ as the expectation of h(x + ϵv) for Gaussian v, and symmetry under v → −v gives the stated identity.The identity is attributed to Nesterov and Spokoiny.Source: Appendix A · p. 9

Proof of Proposition 1

  • Conditioning on x and a fixed pair (ξ, v), the two-point argument applied to ℓ(·, ξ) establishes the estimator’s conditional mean.Taking expectation over ξ and exchanging expectation with the gradient yields E[ĝMC | x] = ∇Fϵ(x).Source: Proof of Proposition 1 · p. 9
  • The smoothing bias is bounded using the gradient Taylor remainder for F, whose Hessian inherits the stated Lipschitz property.The Gaussian expectation used in the bound is E∥v∥2 = n.Source: Proof of Proposition 1 · p. 9
  • With shared ξ, the finite-difference loss difference scales with the perturbed gradient rather than O(1/ϵ); independent draws instead add an O(σℓ^2/ϵ^2) loss-noise term to the variance.The proof combines this noise contribution with the two-point estimator’s mean-term bound and divides by K.Source: Proof of Proposition 1 · p. 9

Proof of Theorem 1

The proof bounds expected progress using the unbiased mini-batch estimator, its second moment, and the smoothing bias. Under the stated conditions, it gives a simulation-complexity bound independent of process dimension.

Proof of Theorem 1

  • For the unconstrained case, the proof uses L-smoothness and the estimator’s mean and second-moment bounds to control expected progress.The projected case replaces the gradient with a gradient mapping and changes only absolute constants.Source: Proof of Theorem 1 · p. 9
  • Under the stated ϵ conditions, Vn = O(n) and the smoothing-bias term is bounded by ν/2.These bounds control the estimator variance and bias contributions in the progress argument.Source: Proof of Theorem 1 · p. 10
  • Choosing η = Θ(√(K/(nT))) yields B = 2KT = O(n/ν2) simulations once KT = O(n/ν2), independent of K and process dimension dξ.The displayed fragments state that the choice drives the first two terms below ν/2.Source: Proof of Theorem 1 · p. 10

APPENDIX B EXPERIMENT CONFIGURATION

The appendix specifies the process and loss setup, benchmark calibration, and implementation details, then reports additional optimizer-runtime and fixed-budget yield analyses. The reported runtime comparison shows substantial surrogate-model and acquisition overhead for BO and TuRBO as design dimension increases.

APPENDIX B EXPERIMENT CONFIGURATION

  • Process variation includes per-device shifts in Vth, β, L, and W plus two global shifts, so dξ grows with stage count.LEVEL-1 Shichman–Hodges models are used for controlled, reproducible dimension sweeps.Source: Appendix B · p. 10
  • The benchmark σ-scale multiplies per-device baseline mismatch sigmas and is fixed after sweeping until nominal-design yield falls within [0.30, 0.85].The chosen scale is then held fixed for calibration, optimization, and evaluation.Source: Appendix B · p. 10
  • All five benchmarks use weights (wgain, wugbw, wpower) = (1, 2, 1) and γ = 0.1; four use calibration (5, 10, 10), while 2-stage csmiller uses (1, 3, 2).The appendix points to Table VII for default ZO-MC-SGD settings.Source: Appendix B · p. 10, Table VII · p. 10
  • RobustAnalog is implemented as deep deterministic policy gradient with multi-task gradient surgery and k-means corner pruning, optimizing a specification-margin reward.Design-side quantities act in normalized X = [0, 1]n coordinates.Source: Appendix B · p. 10

APPENDIX C ADDITIONAL RESULTS

  • At n = 30, BO and TuRBO optimizer times are 464 s and 251 s, respectively, versus approximately 350 s spent in SPICE; ZO-MC-SGD, CMA-ES, PSO, and RobustAnalog add little computation relative to SPICE.Table IX additionally reports best mean yield within B = 400 simulations and the observed range over five seeds.Source: Appendix C · p. 10, Table VIII · p. 10
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