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Evaluation of portability and performance of an OpenMP5 offloaded Quantum-Inspired Evolutionary Optimization Across the GPU Ecosystem

Kasturi Venkata Srikanth, Ashish Singh, Ferdin Sagai Don Bosco, Aman Mittal, Abhishek Singh, Aditya Singh, Abhishek Chopra

arXiv:2609.30862v1cs.PFmath.OC

TL;DR

The paper asks whether a single OpenMP 5 QIEO implementation can perform adequately across laboratory, cloud, and leadership-class GPU settings. It tests the same source on three GPUs and finds strong gene-parallel speedups against each environment’s CPU baseline, with elite selection better suited to the host.

  • Problem

    The paper asks whether one OpenMP 5 target-offloaded QIEO source can deliver a decisive advantage over the same-source CPU in three distinct deployment environments.

    Source: §I · p. 1

  • Method

    The study runs 0/1 knapsack campaigns using one OpenMP 5 QIEO source, comparing chromosome- and gene-parallel offload on three GPUs.

    Source: §I · p. 2

  • Results

    Gene-parallel offload achieved geometric-mean speedups of 90× over one CPU core and 12× over 72 host threads on V100, 136× and 17× on A100, and 155× and 16.6× on MI300X.

    Source: §VIII · p. 13

  • Takeaways & Limitations

    The portable strategy keeps Q resident on the device and places DetermineElite on the host after Evaluation and before CIP.

    Source: §I · p. 2, §VIII · p. 13

Abstract

from arXiv · show

Quantum-inspired evolutionary optimization (QIEO) is a new class of population-based metaheuristic optimization algorithms which represents design variables as a set of qubits and searches a continuous, multi-dimensional landscape through rotation of the qubit's amplitude pair. Every generation rotates those amplitudes toward a single elite, which corresponds to that generation's best. The per-generation cost scales as $O(N_p N_g)$ for $N_p$ chromosomes and $N_g$ genes (decision variables). Production use of such solvers is rarely confined to a single machine class. Prototypes are run on laboratory servers- before moving to rented cloud workstations for more involved campaigns. The largest problems are reserved for leadership-class accelerators. This paper asks whether a \emph{single} OpenMP~5 source of QIEO, offloaded with \texttt{\#pragma omp target}, is a viable production path in each of those settings. We report three independent, campaigns of the 0/1 knapsack problem against a same-source multi-core Intel CPU baseline. The study comprises approximately 3,000 runs spanning varying chromosome and gene counts, evaluated using both chromosome-level and gene-level offload strategies on the NVIDIA Tesla V100 SXM2, NVIDIA A100 80GB, and AMD Instinct MI300X GPUs. Deployment-specific nuances such as Volta's constant-memory cliffs, Ampere's L2 persistence and \texttt{cp.async}, CDNA~3's Infinity Cache and XCD occupancy are addressed to ensure high performance of these platforms. Results reveal gene-parallel offload achieved geometric-mean speedups of 90$\times$, 136$\times$, and 155$\times$ over a single CPU core on the V100, A100, and MI300X, respectively, and 12$\times$, 17$\times$, and 16.6$\times$ over 72 host threads. Furthermore DetermineElite, the $O(N_p)$ selection of the generation-best chromosome, is found to be better suited to the host than to the device.

I. INTRODUCTION

The paper tests whether one OpenMP 5 QIEO source can perform adequately across in-house, cloud, and leadership-class GPU settings, without ranking the GPUs. It compares two offload strategies and frames 0/1 knapsack as a probe of the algorithm’s workload and kernels.

A. Formulation

  • QIEO represents each gene as a qubit amplitude pair that collapses to a binary allele on observation, then rotates amplitudes toward an elite solution.The study uses 0/1 knapsack, a standard NP-complete metaheuristic test, to probe the Np × Ng grid streamed each generation –.Source: §I · p. 1, A. Formulation · p. 2

I. INTRODUCTION

  • The central question is whether OpenMP 5 target offload can deliver a decisive advantage over the same-source multi-core CPU in each deployment setting.The paper treats this as a question of deployment adequacy rather than inter-GPU ranking.Source: §I · p. 1
  • The study evaluates one portable OpenMP 5 QIEO formulation across three GPU environments in 2,940 measured knapsack runs, with chromosome- and gene-parallel offload.The environments are the V100, A100 80GB, and MI300X; the deployment thesis is adequacy in each setting, not inter-GPU ranking.Source: §I · pp. 1–2

II. RELATED WORK

  • Earlier QIEO work introduced qubit chromosomes and rotation gates, developed the inherited QIP, FE, and CIP kernel split, and largely used CUDA [3],, [14].This study holds the algorithm and programming model fixed while changing the deployment ecosystem.Source: §II · p. 2

B. Methodology

  • The measured generation loop comprises QIP resampling and observation, Evaluation’s per-chromosome gene reduction, DetermineElite’s population-wide best selection, and CIP rotation toward that elite.DetermineElite selects the generation-best chromosome after Evaluation and before CIP; it also supplies the convergence test and does two to four orders of magnitude less work than dense kernels.Source: B. Methodology · p. 2

C. OMP5 Offload Strategies

The study compares chromosome-parallel mapping, which parallelizes chromosomes, with gene-parallel mapping, which exposes parallel work within each chromosome. Gene-level work better fills GPUs, while the portable implementation keeps data resident and leaves elite selection on the host.

C. OMP5 Offload Strategies

  • The generation figure distinguishes dense QIP and CIP updates, Evaluation’s gene-axis reduction, and DetermineElite’s chromosome-axis reduction before CIP.DetermineElite selects the elite that CIP uses for rotation.Source: Figure 1 · p. 3
  • Gene-parallel offload exposes up to NpNg independent QIP and CIP updates, whereas chromosome-parallel offload assigns only one worker per chromosome and serializes its gene loop.Evaluation under gene-parallel mapping requires a segmented reduction along the gene axis.Source: C. OMP5 Offload Strategies · pp. 2–3
  • Chromosome-only mapping can leave GPU compute units idle because Np waves may not fill 80–304 units; gene-parallel mapping exposes work within each solution.The source uses a command-line switch to select either loop mapping, while the algorithm and source remain unchanged.Source: C. OMP5 Offload Strategies · pp. 2–3
  • Weights, values, and Q remain mapped across generations; the portable strategy keeps Q on-device and runs DetermineElite on the host between Evaluation and CIP.Vendor-specific constant-memory, L2-window, and cp.async helpers are optional tuning steps.Source: C. OMP5 Offload Strategies · p. 3

D. Deployment Environments

The deployment environments impose different capacity, locality, and occupancy constraints, while the workload spans population and gene-count combinations grouped into overlapping size classes. The corpus retains measured device and CPU runs, with a full host-thread sweep only for Small cases.

D. Deployment Environments

  • V100 Large cases can exceed 16 GB capacity, A100 fits the grid but faces a locality choice, and MI300X accommodates larger instances yet still needs gene-axis parallelism to feed its compute units.The A100 options include constant memory, shared-memory tiles, an L2 persistence window, and GDDR5; MI300X also uses Infinity Cache.Source: D. Deployment Environments · p. 3

A. Workload

  • Workloads are points (Np, Ng): Small emphasizes modest populations, Medium extends toward larger Np at mid-grid work, and Large occupies the high-Np, high-Ng corner.Per-generation time is the hardware-comparison metric because it is independent of stochastic stopping time; convergence uses a 20-generation stability window or a generation cap.Source: A. Workload · p. 3

B. Corpus

  • The three retained campaigns contain 928 V100, 990 A100, and 1,022 MI300X runs; each uses the Intel OpenMP host that produced that archive as its CPU baseline.Empty logs without timing footers are dropped rather than imputed.Source: B. Corpus · p. 3, Table I · p. 4
  • The full host-thread sweep from 1 to 72 threads exists only for 59 matched Small pairs; Medium and Large CPU points are predominantly one-thread baselines.Filename size classes densify corners of the (Np, Ng) plane and are not a disjoint partition.Source: B. Corpus · p. 4, Table II · p. 4, Figure 3 · p. 4

C. Metrics

The metrics compare host and device times, diagnose kernel bottlenecks, and organize results by deployment concern rather than by inter-GPU speed ranking.

C. Metrics

  • T(p) denotes per-generation host time on p threads, while TG and TC denote gene- and chromosome-parallel device times.Source: C. Metrics · p. 4
  • Within-campaign rankings use (Np, Ng)-matched triples, and no speedup compares one GPU’s Tgen directly with another’s.Source: C. Metrics · p. 4
  • Kernel fractions Tk/Tgen diagnose bottleneck shifts, and geometric means summarize speedups across a three-order-of-magnitude dynamic range.Source: C. Metrics · p. 4

V. RESULTS

  • Results proceed from the host baseline to device adequacy, occupancy, memory management, and kernel-resolved analysis.Source: §V · p. 4

A. Intel Xeon Platinum 8581C with OpenMP as a Shared Baseline

Gene-parallel offload beats 72 host threads by 12–17× across the GPUs, while chromosome-parallel loses every matched pair. The CPU baseline peaks near 8× at 16 threads, making host thread count material to the comparison.

A. Intel Xeon Platinum 8581C with OpenMP as a Shared Baseline

  • The cloud-exposed Xeon Platinum 8581C at 2.30 GHz supplies the shared CPU baseline, and the common Small-class thread sweep is its stated honest characterization.Source: A. Intel Xeon Platinum 8581C with… · p. 4
  • For the densest Np=32, Ng≤15000 family, curves follow s≈0.25 (S∞=4); across 59 Small pairs, speedup peaks near 8× at 16 threads and falls to 2.62× median at 72 threads.At 72 threads, parallel efficiency is 3.6%.Source: A. Intel Xeon Platinum 8581C with… · pp. 4–5
  • QIP consumes 77% of serial Tgen, while shared DRAM, false sharing, kernel barriers, and NUMA placement compound the post-16-thread decline.Larger Ng helps slightly but does not restore efficiency because the extra work remains bandwidth-limited.Source: A. Intel Xeon Platinum 8581C with… · p. 5
  • Eight to sixteen host threads are the production CPU mapping; using only one core overstates accelerator gains, while using 72 threads understates host performance.Source: A. Intel Xeon Platinum 8581C with… · p. 5

B. End-to-End Adequacy

  • On V100, gene-parallel SG=89.6 and S72=12.1 across 59 Small pairs; chromosome-parallel loses matched pairs, and (32, 500) is only 0.49× versus one core.The 16 GB capacity wall and low-Np occupancy limit the campaign.Source: B. End-to-End Adequacy · p. 5
  • On A100, SG=136 and S72=17.2; gene-parallel wins every matched pair (median ρ=5.38), although (32, 500) remains 0.81×.The 80 GB memory fills Large cells that are missing on V100.Source: B. End-to-End Adequacy · p. 5
  • On MI300X, SG=155 and S72=16.6; the mapping penalty has median ρ=6.77, and the launch-bound (32, 500) case reaches only 2.1×.Source: B. End-to-End Adequacy · p. 5
  • Gene-parallel offload moves a ~0.6 s host step to milliseconds on every GPU and beats 72 host threads by 12–17×; chromosome-parallel loses every matched pair.Source: B. End-to-End Adequacy · p. 5

C. Occupancy Challenges

Chromosome-parallel mapping underfills the GPUs, while exposing the gene axis improves occupancy; even gene-parallel launches can remain underfilled on small grids. At fixed total work, the population-to-gene aspect ratio still affects device time.

Occupancy rule

  • The practical fill rule is to expose genes and keep generations on the host when NpNg is below roughly one 256-thread block per SM or CU.The reported cutoffs are 8·80·256 for V100, 8·108·256 for A100, and 8·304·256 for MI300X.Source: C. Occupancy Challenges · pp. 5–7

Tesla V100 SXM2

  • On V100, chromosome-parallel with Np = 32 feeds one warp to 80 SMs, while gene-parallel at Ng = 500 still supplies only 500 warps against a roughly 5120-warp ceiling.The mapping comparison in Fig. 7 shows chromosome-parallel rarely exceeding 10×, while gene-parallel approaches 600× once the mesh is fed.Source: C. Occupancy Challenges · pp. 5–6

NVIDIA A100 80GB

  • A100 raises the fill requirement: Np = 32 is still one warp for 108 SMs, and Ng = 500 gene-parallel remains below 6912 concurrent warps.The wider mesh increases the occupancy floor rather than removing the underfill problem.Source: C. Occupancy Challenges · p. 6

AMD Instinct MI300X

  • On MI300X, gene-parallel QIP crosses the occupancy threshold near NpNg ≳ 10^5, but small grids remain launch-bound and chromosome-parallel underfills the eight-XCD mesh.At (32, 500), gene-parallel supplies only about 250 wavefronts, versus an order of 10^5 threads needed to feed 304 CUs.Source: C. Occupancy Challenges · p. 7
  • On MI300X, gene-parallel speedup ratio ρ falls toward 2–3 as Np grows but never crosses, so chromosome-parallel has no late crossover advantage.The darkest ρ cells occur at mid Np and large Ng, where teams still walk a long serial gene loop.Source: C. Occupancy Challenges · p. 7
  • At constant W = NpNg, device time branches by aspect ratio: Evaluation reductions and wavefront occupancy depend on the Np:Ng shape, not work volume alone.The V100 isoefficiency curves likewise show that skinny populations of long chromosomes and fat populations of short ones are not interchangeable.Source: C. Occupancy Challenges · pp. 6–7

D. Memory Management

Across the GPUs, keep the qubit grid resident and place knapsack values and weights in the fastest suitable memory; when those tables must stream from device memory, Evaluation can dominate generation time. The relevant capacity and reuse mechanisms differ by architecture.

Tesla V100 SXM2

  • On V100, past shared- and constant-memory capacity marks, Evaluation streams (v, w) from GDDR5 and its generation-time share rises from 0.077 to 0.816.Gene-fastest Q layout enables coalesced 128-byte warp transactions; chromosome-major access strides by Ng, while gene-parallel approaches the 900 GB/s GDDR5 roof and chromosome-parallel remains one to two decades below.Source: D. Memory Management · p. 7

NVIDIA A100 80GB

  • On A100, 1.6 MB item tables at Ng = 200000 fit in the 40 MB L2, while the 80 GB device memory holds the qubit grid.When Evaluation streams (v, w), its share rises from 0.130 to 0.715 even while the tables fit in L2; larger tiles, an L2 window, and cp.async target this reduction.Source: D. Memory Management · p. 7

AMD Instinct MI300X

  • On MI300X, 1.6 MB of item tables fit in Infinity Cache, but at (262144, 200000) the qubit grid reaches tens of gigabytes and some runs lack footers despite 192 GB HBM3.Gene-fastest layout supports coalescing, while team-private elite caches reduce CIP broadcast traffic.Source: D. Memory Management · pp. 7–8
  • On MI300X, fusing QIP+observe and Evaluation, hosting DetermineElite, and keeping CIP separate reduces implicit device barriers from four to two.The paper notes that launch tax matters on a multi-die GPU even when capacity does not.Source: D. Memory Management · p. 8

Memory strategy

  • Keep Q resident and store (v, w) as high in the memory hierarchy as they fit; beyond capacity cliffs, Evaluation streams from device memory and owns generation time.The Q grid should use gene-fastest layout and transfer from the host only once for the whole run.Source: D. Memory Management · p. 8

E. Kernel-Resolved Picture

Across the kernel-resolved results, QIP and CIP are strong device candidates, Evaluation is the portable performance ceiling, and DetermineElite is better left on the host. Which kernel dominates generation time depends on the offload mapping.

Kernel roles

  • QIP and CIP are element-wise maps, Evaluation is a segmented reduction, and DetermineElite is a scalar minimum.DetermineElite selects the generation-best chromosome after Evaluation, and the same scalar feeds the convergence test.Source: E. Kernel-Resolved Picture · p. 8

Tesla V100 SXM2

  • On V100, gene-parallel QIP reaches 537× and CIP 165×, while Evaluation is near 12× and DetermineElite is 0.060×.DetermineElite is a 17× slowdown because device launch and scalar DtoH transfer outweigh the host arithmetic.Source: E. Kernel-Resolved Picture · pp. 8–9
  • On V100, gene-parallel shifts the generation profile from CPU QIP at 77% to Evaluation at 29% overall and 82% at Ng = 200000.Chromosome-parallel retains a CPU-like profile with QIP at 57%, showing that mapping changes which kernel dominates.Source: E. Kernel-Resolved Picture · p. 9

NVIDIA A100 80GB

  • On A100, gene-parallel QIP reaches 678× and CIP 219×, Evaluation caps near 16×, and DetermineElite remains a 0.063× tax.Evaluation takes 71% of time at Ng = 200000, while chromosome-parallel retains a CPU-like profile with QIP at 58%.Source: E. Kernel-Resolved Picture · p. 9

AMD Instinct MI300X

  • On MI300X, gene-parallel QIP reaches 1010× and CIP 377×, versus 10× for Evaluation and 0.105× for DetermineElite.Evaluation owns 64% of gene-parallel time and rises from 49% to 87% with Ng; chromosome-parallel retains a CPU-shaped profile with QIP at 64% and CIP at 26%.Source: E. Kernel-Resolved Picture · p. 9

Cross-GPU findings

  • Across GPUs, Evaluation is the portable ceiling at 10–16× and becomes the majority of gene-parallel time at large Ng, while DetermineElite is a launch-tax liability best left on the host.The paper recommends tuning the segmented reduction rather than adding another QIP pragma.Source: E. Kernel-Resolved Picture · p. 9

VI. DISCUSSIONS

The three GPU deployments address different operational settings, and their architecture determines both constraints and role. Across them, the shared QIEO grid remains an occupancy and memory-placement problem, but the available resources differ substantially.

VI. DISCUSSIONS

  • The deployments are framed as distinct choices: running QIEO on a laboratory GPU, holding larger grids on a rented workstation, or filling a leadership-class allocation without a vendor rewrite.Performance is judged against the host in each chassis, not by ranking GPUs against one another.Source: §VI · p. 9

A. Architecture

  • The V100 is positioned as a laboratory-owned option, but its 80 SMs need gene-axis parallelism and its 16 GB capacity limits qubit-grid residency.Its 64 KiB constant cache and roughly 48 KiB shared memory are the on-chip homes for (v, w) before Evaluation streams from GDDR5.Source: A. Architecture · p. 9, Figure 10 · p. 10, Figure 11 · p. 10
  • The A100 raises occupancy and capacity with 108 SMs and 80 GB, while 164 KiB shared memory and a 40 MB L2 window support tile and data reuse.Its cp.async pipeline can hide the stream; Tensor Cores and MIG are not useful for this workload, and MIG slicing is harmful for one dense generation.Source: A. Architecture · pp. 9–10
  • MI300X has 304 CUs across eight XCDs and 192 GB HBM3, with Infinity Cache holding item tables; only the most extreme qubit grids exhaust capacity.Its MCM mesh still underfills without gene-axis exposure, and cross-XCD reductions make tiny DetermineElite kernels less defensible than on a single NVIDIA die.Source: A. Architecture · p. 10
  • Across all three cards, warps or wavefronts must be fed from the gene axis, (v, w) must use available on-chip memory, and Q must remain resident.What changes by GPU is the memory structure available and how soon the grid no longer fits.Source: A. Architecture · p. 10

B. Performance

Performance is judged against each accelerator's own CPU baseline and its ability to keep larger campaigns interactive, not by ranking GPUs. The campaigns assign distinct roles to the V100, A100, and MI300X.

B. Performance

  • Gene-parallel offload reaches geometric-mean speedups of 90×, 136×, and 155× over one core and 12×, 17×, and 16.6× over 72 host threads on V100, A100, and MI300X, respectively.The MI300X campaign also reports a 0.15–126 ms generation range and 4.17 ms median.Source: B. Performance · pp. 10–11
  • Gene-parallel mapping wins every matched pair in every environment, and chromosome-parallel never reverses the ranking; DetermineElite is a slowdown everywhere, with reported values ranging from 0.06× to 0.11×.Source: B. Performance · p. 11, Table IV · p. 11

C. Roles

  • V100 is the development and regression home for Small and Medium campaigns; its 16 GB capacity limits the campaign grid, not the algorithm.Its chromosome-parallel mapping returns only 5×, within the host's 8–16-thread band.Source: B. Performance · p. 10, C. Roles · p. 11
  • A100 is the campaign home: its 80 GB holds grids that exceed V100 capacity, including (65536, 100000) at 241 ms per generation.Evaluation becomes the critical path at 16×; cp.async tiles and an L2 window target further gains.Source: B. Performance · p. 10, C. Roles · p. 11
  • MI300X is the allocation home for the largest grids; its 304 compute units penalize mappings that do not expose gene-level parallelism.Infinity Cache holds the item tables, while Evaluation takes 64–87% of gene-parallel generation time.Source: C. Roles · p. 11, B. Performance · p. 11
  • The production workflow moves the same binary contract from V100 prototype and nightly testing to A100 Large campaigns and MI300X's extreme-size corner.The A100 is positioned for campaigns after 16 GB is insufficient but before a center allocation is needed.Source: C. Roles · p. 11

D. Cross-Cutting Evidence

Across the three campaigns, gene-level mapping outperforms chromosome-level mapping, while evaluation and launch costs shape the remaining bottlenecks. Convergence generations depend on problem size rather than device or mapping.

D. Cross-Cutting Evidence

  • Gene-parallel mapping wins every matched pair; chromosome-parallel mapping incurs median penalties of 4.8×, 5.4×, and 6.8×, exceeding the full 72-thread CPU gain in each campaign.Chromosome-parallel QIP retains 57–64% of generation time.Source: D. Cross-Cutting Evidence · p. 11
  • QIP and CIP accelerate by 102–103× under gene-parallel mapping, while Evaluation reaches only 10–16× and becomes the majority of generation time at Large.Evaluation is a segmented reduction whose share grows with gene count; the text identifies warp- or wavefront-level reduction as the profitable device-kernel target.Source: D. Cross-Cutting Evidence · p. 12, Table VII · p. 12
  • DetermineElite has geometric-mean speedups of 0.06× on V100 and A100 and 0.11× on MI300X, making it a slowdown suited to host-side execution.The O(Np) minimum does not amortize a target region.Source: D. Cross-Cutting Evidence · p. 12
  • At (32, 500), offload is slower than one CPU core on V100 and A100 and only 2.1× faster on MI300X, as four launches exceed the useful work.The recommendation is to skip offload below a few blocks per SM or CU.Source: D. Cross-Cutting Evidence · pp. 12–13
  • Convergence generations depend on gene count, not device or mapping; mapping changes wall time per step, while solution quality remains a property of QIEO.Source: D. Cross-Cutting Evidence · p. 13

VII. RECOMMENDATIONS

The recommendations separate portable choices from hardware-specific constants, with the conclusion reporting that one OpenMP 5 QIEO implementation performs adequately across all three environments. Keep the workload on the host when it is too small to fill the device, and move larger campaigns to the GPU capacity and tuning appropriate to their scale.

A. Portable layer (every environment)

  • Stay on the CPU below roughly one well-filled wave per compute unit: approximately 105 items on V100, 2 · 10^5 on A100, and 10^5 on MI300X.The (32, 500) case is attributed to occupancy rather than being an outlier.Source: A. Portable layer (every environment) · p. 13
  • Use collapse(2) on QIP and CIP, persist Q and read-only item tables across generations, and make genes the fastest-varying layout dimension.The recommendations describe these as portable source-level choices.Source: A. Portable layer (every environment) · p. 13
  • Reduce Evaluation within a warp or wavefront, and remove DetermineElite from the device pipeline by reducing on the host or fusing a device-wide reduction into Evaluation.The suggested reduction uses per-thread accumulators over strided item chunks, followed by shuffle-reduce and one store per chromosome.Source: A. Portable layer (every environment) · p. 13
  • Use eight to sixteen CPU cores as the honest baseline, and fuse barriers where dependencies permit to cut the pipeline from four device launches to two.QIP and observation write Q and x at identical indices, and CIP can cache the elite chromosome in shared memory or LDS.Source: A. Portable layer (every environment) · p. 13

B. In-house layer (V100 SXM2)

  • On V100, place item tables in constant memory through Ng ≤ 6553, shared memory through Ng ≤ 4915, then shared tiles of 128 items; treat 16 GB as a residency ceiling.Failed Large grids should use a smaller population or a higher-capacity environment, not a different algorithm.Source: B. In-house layer (V100 SXM2) · p. 13

C. Cloud layer (A100 80GB)

  • On A100, use 256–512-item cp.async tiles beyond Ng ≈ 16793, manage the 40 MB L2 window deliberately, and avoid MIG-partitioning a dense generation.The 80 GB capacity is intended to keep Large problem pairs resident.Source: C. Cloud layer (A100 80GB) · p. 13

D. Leadership layer (MI300X)

  • On MI300X, match teams to the CU mesh, keep item tables in Infinity Cache, and prioritize Evaluation's wavefront-level segmented reduction.The recommendation also cautions against recopying Q each generation and specifies the ROCm OpenMP offload toolchain.Source: D. Leadership layer (MI300X) · p. 13

VIII. CONCLUSION

  • 90×, 136×, and 155× over one core and 12×, 17×, and 16.6× over 72 host threads are the reported V100, A100, and MI300X geometric-mean speedups for one OpenMP 5 implementation.MI300X remains interactive, at tens of milliseconds per generation, deep into the Large class.Source: §VIII · p. 13
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