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Design and Analysis of a 2D Vernier Structure

Hüsna Yildiz, Rick Helmer

arXiv:2609.36083v1physics.ins-detcs.SYeess.SY

TL;DR

Finite delay lines can produce non-uniform quantization in a 2D Vernier TDC, making precise delay matching and calibration important. The paper implements a calibrated 2D TDC and reports 16.9 ps resolution, with DNL and INL below 0.5 LSB across tested PVT corners.

  • Problem

    Finite delay lines can produce non-uniform quantization, making precise delay matching and calibration critical for linearity.

    Source: §I · p. 1

  • Method

    The design uses a calibration loop to adjust voltage-controlled delay buffers in the X line and maintain timing alignment with the Y line.

    Source: C. Optional Enhancements and Design… · p. 1, §II · p. 2

  • Results

    The transfer curve shows approximately 16.9 ps resolution, while DNL and INL remain below 0.5 LSB across tested PVT corners.

    Source: §III · p. 6, §V · p. 7

  • Takeaways & Limitations

    The calibration loop effectively maintains timing alignment and improves the TDC's accuracy and robustness.

    Source: 3) Calibration · p. 5

    The study is limited to schematic-level simulations with a 5-bit design, unlike the cited 7-bit design with complete layout implementation.

    Source: §V · p. 7

Abstract

from arXiv · show

This paper presents the design and simulation of a 2D Vernier Time-to-Digital Converter (TDC) targeting less than 20 picosecond time resolution and 5-bit output resolution. The TDC comprises voltage-controlled delay buffers, NAND-based SR latches with reset functionality, and a calibration loop using a phase-frequency detector (PFD) and charge pump. The calibration loop dynamically adjusts delay mismatches to maintain consistent timing across process-voltage-temperature (PVT) corners, significantly improving linearity. Simulations show that the TDC achieves a resolution of 16.9 ps for tt corner and maintains DNL and INL below 0.5 LSB under all tested PVT conditions

I. Introduction

The 2D Vernier TDC quantizes time differences using two delay lines, but finite lines can produce non-uniform quantization, making precise matching and calibration important. The project targets high resolution and linearity in a stand-alone TDC design and simulation.

I. Introduction

  • The 2D Vernier TDC quantizes time differences through delay mismatches between two orthogonal delay lines arranged as a grid.When stage delays are integer multiples of the desired resolution, the quantization step is determined by their greatest common divisor.Source: §I · p. 1
  • Finite delay lines can cause non-uniform quantization, making precise delay matching and calibration critical; a larger Vernier plane can reduce abrupt diagonal transitions.The 2D Vernier structure also shortens delay lines and reuses taps across dimensions, offering benefits in jitter, power, quantization density, and range.Source: §I · p. 1

A. Design Objectives

  • The design targets time resolution better than 20 ps, 5-bit output resolution with 32 codes, and DNL and INL below 0.5 LSB.An optimized figure of merit is also a target.Source: A. Design Objectives · p. 1
  • Area minimization remained a core goal because area strongly affects power, although area is not included in the figure of merit.Area efficiency was considered throughout the design process.Source: A. Design Objectives · p. 1

B. Project Boundaries

Included

The project includes TDC design, optional delay calibration, and simulation-based evaluation across PVT corners and mismatch conditions. It excludes layout implementation and full system-level integration; the optional calibration loop adds design constraints and trade-offs.

Included

  • The included work covers 2D Vernier TDC design, optional charge-pump delay calibration, and Spectre simulations across PVT corners and mismatch conditions.Evaluation metrics include time resolution, energy per conversion, DNL/INL, transistor-width area, and FoM.Source: Included · p. 1

Excluded

  • Layout and post-layout simulations, as well as full system-level integration, are excluded.Source: Excluded · p. 1

C. Optional Enhancements and Design Boundaries

  • The optional calibration loop compensates for Start/Stop delay mismatches across PVT variations, but must converge reliably across corners and adds power and circuit complexity.The report states that the loop improves signal alignment on the Vernier plane, linearity, and overall system reliability.Source: C. Optional Enhancements and Design… · p. 1

II. Design Methodology

The design compares propagation across two delay-line dimensions, with SR latches at grid intersections encoding time differences. A calibration loop tunes the X-line delay to maintain the target stage-delay relationship, which simulations support across the described operating conditions.

II. Design Methodology

  • The 2D grid uses 9 X-line stages and 5 Y-line stages to create 45 intersections, each connected to an SR latch acting as a time comparator.The implementation uses voltage-controlled buffers in both lines and a calibration loop comprising a PFD and charge pump.Source: §II · p. 2
  • A 5:4 stage-delay ratio makes five Y stages equal four X stages; the TDC resolves one-quarter of the Y-stage delay.The calibration point is X=4, Y=5, where the differential delay is zero.Source: §II · p. 2
  • Calibration adjusts the X-line buffer control voltage to maintain the 4:5 delay relationship and keep resolution constant across process and temperature variations.The buffer bias is set by the loop to maintain the target ratio across PVT corners.Source: §II · p. 2, A. Voltage-Controlled Delay Buffer · p. 2

A. Voltage-Controlled Delay Buffer

B. Time Comparator: SR Latch

The NAND-based SR latch compares Start and Stop arrival times on the X and Y delay lines. Its outputs encode the TDC result, while a reset stage clears latch states between measurements.

B. Time Comparator: SR Latch

  • Each latch compares signal arrival times: Start arriving first sets the output high, while Stop arriving first makes it low.The inputs are Start and Stop, and the latch is NAND-based.Source: B. Time Comparator: SR Latch · p. 3
  • 32 SR latches represent the valid 5-bit output range, with each latch corresponding to one quantization point.For example, five high latches indicate a four-step delay difference between Stop and Start.Source: B. Time Comparator: SR Latch · p. 3
  • When Reset is high, an additional logic stage forces the output to zero, clearing latch states between measurements.When Reset is low, the stage is transparent and the output reflects the latch state.Source: B. Time Comparator: SR Latch · p. 3
  • Simulation confirms that a rising Start signal sets the latch output high and Reset pulls it back to zero.The latch circuit is shown in Figure 5; transistor sizes are summarized in Table II.Source: B. Time Comparator: SR Latch · p. 4, Figure 5 · p. 4, Table II · p. 4

C. Calibration

The calibration loop adjusts the X-line delay to align signals at the calibration point, with Start and Stop launched simultaneously so measured differences reflect delay mismatch. A zero-dead-zone PFD detects phase differences and directs the charge pump.

C. Calibration

  • The loop adjusts X-line delay to maintain zero timing difference at X = 4 and Y = 5, using simultaneous Start and Stop launches to isolate delay mismatch from external skew.Voltage-controlled buffers tune the X line.Source: C. Calibration · p. 4

1) Phase-Frequency Detector:

  • The selected eight-transistor PFD has zero dead zone, enabling it to detect minimal phase differences for picosecond-scale calibration.The passage attributes this architecture to.Source: C. Calibration · p. 4
  • The PFD raises UP when X arrives later than Y and DN when X arrives earlier, directing the charge pump to adjust delays.The PFD architecture is shown in Figure 7.Source: C. Calibration · p. 4, Figure 7 · p. 4

2) Charge Pump:

The charge pump converts PFD signals into a control voltage for the X-line buffers, and the calibration transient reaches a stable bias associated with signal alignment. The pump uses balanced charge and discharge paths and an RC loop filter.

2) Charge Pump:

  • The charge pump converts UP and DN into a control voltage for tuning the voltage-controlled buffers in line X.Accurate calibration requires matched sourcing and sinking currents and minimal output ripple.Source: 2) Charge Pump · p. 4
  • A parallel RC loop filter integrates charge-pump current and uses its second capacitor to stabilize the control voltage and reduce ripple.Asymmetric paths produced some delay mismatch, which transistor sizing was optimized to minimize.Source: 2) Charge Pump · p. 5

3) Calibration

III. Simulation and Results

Simulations report an approximately 16.9 ps resolution at the typical-typical corner and show DNL and INL peaks at Vernier-plane diagonal transitions. The reported design meets its specified requirements across tested PVT conditions.

III. Simulation and Results

  • The design consistently meets its specified requirements under all tested PVT conditions.The simulation used a 5e-13 time step, 5e-9 s transient duration, and 1.8 V supply.Source: §III · p. 5
  • Area estimates use 180 nm CMOS and calculate transistor area as total gate width multiplied by gate length.The total gate width is multiplied by a gate length of 180 nm.Source: §III · pp. 5–6
  • DNL and INL peaks occur at Vernier-plane diagonal transitions across the plotted corners.The initial DNL peak is attributed as likely arising from the Start signal's steeper rising edge after the first buffer.Source: Figure 12 · p. 6, Figure 13 · p. 6, §III · p. 6
  • Approximately 16.9 ps is the reported resolution at the tt corner, with the measured transfer curve closely aligned to the ideal response.Figure 14 compares the measured digital output with the ideal linear response over input time delays.Source: Figure 14 · p. 6, §III · p. 6

IV. Discussion

The implemented 2D Vernier TDC sets its resolution through the delay mismatch between its X and Y lines. Increasing the stage counts while keeping total line delays nearly equal can produce finer resolution, with trade-offs in power, area, and calibration complexity discussed in the following subsection.

IV. Discussion

  • With τX = 5/4τ and Y-stage delay τ, the implemented design's delay mismatch is Δ = 1/4τ.The section defines resolution as the difference between the delays of one X and one Y stage.Source: §IV · p. 6
  • The implemented configuration offers a balance between resolution, power, and area.Source: §IV · p. 6

A. Improving Resolution

  • Increasing the X and Y stage counts while keeping total delays nearly equal can make the theoretical resolution a smaller fraction of τ.The section gives NY = 31 and NX = 30 as an example, describing the resulting resolution as much smaller than the earlier Δ = 1/4τ case.Source: A. Improving Resolution · p. 7

B. Trade-Offs

The paper reports that the calibrated TDC meets its specified performance requirements across tested PVT corners, with DNL and INL below 0.5 LSB. Finer resolution carries area, power, and calibration-complexity trade-offs, and the study is limited to schematic-level simulations.

B. Trade-Offs

  • At NX = 30 and NY = 31, the design requires 930 SR latches and 61 delay buffers.The trade-off section says more delay stages increase SR-latch count quadratically.Source: B. Trade-Offs · p. 7
  • Larger arrays and longer signal paths result in higher dynamic and leakage power.Source: B. Trade-Offs · p. 7
  • When stage-delay differences become extremely small, precise calibration becomes harder, so finer resolution must be weighed against area, power, and circuit complexity.Source: B. Trade-Offs · p. 7

V. Conclusion

  • DNL and INL remain below 0.5 LSB across tested PVT corners, and the calibrated design meets its specified performance requirements.The paper cautions that comparison with is not entirely equivalent because that work uses 7-bit resolution and a complete layout, while this study uses 5-bit resolution and schematic-level simulations.Source: §V · p. 7

Appendix A Additional Figures

The appendix presents schematics for an inverter, a NAND gate, and an AND gate.

Appendix A Additional Figures

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