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cktFormer: Transformer-Based Approach for Automated Analog Circuit Design

Pasindu Dodampegama, Praveen Wijesinghe, Naveen Basnayake, Keshawa Jayasundara, Tharindu Bandaragoda

arXiv:2609.36752v1cs.LGcs.AR

TL;DR

Manual schematic design remains time-consuming, and analog circuit design remains manual. This paper proposes interlinked transformer models for component and connection prediction on graph-structured netlists; it reports a higher share of valid generated circuits than cktGNN.

  • Problem

    Manual schematic design is time-consuming, and analog schematic design remains manual despite automation in other electronic-design stages.

    Source: §I · p. 1

  • Method

    Interlinked transformer models use graph representations and self-attention to predict circuit components and electrical connections.

    Source: §III · p. 2, §V · p. 6

  • Results

    76.0% versus 67.5% of generated circuits are valid for this model and cktGNN, respectively.

    Source: §V · p. 6

  • Takeaways & Limitations

    The model can complete partially designed circuits and provide component and connection suggestions while preserving engineers' creative control.

    Source: §V · p. 6

    The model occasionally generates disconnected nodes for novel sequences, and performance degrades with limited training data.

    Source: §V · p. 6

Abstract

from arXiv · show

Circuit design is a complex and iterative process that requires expertise in electronic engineering. It involves selecting components while meeting performance constraints, such as power efficiency, cost-effectiveness, and signal integrity. However, manual design is time-consuming and prone to errors. Although other stages of the manufacturing pipeline have benefited from AI-driven optimizations, circuit design remains a bottleneck, limiting overall productivity. Generative AI and machine learning offer the potential to automate and improve this stage, boosting efficiency and accuracy. To address this, we introduce a dual transformer architecture that bridges the gap between AI and circuit design by leveraging attention mechanisms to model complex, non-sequential circuit relationships. Our approach structures netlist data into graph-based representations, enabling effective learning of circuit topology and component interactions. The system consists of two interlinked models: a node prediction model that proposes components and an edge prediction model that infers valid connections. This collaborative and decoupled design captures both component-level semantics and global structural coherence. In our experiments, this architecture outperforms recent models such as AnalogGenie and cktGNN in the validity of generated circuits. By addressing key limitations in existing methods, our work advances automation in electronics engineering and contributes a benchmark for AI-driven circuit synthesis.

I. INTRODUCTION

Schematic design is time-consuming and expertise-intensive, and analog schematic design remains manual despite automation in other electronic-design stages. The paper proposes interlinked transformer models for component and connection prediction, with iterative refinement of generated circuits.

I. INTRODUCTION

  • Manual schematic work can take weeks to months and requires extensive simulation and iteration to check feasibility and performance.When simulations reveal errors or unmet requirements, teams modify the design and reevaluate it, sometimes trading off feasibility, performance, cost, manufacturability, reliability, and compliance.Source: §I · p. 1
  • Analog schematic design remains manual and time-intensive despite automation across other electronic-design stages.The introduction identifies analog circuits' continuous signals and sensitive components as part of the challenge.Source: §I · p. 1

A. Our Contributions

  • Separate but interlinked transformer models predict circuit components and their connections to better capture circuit structure.The contribution list also describes an encoder-decoder transformer that processes structured graph data.Source: A. Our Contributions · p. 1
  • An iterative refinement mechanism removes incompatible or unconnectable components after each new node is added.The paper also reports preliminary evaluation of performance and generative capability, without giving results in this passage.Source: A. Our Contributions · pp. 1–2

II. RELATED WORK

Analog design automation remains challenging because analog circuits have tighter component interdependencies and less predictable behavior. Prior work includes sequential topology generation and simulation-guided reinforcement learning, each with a distinct approach.

II. RELATED WORK

  • Analog design automation remains challenging relative to mature digital automation because analog circuits have tighter component interdependencies and less predictable behavior.Researchers have explored sequential and graph-based methods, GPT models, language models, and graph neural networks.Source: §II · p. 2

A. Sequential Approaches

  • Sequential topology generation can produce circuits in one pass, but not all circuits can be efficiently represented in a strictly sequential form.This constraint may pose challenges for complex circuit designs.Source: A. Sequential Approaches · p. 2
  • AutoCkt uses deep reinforcement learning to iteratively propose design changes and refine them using circuit-simulation feedback.Its simulated test environment evaluates each design as the model updates its strategies.Source: A. Sequential Approaches · p. 2

B. Graph Neural Networks

Prior circuit-design work includes graph neural networks and transformers, while simpler instance-based methods have limitations in capturing global dependencies. The proposed framework uses interlinked transformers on circuit graphs to predict components and electrical connections.

B. Graph Neural Networks

  • Graph neural networks have been applied to circuit-property prediction and transistor sizing, and cktGNN introduced the Open Circuit Benchmark.The cited work describes GNNs as effective for graph-structured data and notes their potential to reduce reliance on costly simulations.Source: B. Graph Neural Networks · p. 2

C. Transformer Architectures

  • AnalogGenie uses an autoregressive transformer for topology generation, whereas this work separates component and connection prediction to improve structure learning and circuit validity.The passage points to Table II for the comparison but provides no table values here.Source: C. Transformer Architectures · p. 2
  • kNN performs strongly in moderately linear, data-rich systems but struggles with nonlinear topologies and global circuit dependencies.The passage identifies these limits as motivating a model that handles both components and their connections.Source: C. Transformer Architectures · p. 2

III. METHODOLOGY

  • The proposed framework uses interlinked models on structured circuit graphs: one proposes components and the other infers valid electrical connections.Self-attention is used to capture long-range dependencies and global context without imposing a predefined graph structure or linear ordering.Source: §III · p. 2

A. Component Encoding

Circuit components and terminals are represented as graph nodes, with component identities encoded for prediction and adjacency matrices representing connectivity. The node-prediction transformer uses this representation to propose components and extend the circuit.

A. Component Encoding

  • The component vocabulary assigns distinct identifiers to parts and terminals, and modeling pins individually supports fine-grained connectivity learning, especially for multiterminal components.MOSFET drain, source, and gate terminals are represented separately because they have distinct circuit roles.Source: A. Component Encoding · pp. 2–3

C. Node Prediction Model

  • The model overview places component and geometry encoding before node and edge prediction, followed by refinement to remove or connect unconnected nodes.The node model uses four transformer layers with four attention heads and is trained independently of the edge-prediction model.Source: Figure 2 · p. 3, C. Node Prediction Model · p. 3

B. Graph Encoding

  • A linear layer encodes the circuit graph for the transformer, with nodes representing components or ports and the adjacency matrix representing their connections.In the example described, matrix entries mark a voltage source connected to the N-MOSFET drain and gate.Source: B. Graph Encoding · p. 3

C. Node Prediction Model

  • The node-prediction encoder processes a fixed-dimension graph input of 310 features per node, and its decoder predicts components from a vocabulary of 894 entries.A predicted component adds a node and its corresponding adjacency-matrix row and column.Source: C. Node Prediction Model · p. 3

D. Edge prediction Model

The edge-prediction model infers component connections from encoded component lists, using either a one-pass non-cyclic design or an iterative cyclic design.

D. Edge prediction Model

  • The edge model uses encoded component lists to update embeddings with local and global connection context, then predicts connection probabilities for each node pair.The two architectures differ in input representation and internal configuration.Source: D. Edge prediction Model · p. 3

1) Non cyclic design:

  • The non-cyclic design predicts possible connections from a node sequence in a single forward pass.Each node has a 128-dimensional embedding; the model uses four encoder layers with eight attention heads and a feed-forward dimension of 256.Source: 1) Non cyclic design · p. 3

2) Cyclic Design:

  • The cyclic design iteratively predicts missing edges using an incomplete adjacency matrix as decoder input alongside node features.It is described as suited to partially designed circuits and uses an eight-head, six-layer Transformer with 0.1 dropout.Source: 2) Cyclic Design · p. 3

3) Graph Attention with Edge Bias:

The cyclic model incorporates edge information into graph attention, then uses pairwise node embeddings to estimate connection probabilities and apply a threshold for establishing edges.

3) Graph Attention with Edge Bias:

  • The cyclic model computes attention between existing node pairs and integrates edge information through a bias term derived from the binary adjacency matrix.A learnable linear projection produces a scalar edge bias shared across attention heads, guiding attention to respect circuit connectivity.Source: 3) Graph Attention with Edge Bias · p. 4

E. Edge probability calculation

  • Updated node embeddings are passed pairwise through a three-layer MLP with ReLU activations and LayerNorm to calculate connection probabilities.The sigmoid output represents the likelihood of an edge; an edge is established when it exceeds a predefined threshold.Source: E. Edge probability calculation · p. 4

F. Iterative Refinement Strategy: Post-Processing and Edge Refinement

Post-processing addresses disconnected or floating nodes in edge predictions, while the framework is also evaluated on continuing synthesis from incomplete circuits.

F. Iterative Refinement Strategy: Post-Processing and Edge Refinement

  • Autoregressive edge predictions can leave disconnected or floating nodes, limiting global structural coherence despite the node model’s ability to propose novel component sequences.The authors state that further steps are needed for physical validity and circuit consistency.Source: F. Iterative Refinement Strategy:… · p. 4
  • The refinement process symmetrizes pairwise edge probabilities and resolves conflicting or floating connections by selecting the most probable connection.The probability calculation is intended to ensure a symmetric generated adjacency matrix.Source: F. Iterative Refinement Strategy:… · p. 4

G. Partial Circuit Completion Capability

  • Unlike cktGNN and AnalogGenie, which focus on valid circuits under fixed constraints, this model is designed to extend partially completed schematics.The evaluation uses incomplete test-set circuits to measure prediction accuracy for subsequent components and their interconnections.Source: G. Partial Circuit Completion Capability · p. 4

IV. EXPERIMENT

Experiments use the AnalogGenie dataset and compare edge-prediction variants, node prediction, and training behavior against the stated evaluation setup.

A. Dataset

  • The benchmark contains 3,351 unique analog circuits, categorized by function and split into training and testing sets at a 9:1 ratio.It includes graphical and netlist representations and components such as resistors, capacitors, inductors, and transistors.Source: A. Dataset · p. 4

B. Baseline

  • The comparison includes CktGNN, LaMAGIC, AnalogCoder, and AnalogGenie as examples of graph-generation, masked-graph, code-generation, and autoregressive graph-modeling approaches.The experiments use the dataset used in AnalogGenie.Source: B. Baseline · p. 4, §IV · p. 4

C. Evaluation

  • Binary cross-entropy is averaged per epoch, with positive-class weighting differing between the cyclic and non-cyclic models; Figure 4 shows both models’ losses decreasing over epochs.The loss scales differ between the two graphs because the cyclic model uses wp = wn = 1 while wp is tuned for the non-cyclic model.Source: C. Evaluation · p. 4, Figure 4 · p. 5
  • The non-cyclic model achieves higher accuracy, recall, and F1 score, while the cyclic model achieves higher precision.The reported high recall for the non-cyclic model suits topologies where missing an edge is costly; cyclic precision reduces false positives where incorrect connections matter.Source: C. Evaluation · pp. 4–5, Table I · p. 5
  • Node prediction accuracy is relatively low with fewer than 10 preceding nodes and improves with more context, but becomes less consistent at higher positional indices.The authors attribute the instability to limited large-node samples.Source: C. Evaluation · p. 5
  • The authors report that limited training-dataset size constrains edge-prediction performance.Source: C. Evaluation · p. 5

D. Generation of valid circuits

The section defines circuit validity using connectivity, power-source, short-circuit, floating-component, and power-port criteria, then evaluates generated circuits on the test set. It relates validity to the edge and node prediction stages and presents an example generated circuit.

D. Generation of valid circuits

  • Validity requires a connected graph, a power source, no short circuits or floating components, and correctly connected power ports.Validation uses the test set with the same 9:1 training-to-testing ratio as the Analog Genie paper.Source: D. Generation of valid circuits · p. 5
  • Table II compares models by valid-circuit percentage; combined generation depends on both node and edge prediction, while edge-only prediction is expected to yield higher validity.The passage attributes this expectation to edge prediction's narrower task compared with generating an entire circuit.Source: D. Generation of valid circuits · p. 5, Table II · p. 5
  • Iterative refinement can further improve circuit validity by enforcing valid connections; Figure 6 shows an example generated with a randomly initialized adjacency matrix.The example combines the node prediction model with the non-cyclic edge prediction model for the listed input sequence.Source: D. Generation of valid circuits · p. 5, Figure 6 · p. 5

V. DISCUSSION

The discussion presents interlinked transformer models as a way to represent non-sequential circuit relationships and reports higher validity than cktGNN. It also notes limitations on novel sequences and with limited training data, alongside the potential for collaborative completion of partial circuits.

V. DISCUSSION

  • Interlinked node- and edge-prediction transformers use self-attention to model complex component relationships without imposing artificial linear constraints.The discussion presents this as addressing circuit design's non-sequential nature.Source: §V · p. 6
  • Novel component sequences can still produce disconnected nodes during edge prediction, and performance degrades with limited training data.The discussion identifies reliance on large datasets as a limitation of the transformer architecture.Source: §V · p. 6
  • The model generated 76.0% valid circuits versus 67.5% for cktGNN, while transformers handled novel component combinations and partial-circuit information better than GNNs.The comparison also notes that GNNs excel at capturing local graph structures.Source: §V · p. 6
  • Completing partial circuits could support a collaborative design assistant that suggests components and connections while preserving engineers' creative control.The suggested use is autocomplete during the design process.Source: §V · p. 6

VI. CONCLUSIONS AND FUTURE WORK

The conclusion presents a dual-transformer framework for analog circuit design and highlights its potential for completing partial circuits. Future work could extend the framework from topology generation toward component parameters, functional targets, commercial libraries, and circuit-specific tuning.

VI. CONCLUSIONS AND FUTURE WORK

  • The framework represents netlists as graphs and uses interlinked node- and edge-prediction transformers with self-attention to model interconnected, non-sequential circuits.The conclusion describes its circuit-generation performance as strong and its partial-circuit completion capability as a potential collaborative design aid.Source: §VI · p. 6
  • The authors propose future models that predict resistance and capacitance as well as topology, to improve utility for complete designs.They also propose user-defined functional targets, commercial EDA component libraries, and fine-tuning for specific circuit types such as amplifiers.Source: §VI · p. 6

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