Zephyr: An Efficient Audio Denoising System Using Spiking Neural Networks Enabled With A Sparsity-Aware Flexible FPGA PE Array

Motivation

• Smartphones, headphones, and hearing aids run audio-denoising ANNs despite tight power constraints and battery-life expectations.The paper identifies ANNs as computationally resource- and power-hungry.Source: §1 · p. 1
• SNNs offer potential power savings through high activation sparsity and low complexity, provided they are paired with appropriate hardware.Source: §1 · p. 1

Zephyr

• Spiking-FullSubNet requires matrix multiplication, addition, and elementwise multiplication across its encoding, spiking, and leakage operations.The proposed system combines a hardware-friendly algorithm with a flexible PE array and event-based memory reads to support these operations and exploit sparsity.Source: §1 · p. 1

Prior work

• SFSN and DPSNN report 15.20 dB and 14.70 dB, respectively, on the Intel-DNS challenge dataset.The passage characterizes these SNN approaches as using sparse binary activations to reduce computational complexity.Source: §2 · p. 1

Comparison scope

• Table 1 covers speech-enhancement performance and energy efficiency on Intel N-DNS, with ANN/SNN baseline energy costs following the operation-based proxy methodology.Source: Table 1 · p. 2

Prior work

• S5 sparse-11 matches Spiking-FullSubNet-XL at 15.20 dB SI-SNR with 3.2× lower effective compute and 5.37× lower memory at iso-accuracy.Its 0.463 µJ energy cost is an operation-count estimate using the Intel N-DNS proxy methodology, not a direct hardware measurement.Source: §2 · p. 2

3.1. Spiking-FullSubNet Architecture Overview

• The three sub-band branches use 5, 3, and 1 filtering taps, respectively, while Multi-Frame Deep Filtering applies coefficients to current and preceding STFT frames.The full-band branch extracts a global spectral embedding, and the sub-band branches combine it with neighboring frequency bins; the resulting data flow includes dense products, spike-driven accumulation, gated updates, normalization, and complex MACs.Source: §3.1 · p. 2, Figure 1 · p. 2

3.2. GSN Membrane Update: Original Formulation

• The original GSN membrane update uses a dynamic decay gate to control the relative contributions of the previous membrane state and current input.In floating point, each update involves two elementwise multiplications; Zephyr preserves the update structure while implementing gating products and rescaling with integer arithmetic.Source: §3.2 · p. 2

3.3. Hardware-Friendly Implementation Methods

• Zephyr applies QAT-based symmetric signed INT8 quantization to weights, non-spiking activations, and recurrent membrane states, reducing weights from 4MB to 1MB.A 255-entry sigmoid LUT produces unsigned 8-bit gate coefficients, and batch-normalization affine transforms are folded into bias and requantization parameters.Source: §3.3 · pp. 2–3

3.4. Energy Analysis Methodology

• Computational energy is estimated by weighting operation counts after zeroskipping by their corresponding costs; for 45 nm, 0.9 V CMOS, INT8 multiplication and INT32 addition cost 0.20 pJ and 0.10 pJ per operation, respectively.Full-model accounting includes membrane updates, channel-wise rescaling, LUT access, normalization, and deep filtering; this estimate is not measured FPGA energy and does not capture memory-access costs.Source: §3.4 · p. 3

4.1. Accelerator Architecture

• The accelerator combines an inference module, an FSM, and event-driven weight-reading memory; the memory maps active-neuron indices to weight addresses.The inference module integrates frame buffering, layer normalization, a PE array, and recurrent-state SRAM.Source: §4.1 · p. 3

4.2. PE Array Architecture

• One Hybrid PE array is time-multiplexed across gate computation, membrane and spike updates, and MFDF, avoiding operation-specific arithmetic duplication.For MFDF, pairs of PEs accumulate real and imaginary components over multiple filter taps.Source: §4.2 · pp. 3–4

4.3. Sparsity-Aware Computation

• Active spike indices are recorded before weight fetch, so only their weight vectors are read and accumulated, skipping inactive-spike DRAM accesses and PE operations.Dense execution instead fetches weight vectors for all spike entries, including zero-valued spikes.Source: §4.3 · p. 4, Figure 4 · p. 4

• The accelerator was implemented on a PYNQ-Z1 FPGA with 32 PEs operating at 100 MHz.Source: §5 · p. 4
• Evaluation used the Intel N-DNS Challenge dataset, measuring speech quality with SI-SDR and hardware performance with board-loop latency and sustained real-time factor.Source: §5 · p. 4
• Table 2 summarizes the accelerator implementation and compares it with prior speech-enhancement FPGA accelerators.Source: §5 · p. 4

• Zephyr is reported to perform high-quality audio denoising while achieving low power and processing latency.Source: §6 · p. 4
• The conclusion presents Zephyr as a neuromorphic hardware-software co-designed audio-denoising system.Source: §6 · p. 4
• The reported capabilities are stated for the Zephyr system as a whole, rather than as separate component-level results.Source: §6 · p. 4