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Vulnerability-Weighted Routing of Timing-Critical Nets for Configuration-Upset-Resilient SRAM-Based FPGAs

Mostafa Darvishi

arXiv:2610.00281v1eess.SYcs.ARcs.ETcs.PFcs.SYeess.SP

TL;DR

Conventional FPGA routing does not distinguish similarly fast routes with different susceptibility to configuration-induced delay. This paper adds continuous vulnerability and configuration-concentration costs to routing and selectively reroutes high-risk nets, reducing aggregate vulnerability while limiting nominal timing degradation.

  • Problem

    Conventional routing optimizes timing and congestion but does not distinguish routes with comparable nominal delay and different configuration-induced timing severity, which can consume path slack despite meeting fault-free timing constraints.

    Source: §I · p. 1

  • Method

    The method adds a continuous predicted-delay-to-slack vulnerability cost and a configuration-concentration penalty, selectively rerouting the highest-risk eligible nets while leaving unaffected routes fixed.

    Source: §I · p. 2

  • Results

    At p=5%, the method achieves approximately 41.7% lower aggregate vulnerability with only 1.0% mean critical-path-delay degradation and captures approximately 85.8% of the reduction obtained when four times as many nets are rerouted.

    Source: E. Overall Design Tradeoff · p. 12

  • Takeaways & Limitations

    Controlled hardware perturbations show that lower analytical vulnerability corresponds to lower measured configuration-induced delay, supporting configuration-aware vulnerability as a practical physical-design objective.

    Source: §VIII · p. 13

    Route ranking depends on delay and slack model accuracy, while the preferred rerouting fraction is benchmark-specific and should be retuned as timing margin, utilization, or reliability requirements change.

    Source: §VII · p. 12

Abstract

from arXiv · show

Conventional FPGA routing optimizes timing, congestion, and routability but does not distinguish routes with similar nominal performance and substantially different susceptibility to configuration-induced delay degradation. This paper presents a vulnerability-weighted routing methodology for SRAM-based field-programmable gate arrays (FPGAs) that incorporates predicted routing-fault severity directly into the routing objective. A continuous vulnerability cost relates delay perturbations caused by electrically attachable dormant routing resources to the available downstream timing slack, while a complementary configuration-concentration term discourages excessive localization of vulnerable resources. To limit implementation disruption, only the highest-risk nets are selectively ripped up and rerouted while unaffected routes remain fixed. The method is implemented on a Zynq UltraScale+ XCZU7EV using a Vivado/RapidWright-based flow and evaluated across four routed benchmarks against commercial timing-driven routing, vulnerability-agnostic rerouting, and binary vulnerable-resource avoidance. Controlled configuration-equivalent perturbations provide hardware-level validation. The proposed method reduces aggregate configuration-induced timing vulnerability by 41.7% with approximately 1.0% nominal timing degradation and captures 85.8% of the vulnerability reduction obtained at the expanded routing budget by rerouting only the highest-risk 5% of eligible nets. The results demonstrate that continuous vulnerability information can improve configuration-upset resilience with limited impact on nominal routing quality.

I. INTRODUCTION

Conventional FPGA routing balances timing, congestion, and routability, but does not distinguish routes with comparable nominal delay and different configuration-induced timing severity. The paper adds continuous vulnerability and configuration-concentration costs and selectively reroutes high-risk nets.

I. INTRODUCTION

  • Configuration upsets can electrically attach dormant resources, add loading, and increase combinational delay while silently consuming slack on routes that meet nominal timing constraints.Prior objectives do not distinguish similarly fast routes with different continuous distributions of configuration-induced delay severity.Source: §I · p. 1
  • The proposed flow augments timing and congestion costs with continuous timing-vulnerability and configuration-concentration terms, then selectively reroutes high-risk nets toward safer alternatives.Vulnerability reflects predicted delay consequences relative to available timing slack rather than a binary vulnerable-resource classification.Source: §I · pp. 1–2, Figure 1 · p. 2
  • The evaluation uses four structurally different benchmarks on a Zynq UltraScale+ XCZU7EV and compares against commercial timing-driven routing, vulnerability-agnostic routing, and binary resource avoidance.Controlled function-preserving routing perturbations test whether lower vulnerability scores correspond to lower measured configuration-induced timing degradation.Source: §I · p. 2

A. Timing-Driven FPGA Routing

  • Classical timing-driven routing frameworks optimize routability, congestion, and nominal path delay, while RapidWright and RWRoute enable customized timing-driven routing on commercial UltraScale+ devices.Their routing objective does not explicitly represent configuration-induced timing vulnerability.Source: A. Timing-Driven FPGA Routing · pp. 2–3

B. Reliability-Aware FPGA Physical Design

Prior reliability-aware FPGA physical-design methods target sensitive bits, bridging faults, fault occurrence, or functional error propagation. This paper instead assigns continuous timing-vulnerability costs to routing alternatives and models electrically attachable delay perturbations on a routed-resource graph.

B. Reliability-Aware FPGA Physical Design

  • Earlier reliability-aware FPGA design methods target configuration-bit sensitivity, bridging faults, fault occurrence, or functional error propagation rather than delay-perturbation severity relative to path slack.Vulnerability-analysis frameworks identify sensitive resources but do not determine routing tradeoffs against nominal cost.Source: B. Reliability-Aware FPGA Physical… · p. 3

C. Position of the Proposed Method

  • The proposed method scores routing alternatives by predicted delay increments from dormant-resource attachments relative to available slack, penalizes configuration-region concentration, and targets high-risk nets.It complements rather than replaces conventional timing and congestion costs, and is evaluated on commercial UltraScale+ routing resources.Source: C. Position of the Proposed Method · p. 3

A. Routed-Net and Perturbation Model

  • The routed-net model represents the post-route interconnect as a directed graph of routing nodes and programmable connections, with each net defined by its source-to-sink routing resources.Electrically adjacent configuration-induced delay candidates are associated with active routing edges.Source: A. Routed-Net and Perturbation Model · p. 3
  • Only delay-only perturbations that preserve intended Boolean connectivity are retained; candidates causing opens, logical shorts, or additional active drivers are excluded.Configuration-region associations are used for concentration scoring only when established by the extraction and mapping procedure.Source: A. Routed-Net and Perturbation Model · pp. 3–4

B. Slack-Exhaustion Severity

The method weights candidate routing perturbations by their predicted delay relative to downstream timing slack, then evaluates both total route vulnerability and its concentration across configuration regions.

B. Slack-Exhaustion Severity

  • Endpoint-specific setup slack avoids misestimating a branch perturbation’s timing consequence on multisink trees.A branch affects only sinks downstream of that branch, so net-wide slack may overestimate or underestimate its consequence.Source: B. Slack-Exhaustion Severity · p. 4
  • Candidate severity is the probability that predicted delay exceeds available slack, not the probability of a radiation-induced upset.The severity is conditional on the considered configuration perturbation; radiation-event probability can be added separately when application-specific exposure data are available.Source: B. Slack-Exhaustion Severity · p. 4

C. Edge and Route Vulnerability

  • Route vulnerability aggregates admissible delay-producing attachments by their predicted ability to consume downstream timing margin.It is a comparative routing metric, not an absolute system-failure probability.Source: C. Edge and Route Vulnerability · p. 4
  • The configuration-concentration index is higher when vulnerable resources are concentrated in fewer mapped configuration regions.Candidates without verified region associations still contribute to route vulnerability but are excluded from the concentration penalty.Source: C. Edge and Route Vulnerability · p. 5
  • The concentration penalty discourages localization of cumulative vulnerable resources; it does not imply one upset activates every candidate in a region.Aggregate vulnerability and configuration-space concentration are complementary route properties.Source: C. Edge and Route Vulnerability · p. 5

A. Selective High-Risk Net Identification

The method ranks legally reroutable signal nets by baseline vulnerability and searches alternatives using a cost that augments conventional timing and congestion objectives with vulnerability and concentration terms.

A. Selective High-Risk Net Identification

  • Eligible nets exclude clock, dedicated, static, and implementation-locked routes, and the prescribed rerouting fraction determines which nets are selected.Unselected nets retain their original placement and routing.Source: A. Selective High-Risk Net… · p. 5
  • The routing objective combines timing-driven cost, negotiated congestion, configuration-induced vulnerability, and configuration concentration.The terms are normalized to a common dimensionless range, with normalization parameters held fixed across alternatives in each experimental configuration.Source: A. Selective High-Risk Net… · p. 5
  • Incremental route search retains conventional timing and congestion penalties while adding vulnerability and a concentration penalty for increases in route-level concentration.The complete candidate route is evaluated using its full concentration term, and candidates without verified configuration associations contribute to vulnerability but not concentration.Source: A. Selective High-Risk Net… · p. 6

C. Selective Rip-Up-and-Reroute Procedure

The flow reroutes selected high-risk nets while preserving unselected routes and placement, accepting changes only when vulnerability improves without violating timing or routing constraints.

C. Selective Rip-Up-and-Reroute Procedure

  • Selected nets are processed in descending baseline vulnerability, while routes outside the selected population remain preserved.Each selected route is temporarily removed and reconstructed using the vulnerability-augmented routing cost.Source: C. Selective Rip-Up-and-Reroute… · p. 6
  • If no legal alternative satisfies timing and routing constraints, the original route is restored rather than forcing a reliability modification.This concentrates computational effort and physical-design disruption on nets contributing most strongly to configuration-induced timing vulnerability.Source: C. Selective Rip-Up-and-Reroute… · p. 6

D. Timing Preservation and Route Acceptance

  • A reroute is accepted only when it provides an actual vulnerability benefit and preserves complete-design timing and routing legality.The placement remains unchanged, and final legality, routed timing, and route preservation are independently checked.Source: D. Timing Preservation and Route… · p. 6
  • The bounded optimization permits controlled nominal-quality tradeoffs but bars illegal congestion, uncontrolled timing degradation, and changes to nets outside the protection set.The flow scores perturbations, aggregates net-level vulnerability, guides selective routing decisions, and validates the resulting design.Source: D. Timing Preservation and Route… · pp. 6–7, Figure 2 · p. 7

V. EXPERIMENTAL METHODOLOGY AND BENCKMARKS

The evaluation uses four structurally varied benchmarks and a fixed-placement comparison flow on a Zynq UltraScale+ platform, with Vivado checking legality and timing after custom routing.

A. FPGA Platform and Physical-Design Flow

  • The experiments target a ZCU104 board with a Zynq UltraScale+ XCZU7EV-2FFVC1156 and use Vivado 2025.1 for baseline implementation and post-route timing.RapidWright extracts routed resources and timing; RWRoute enables partial rerouting while preserving previously routed resources, followed by Vivado validation.Source: A. FPGA Platform and Physical-Design… · p. 7
  • Five baseline instances per benchmark use distinct implementation seeds, and each comparison strategy shares the same frozen placement within an instance.Custom-routing results are accepted only when routing is legal and the timing-preservation condition is satisfied.Source: A. FPGA Platform and Physical-Design… · p. 7

B. Benchmark Suite

  • The four benchmarks span a five-stage RV32I processor, an eight-lane fixed-point MAC, an AXI4-Stream/dual-port-BRAM buffer, and a two-master/four-slave AXI subsystem.Their routing structures range from localized processing and arithmetic to memory-adjacent streaming and distributed, arbitration-dependent, high-fan-out paths.Source: B. Benchmark Suite · pp. 7–8, Figure 3 · p. 8
  • Target clocks are 100, 200, 150, and 125 MHz for B1–B4, respectively, and only eligible signal nets enter the routing population.Clock, static, dedicated, and explicitly fixed networks are excluded.Source: B. Benchmark Suite · p. 8

C. Routing Baselines and Experimental Parameters

The routing comparison holds the selected-net population constant across custom-routing alternatives, while controlled perturbations test whether lower-scored routes also show lower measured timing degradation.

C. Routing Baselines and Experimental Parameters

  • R1–R3 reroute the same net set at each selected-net fraction, separating routing-cost effects from differences in net selection.R1 uses nominal RWRoute; R2 applies binary avoidance; R3 uses the continuous vulnerability and configuration-concentration costs.Source: C. Routing Baselines and Experimental… · p. 8
  • The nominal proposed configuration applies the same weights across four benchmarks and implementation seeds, with a maximum permitted WNS degradation of 2% of the applicable clock period.The binary threshold is based on the baseline resource population, with the nominal experiment using the 75th percentile of nonzero vulnerability.Source: C. Routing Baselines and Experimental… · pp. 8–9

D. Controlled Routing-Fault Validation

  • Matched baseline and vulnerability-reduced routes undergo configuration-equivalent perturbations that preserve Boolean connectivity and the active signal path.Candidates are matched as closely as possible by resource class, physical region, and predicted severity range.Source: D. Controlled Routing-Fault Validation · p. 9
  • Ten reference–perturbed acquisition pairs are taken per candidate, with the reference remeasured after each perturbation to suppress drift.A pair is rejected if the restored reference differs from its calibrated baseline by more than three standard deviations.Source: D. Controlled Routing-Fault Validation · p. 9
  • Validation spans four benchmarks, severity ranges, physical regions, and routing-resource classes; direct configuration-memory perturbations cross-check electrical and timing response, not radiation rates or mission-level failure probability.The directly perturbed subset uses independently verified configuration-bit-to-routing-resource associations.Source: D. Controlled Routing-Fault Validation · p. 9

E. Evaluation Metrics

The evaluation measures vulnerability reduction alongside conventional routing quality and controlled-fault timing effects. At a 5% rerouting budget, the continuous method provides the largest reported vulnerability reduction, with diminishing returns as more nets are rerouted.

E. Evaluation Metrics

  • Aggregate vulnerability reduction measures the design-level benefit of protecting only selected nets, while configuration-concentration reduction is evaluated analogously using F(R_n).Unselected nets remain unchanged.Source: E. Evaluation Metrics · p. 9
  • Evaluation covers WNS, critical-path delay/Fmax, routed wirelength, resource overuse, runtime, selective-routing success, and hardware-subset timing perturbation and ranking agreement.Aggregate results are reported across five implementation seeds, alongside results for B1–B4.Source: E. Evaluation Metrics · p. 9

A. Vulnerability Reduction

  • At 5%, proposed routing reduces aggregate vulnerability by 39.8%, 36.4%, 43.7%, and 46.9% for B1–B4, respectively, averaging approximately 41.7%.Binary avoidance averages approximately 26.0% under the same selected-net population; the advantage of the proposed method appears across all four architectural classes.Source: A. Vulnerability Reduction · p. 9, Table III · p. 10
  • The proposed routes reduce configuration concentration by approximately 18.6–28.7% across the four benchmarks.The reported reduction means vulnerability improvement is not merely an exchange for another highly concentrated set of exposed resources.Source: A. Vulnerability Reduction · p. 9

B. Benefit of Selective Rerouting

  • Rerouting the highest-risk 1%, 2.5%, 5%, 10%, and 20% of eligible nets reduces aggregate vulnerability by approximately 18.9%, 31.7%, 41.7%, 46.2%, and 48.6%, respectively.Increasing the rerouted share from 5% to 20% yields only 6.9 additional percentage points of reduction despite quadrupling the number of modified nets.Source: B. Benefit of Selective Rerouting · p. 10
  • Binary avoidance reduces aggregate vulnerability by approximately 11.8%, 19.9%, 26.0%, 30.4%, and 32.8% at rerouting fractions of 1%, 2.5%, 5%, 10%, and 20%, respectively.Its benefit also saturates, but at a lower level than the continuous formulation.Source: B. Benefit of Selective Rerouting · p. 10
  • At 5%, the proposed method reduces aggregate routing vulnerability by 41.7%, versus 26.0% for binary avoidance and 3.4% for nominal RWRoute, with approximately 1.0% critical-path-delay degradation and 1.5% routed-wirelength increase.The continuous formulation consistently provides the largest vulnerability reduction, with pronounced diminishing returns beyond this operating point.Source: B. Benefit of Selective Rerouting · p. 10, Figure 4 · p. 10

C. Timing, Routing, and Computational Cost

At the 5% rerouting point, the method limits nominal timing and wirelength costs while selectively routing most eligible nets to lower-vulnerability alternatives. Hardware perturbations show reduced measured delay shifts and fewer cases exceeding downstream timing margin.

C. Timing, Routing, and Computational Cost

  • At p=5%, mean critical-path-delay degradation is approximately 1.0%, with routed wirelength increases of 1.2–1.8%, and accepted implementations satisfy the WNS-preservation constraint.The largest timing penalty occurs for B2, while B3 has the smallest penalty.Source: C. Timing, Routing, and Computational… · pp. 10–11
  • As p rises from 1% to 20%, mean critical-path-delay penalties increase from approximately 0.3% to 1.8%, while wirelength increases from 0.4% to 4.1%.The paper identifies p≈5% as favorable for this benchmark suite, not as a universal constant.Source: C. Timing, Routing, and Computational… · p. 11
  • Approximately 87–93% of selected nets admit a legal lower-vulnerability alternative, and selective-routing runtimes are approximately 14 to 32 s per design after vulnerability extraction.About 95% of eligible nets remain unchanged; nets without an acceptable alternative are restored to their original implementation.Source: C. Timing, Routing, and Computational… · p. 11

D. Controlled Hardware Validation

  • Measured median delay shift fell from approximately 110 ps for baseline routes to 67 ps for vulnerability-weighted routes, a reduction of about 39%.Across 160 matched perturbations, the fraction exceeding downstream timing margin also fell from approximately 27.5% to 13.1%.Source: D. Controlled Hardware Validation · p. 11, Figure 5 · p. 11
  • For the subset with independently verified configuration-bit mappings, direct configuration-memory perturbations produce timing shifts consistent with deterministic configuration-equivalent variants.The authors make no inference about radiation-event probability or device upset cross section.Source: D. Controlled Hardware Validation · pp. 11–12

E. Overall Design Tradeoff

Rerouting the highest-risk nets yields substantial vulnerability reduction with modest nominal routing costs, while the discussion bounds the result to its tested device, flow, and conditional timing-severity framework. The conclusion identifies broader device coverage and joint placement-and-routing as future work.

E. Overall Design Tradeoff

  • At p=5%, rerouting the highest-risk nets reduces aggregate vulnerability by approximately 41.7%, with 1.0% mean critical-path-delay degradation and 1.5% wirelength increase.This captures approximately 85.8% of the vulnerability reduction obtained when four times as many nets are rerouted.Source: E. Overall Design Tradeoff · p. 12

VII. DISCUSSION AND LIMITATIONS

  • In the evaluated benchmarks, most achievable reduction comes from modifying a small high-risk fraction of eligible nets, while timing and congestion remain part of route selection.The configuration-concentration term is a routing-concentration surrogate, not an upset-probability model; concentration in one region does not mean one upset activates all associated perturbations.Source: §VII · p. 12
  • The experiments cover one Zynq UltraScale+ device family and one physical-design flow, so vulnerability data and normalization parameters must be regenerated for a new architecture or implementation.The routing stage uses fixed placement; joint reliability-aware placement and routing could expose additional solutions but enlarges the optimization space.Source: §VII · p. 12
  • Route quality depends on delay-perturbation, severity, and slack-model accuracy; the preferred rerouting fraction and coefficients are benchmark-specific, and the perturbation experiments do not measure radiation-event frequency or mission-level failure probability.The paper frames the method as reducing conditional timing vulnerability given a configuration perturbation, not as a complete radiation-reliability prediction framework.Source: §VII · p. 12

VIII. CONCLUSION AND FUTURE WORK

  • The conclusion proposes extending the method to joint vulnerability-aware placement and routing, additional FPGA families and utilization regimes, and device- and environment-specific upset probabilities.Radiation-calibrated exposure weights and correlated multi-fault scenarios are identified as possible extensions toward system- and mission-level optimization.Source: §VIII · p. 13
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