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Neuromorphic Pseudo-Random Number Generators with a Low Power Hardware Implementation

Jafar Shamsi, Navid Akbari, Sonia Sennik, Aaron Gruber, Wilten Nicola

arXiv:2610.00719v1cs.NEq-bio.NC

TL;DR

Conventional PRNG hardware can require resource- and power-intensive operations, motivating whether brain-inspired balanced chaotic neural dynamics can serve as low-power generators. This paper builds balanced spiking-network NPRNGs and finds that software and FPGA versions pass all 15 NIST SP800-22 tests, with fabricated hardware producing 120 Kbits per second at 5.45 mW.

  • Problem

    Whether brain-inspired chaotic balanced neural dynamics can provide low-power hardware PRNGs remains a research question, as conventional PRNG operations can be resource- and power-intensive in hardware.

    Source: Introduction · p. 1

  • Method

    The paper uses balanced spiking neural networks to generate bit streams from spike-time sequences and evaluates their randomness with NIST SP-800-22.

    Source: Introduction · p. 1, Creating and Testing Random Bit… · p. 5

  • Results

    Both software and FPGA NPRNGs passed all 15 NIST SP800-22 tests; fabricated hardware generated 120 Kbits per second at 5.45 mW.

    Source: Discussion · p. 12

  • Takeaways & Limitations

    The results demonstrate the feasibility of low-power random number generation with NPRNGs for potential edge-computing applications.

    Source: Discussion · p. 13

    Formal evaluation against side-channel or fault exploitation remains future work.

    Source: Discussion · p. 12

Abstract

from arXiv · show

Pseudo-random number generation often requires trade-offs among quality, power consumption, and bandwidth to produce unpredictable sequences of numbers. The brain, on the other hand, efficiently generates unpredictable output complex network dynamics occurring in a high-dimensional state. This state, which is hypothesized to be chaotic, relies on the balance between excitation and inhibition. Here, we investigated if computational models of these chaotic balanced states can be harnessed for Neuromorphic Pseudo-Random Number Generators (NPRNGs) in low power hardware. We successfully constructed a balanced spiking neural network model consisting of leaky-integrate-and-fire neurons that could be readily implemented in low power FPGAs and used as a NPRNG. The prototyped NPRNG consumed 3.24 mW during operation and produced pseudo-random numbers at 120kbps. In both hardware and software instantiations, NPRNGs produce high-quality random numbers as validated by standard metrics for testing RNG quality.

Introduction

This work uses chaotic, balanced spiking-neural-network dynamics as a basis for low-power neuromorphic pseudo-random number generators (NPRNGs). The networks produced high-quality random bit streams, and FPGA prototypes generated numbers at 120 kbps.

Motivation

  • Conventional PRNGs generate deterministic bit streams through repeated operations on a seed, but the complex operations for high-quality output can be resource- and power-intensive in FPGAs and ASICs.PRNGs are used in advanced computational problems and as inputs for generative AI.Source: Introduction · p. 1
  • Balanced excitation and inhibition can produce asynchronous chaotic dynamics, motivating efficient random-number generation with neuromorphic hardware primitives.The passage notes that in larger networks, neurons become increasingly independent and behave as if driven by a Gaussian process.Source: Introduction · p. 1

Network dynamics

  • Sufficiently strong but subcritical connectivity produced spike-chaos and Poisson-like firing in small networks, whereas stronger connectivity caused rate-chaos and poor bit streams.Connectivity parameter g critically determined PRNG quality; not all balanced spiking-network configurations were suitable.Source: Introduction · p. 1

Results

  • Fabricated NPRNG devices generated random numbers at 120 kbps using 5.45 mW across all circuit components, while Lattice Radiant Software reported 3.24 mW for the FPGA device alone.The pseudo-random number bit streams were high quality and matched or exceeded other established PRNGs.Source: Introduction · p. 2

Network design

  • Binary weights gave each NPRNG a large O(2^N^2) parameter space and allowed reconfiguration by disabling neurons with inhibitory bias currents.The passage describes each NPRNG as unique because of its binary weights.Source: Introduction · p. 2

Results

The results evaluate whether binarized and quantized balanced spiking networks retain irregular, chaotic dynamics and produce spike streams that perform comparably to established PRNGs under NIST testing. They report FPGA throughput and power, demonstrate a Monte Carlo estimate of π, and distinguish the algorithm from fixed, non-programmable chaos oscillators.

The excitatory/inhibitory balanced state in quantized spiking neural networks.

  • With N = 256, binarized weights retained irregular, Poisson-like spiking (mean CV 0.99), while quantized parameters also retained irregular spiking (mean CV 0.68) and rate-chaos transitions.The binarized network’s trajectories changed after a single spike deletion or connection-weight flip; quantization and binarization preserved the overall dynamical features needed for implementation.Source: The excitatory/inhibitory balanced… · pp. 2–4, Figure 1 · p. 4

Creating and Testing Random Bit Streams with Balanced SNNs

  • A dynamic lookup-table transform yielded streams with about 50% passing every NIST test and another 40% passing 14/15 for one weight matrix, whereas a naive spike-index transform produced detectable non-randomness.Across 10^4 weight matrices, about half passed all 15 tests, but average quality was slightly poorer than for the single matrix; networks with N < 64 may have stable non-chaotic attractors. Input signals could also drive different trajectories and bitstreams from identical initial conditions.Source: Creating and Testing Random Bit… · pp. 5–6
  • The dynamic lookup table produced poorer NIST results in rate-chaos than spike-chaos, with passed-test counts negatively correlated with mean CV (ρ = −0.8147, p ≪ 10^-4).Rate-chaos bursts introduce temporal autocorrelations; two adjacent-bit XOR decimation passes eliminated systematic Dieharder short-range correlation failures, while all 100 configurations passed TestU01 SmallCrush.Source: Creating and Testing Random Bit… · pp. 6–7
  • To check for cycles, a quantized NPRNG generated 1.1 TB of random bits, with each bit corresponding to one spike; searching the final 1,000 bits found no repetitions.Source: Creating and Testing Random Bit… · p. 6
  • ≈50% of streams from the LCG, BBS, Mersenne Twister, and both NPRNGs passed all 15 NIST tests, while none from the quadratic congruential or modular exponentiation generators did.Across these generators, an additional ≈40% of streams passed 14 tests, and the remaining 10% passed 10–13 tests.Source: Creating and Testing Random Bit… · p. 7, Figure 2 · p. 8

NPRNGs in hardware run on approximately 5 mW of power.

  • The FPGA implemented 256 neurons using 76 percent of iCE40UP5K SLICEs; at 6 MHz, software estimated 3.24 mW consumption and simulated NPRNG throughput of 120 kbps.Board current was measured at 1.65 mA at 3.3 V, resulting in 5.45 mW total power consumption. The design eliminated dedicated multipliers by mapping SNN dynamics to distributed shift-and-add operators.Source: NPRNGs in hardware run on… · p. 9
  • Unlike Asymmetric Boolean Chaos Oscillators46, which provide fixed, non-programmable entropy generation, the algorithm offers algorithmic versatility.Source: NPRNGs in hardware run on… · p. 10
  • The hardware NPRNG’s Monte Carlo estimate of π was 3.1413, based on 2.2 million uniform random numbers forming 1.1 million ordered pairs.The estimate used the proportion of points below the red line in the unit square to approximate π/4.Source: Figure 3 · p. 11
  • The FPGA microarchitecture pipelines synaptic and neuron dynamics, with two stages for h[n] and five stages each for r[n] and v[n].The data path includes memory, a multiply-accumulate block, synaptic and neuron dynamics, function block F[n], and look-up table L[y].Source: Figure 3 · p. 11
  • Xilinx Vertix-7 and Artix-7 FPGAs have 5-input LUTs, while iCE40UP5K and Cyclone V SoC have 4-input LUTs.Source: NPRNGs in hardware run on… · p. 12

Discussion

The discussion presents balanced spiking NPRNGs as low-power hardware generators with NIST-tested statistical quality, while noting their low bandwidth and that cryptographic security remains unproven.

Discussion

  • 5.45 mW in fabricated hardware produces a 120 Kbits-per-second bit stream, and the balanced spiking NPRNG passes all 15 NIST SP800-22 tests at rates similar to or higher than other PRNGs.The paper also characterizes the design as a low-power generator for edge computing.Source: Discussion · pp. 12–13
  • The number of configurable NPRNGs grows geometrically with network size, but the current design’s approximately 120 kbps bandwidth is low; ASIC or dedicated neuromorphic implementations may improve it.For a network of N neurons, the paper gives O(2N2) unique configurable NPRNGs and expects bandwidth increases while power remains sub-milliwatt.Source: Discussion · p. 12
  • Statistical randomness is validated across software and FPGA implementations, but cryptographic security and resistance to state-reconstruction, side-channel, or fault attacks remain unestablished.The authors describe structural sensitivity to localized perturbations and a complex O(N2)-bit recurrent-weight key as potential security advantages, not formal guarantees.Source: Discussion · p. 12
  • The balanced recurrent SNN can provide entropy for stochastic computing and probabilistic inference, while the same logic can be reconfigured as a reservoir-computing accelerator for temporal data.Using native spiking primitives avoids clock-domain and routing overhead from traditional PRNG macros, supporting resource-constrained edge computing.Source: Discussion · p. 13
  • A proposed follow-up is an analog spiking-network true RNG, with analog or mixed-signal ASIC implementations and SNN-based physically unclonable functions also identified as directions.The paper also notes that analog implementations may offer low energy use and mentions near-memory or in-memory computing technologies.Source: Discussion · p. 13

Author contributions statement

WN and AG supervised the project; WN, NA, JS, and SS contributed to its research, hardware, and manuscript preparation.

Code Availability Statement

The code is available at ModelDB for referee access and will be made public upon manuscript acceptance.

Code Availability Statement

  • Code is hosted at https://modeldb.science/2018267 with referee access password rx114 and will be made public upon manuscript acceptance.Source: Code Availability Statement · p. 13

Methods

The methods model excitatory/inhibitory balanced spiking dynamics, convert spikes into bits with a dynamic lookup table, and co-design a hardware datapath evaluated with NIST randomness tests.

Spiking Neural Networks and the Excitatory/Inhibitory Balanced State

  • The network models balanced excitatory/inhibitory leaky-integrate-and-fire neurons with threshold-and-reset voltage dynamics, filtered synaptic currents, and bipolar weights.Each neuron receives exactly N/2 positive weights, making the specified weight balance exact for every neuron.Source: Spiking Neural Networks and the… · p. 14

Generating Uniform Random Bit Sequences from a Spiking Neural Network with a Dynamic Lookup Table

  • A dynamic lookup table maps spike events to output bits by advancing neuron indices modulo N and indexing a randomly permuted binary vector balanced between zeros and ones.The vector contains N/2 zeros and N/2 ones.Source: Generating Uniform Random Bit… · p. 14

The NIST-SP-800-22 Package for Testing PRNGs

  • The NIST SP 800-22 evaluation uses 15 tests under an independent, identically distributed Bernoulli null hypothesis, requiring every reported result to pass for selected multi-result tests.The strict rule applies to Non-overlapping Template Matching, Random Excursions, and Random Excursions Variant tests.Source: The NIST-SP-800-22 Package for Testing… · p. 15

Microarchitecture of the NPRNGs

  • The hardware co-design removes synaptic multipliers by adding weights when spikes occur, and combines resource sharing with pipelining to limit area while restoring throughput.The arithmetic uses 32-bit fixed point, with 16 integer and 16 fractional bits; the overall microarchitecture has O(N^2) space and O(N) time complexity.Source: Microarchitecture of the NPRNGs · pp. 15–16

Additional Methods for Each Figure

  • Figure-specific methods tested single-spike response deletion and a weight flip after 2 seconds, and used quantized network parameters with dt = 2^-10.A separate parameter sweep varied connection strengths and synaptic time constants across 1,000 simulations per parameter set until 108 bits/spikes were produced for NIST testing.Source: Additional Methods for Each Figure · pp. 17–18

Supplementary Information · Supplementary Videos

Supplementary Video 1 visualizes a 0.3-second simulation of an excitatory/inhibitory balanced network, showing neuron activity, a spike raster, and voltage traces.

Supplementary Videos

Supplementary Section S1: Parameter Complexity Space

The NPRNG’s constant-row-sum constraint allows [C(N, N/2)]^N weight matrices, which scales like 2^(N^2) for large N—effectively the same scaling as unconstrained binary weights.

Parameter Complexity Space

  • Each NPRNG weight-matrix row has N/2 positive and N/2 negative values, yielding C(N, N/2) configurations per row and [C(N, N/2)]^N across N rows.The rows are permutations of a vector containing equal numbers of positive and negative values.Source: Supplementary Section S1: Parameter… · p. 19
  • For large N, the number of weight matrices satisfying the constant-row-sum condition scales like 2^(N^2), effectively the same as without a row-sum constraint.This is the stated asymptotic result for the constrained NPRNG weights.Source: Supplementary Section S1: Parameter… · p. 19

Supplementary Section S2: Simulations

The simulations first verified software–hardware consistency, then generated and evaluated random-bit streams using a two-phase protocol and strict NIST SP 800-22 pass criteria.

Supplementary Section S2: Simulations

  • Matching weights and seeds produced perfectly aligned hardware and software spike rasters; software then generated approximately 10^8 bits across 100 streams of 10^6 bits each.The experiments used 65.49 core years of CPU time across Digital Research Alliance of Canada clusters.Source: Supplementary Section S2: Simulations · p. 19
  • A 16-bit LFSR initialized the network with 2^16 distinct configurations, using different weights, a look-up table, and a seed for each generation phase.Different seeds were used to ensure diverse random-number generation.Source: Supplementary Section S2: Simulations · p. 20
  • Simulations with different network parameters stopped when the generated output reached the 115MB threshold.The network ran for a specified duration after initialization before bit capture began.Source: Supplementary Section S2: Simulations · p. 20
  • NIST SP 800-22 results counted as passed only when every test instance met the minimum pass-rate criteria for both P-value and Proportion metrics.Raw reports were parsed into CSV files and processed with Python scripts.Source: Supplementary Section S2: Simulations · p. 20

Supplementary Section S3: Throughput of the microarchitecture

The section analyzes how pipelining changes throughput by reducing critical-path delay while adding register overhead. It identifies an intermediate pipeline depth as a sweet spot.

Supplementary Section S3: Throughput of the microarchitecture

  • Without pipelining, the minimum is 256 clocks per time step, and the clock period is set by the critical-path delay Tcp.The throughput calculation also identifies the clock period Tclk and clocks per time step Nclk.Source: Supplementary Section S3: Throughput… · p. 20
  • Each time step processes 256 neurons; with S pipeline stages, the design uses 256+S clock cycles because the last neuron must be updated before the next time step.The pipelined clock period is determined by the maximum stage delay; equal stage delays are assumed for the approximation.Source: Supplementary Section S3: Throughput… · p. 20
  • Pipelining increases throughput when THpip > THno−pip.The section defines throughput as the number of neurons processed per unit time.Source: Supplementary Section S3: Throughput… · p. 20
  • An intermediate pipeline depth is a sweet spot: added stages reduce critical-path delay, while register overhead grows roughly with S^2 and can eventually dominate.The passage describes the delay reduction as growing linearly with S·Tcp and register overhead as growing roughly with S^2·Treg.Source: Supplementary Section S3: Throughput… · p. 20

Supplementary Section S4: Expected Cycle Time

The section estimates cycle times for the discretized balanced spiking network: finite state space guarantees an eventual cycle, while the birthday paradox predicts cycle detection becomes likely earlier.

Supplementary Section S4: Expected Cycle Time

  • With three 32-bit variables per neuron, the finite state space guarantees a cycle by its size at the parameters considered (N = 256, nbits = 32, D = 3).The guarantee follows from the pigeon-hole principle.Source: Supplementary Section S4: Expected… · p. 21
  • The birthday paradox predicts that the probability of detecting a cycle rises dramatically before the pigeon-hole maximum, although the approximate threshold is not specified in the supplied text.The passage introduces an approximate value, but it is missing from the supplied text.Source: Supplementary Section S4: Expected… · p. 21
  • A numerical evaluation of Lorenz96 found that cycle periods increase exponentially with system size [26].The passage describes Lorenz96 as a spatiotemporal system of coupled chaotic Lorenz systems.Source: Supplementary Section S4: Expected… · p. 21

Supplementary Figures

The supplementary figures examine how coupling, quantization, synchronization, and network structure affect spiking dynamics and NPRNG behavior. They also relate spike-train statistics to random-number quality and test methods for generating distinct NPRNGs.

Supplementary Figures

  • In non-quantized and quantized N = 256 networks, stronger coupling produced variable bursts; lower coupling had Poisson-like inter-spike intervals, while the strongest couplings had mean CV > 1.The non-quantized networks used binarized weights; all operations were quantized in the quantized networks.Source: Supplementary Figures · p. 22, Figure S1 · p. 22, Figure S2 · p. 23
  • A 250 ms input current transiently synchronized the balanced quantized network, whereas a 750 ms input maintained synchrony in perpetuity despite chaotic dynamics.After the short input ended, the neurons eventually desynchronized.Source: Figure S3 · p. 24
  • In the balanced quantized network, cross-correlations were weak and scaled approximately as N^-1, while autocorrelations showed prominent peaks between refractory non-firing periods centered at zero.The correlations were computed from a 1,000-second simulation of a network with N = 256.Source: Figure S4 · p. 25
  • Mean CV was inversely correlated with the average number of NIST tests passed (ρ = −0.9029 at N = 128; ρ = −0.6818 at N = 256; ρ = −0.8147 at N = 128; ρ = −0.9538 at N = 512).The passage reports p ≪ 10^-4 for each correlation; Supplementary Figure S5 also gives best-fit slopes and intercepts for N = 128, 256, and 512.Source: Figure S5 · p. 26
  • A balanced excitatory/inhibitory network with circularly shifted rows in its weight matrix stabilized on periodic spiking, and its reported lookup-table bits cycled at twice the neurons’ period.The network was quantized, and the weight matrix had 50% excitatory and 50% inhibitory connections.Source: Figure S6 · p. 27
  • As network size increased with coupling scaled as g = 2^-6√N, Supplementary Figure S7 tracks eventual spiking cessation and the maximum Lyapunov exponent.The figure reports cessation proportions because the non-spiking state is bistable with other attractors; its red line marks a zero Lyapunov exponent.Source: Supplementary Figures · p. 28, Figure S7 · p. 28
  • Supplementary Figure S8 maps average NIST tests passed and resulting spike-train coefficient of variation for N = 128, 256, and 512.The heat maps show these measures across the tested conditions.Source: Figure S8 · p. 29
  • Inhibiting neurons generated a different spike raster and enabled multiple NPRNGs from one network; randomly inhibiting three neurons did not appreciably change NIST-tested quality at N = 256.Inhibition used sub-threshold bias currents, equivalent to setting the inhibited neurons’ postsynaptic weights to zero.Source: Figure S9 · p. 30
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