Source-linked AI summary
U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
Federico Villani, Nico Canzani, Marc-André Wessner, Philippe Sauter, Enrico Zelioli, Andrea Cossettini, Christoph Leitner, Luca Benini
TL;DR
Miniaturized ultrasound probes need synchronized transmit excitation across multiple elements, while existing platforms can have limited channels or closed timing devices. U-Sonic provides an open-source, memory-mapped RISC-V transmit peripheral; its 8-channel implementation was verified and physically implemented, and occupies 14.9 kGE.
Problem
Miniaturized ultrasound probes need synchronized excitation across multiple elements, while existing platforms can have limited MCU channels or keep timing in closed devices.
Source: §I · p. 1Method
U-Sonic is an open-source RISC-V peripheral exposing up to 16 independently programmable, synchronized pulser cores through memory-mapped registers.
Source: §I · p. 1Results
14.9 kGE for the 8-channel instance, approximately 14.3% of the 104 kGE RISC-V SoC; RTL matched a Python reference across 4,379 checked cycles and was also tested on FPGA.
Source: §III · pp. 3–4Takeaways & Limitations
The paper presents a compact, reproducible transmit subsystem for multi-element ultrasound research and releases its RTL, register descriptions, verification collateral, and software support.
Source: §I · p. 1, §IV · p. 4The current peripheral lacks per-channel delay and a drive stage, and focusing and steering are left for a delay-stage extension.
Source: E. Multi-Channel Synchronization and… · p. 3
Abstract
from arXiv · showhide
Miniaturized ultrasound (US) probes require programmable and synchronized transmit (TX) excitation across multiple elements, while existing compact platforms often rely on limited microcontroller (MCU) pulse generators or closed-source fixed-function pulser devices. We present U-Sonic, an open-source digital US TX peripheral integrated into a 32-bit RISC-V system-on-chip (SoC). The implemented SoC integrates 8 pulser cores, while the parameterized architecture supports up to 16 channels. Each core generates single- or dual-tone bursts with programmable period, duty cycle, pulse count, polarity, and idle level, together with optional inverted stop pulses for active damping. A shared memory-mapped Open Bus Interface (OBI) enables synchronous start and stop of arbitrary channel subsets and supports composite bipolar, gated, and three-level excitation schemes. Functional correctness was verified in Verilator against a Python golden model over 4379 checked cycles across directed and randomized configurations, and confirmed on a Terasic DE10-Lite field-programmable gate array (FPGA). The design was synthesized and placed-and-routed in IHP 130 nm. The post-layout area in kilo gate equivalents (kGE), scales as 1.65 kGE plus 1.66 kGE per channel. The 8-channel instance occupies 14.9 kGE, corresponding to approximately 14.3% of the 104 kGE SoC. The register-transfer level (RTL), register descriptions, verification collateral, and software support are released as open source.
I. INTRODUCTION
Miniaturized ultrasound probes need precisely synchronized excitation across multiple elements, but existing platforms offer limited channel counts or keep excitation timing in closed, fixed-function devices. U-Sonic addresses this with an open-source, processor-visible transmit peripheral, with verification and implementation collateral released for reuse.
I. INTRODUCTION
- Coherent firing, aperture selection, and beamforming require synchronized excitation of several transducer elements.The number of elements and precision of excitation determine miniaturized probes’ front-end capabilities.Source: §I · p. 1
- Existing compact platforms use limited MCU pulse channels or proprietary fixed-function pulsers, while prior open scanners generally do not expose reusable RTL.A reported 16-channel 130 nm beamformer did not release design files or a processor-visible register interface.Source: §I · p. 1
- U-Sonic is an open-source peripheral exposing multi-element burst generation as memory-mapped registers in a RISC-V SoC [16], with up to 16 independently programmable, synchronized pulser cores behind an OBI.Source: §I · p. 1
- The verification flow used Verilator and a Python golden model for directed and randomized configurations, with functional confirmation on a Terasic DE10-Lite FPGA.The supplied passage describes the flow but does not report cycle counts.Source: §I · p. 1
- The RTL, register descriptions, verification documentation, driver software, and physical implementation files are released under a permissive license.The design was also synthesized and placed-and-routed in IHP 130 nm.Source: §I · p. 1
A. System Overview
U-Sonic integrates parallel pulser cores into Croc through an OBI-to-register bridge. Each core has an independent burst configuration, while shared controls support synchronous starts and stops of selected channels.
A. System Overview
- Eight parallel pulser cores generate programmable logic-level excitation at chip I/Os, each with an independent burst configuration.A shared interface can start or stop any subset synchronously.Source: A. System Overview · p. 1
- An OBI-to-register bridge exposes the pulser cores to the RISC-V processor for configuration and multi-channel transmission triggers.U-Sonic is integrated as a Croc OBI peripheral and reuses the SoC’s processor, memory, debug, and software infrastructure.Source: A. System Overview · pp. 1–2
- Fig. 1 depicts the Croc integration, IHP 130 nm layout, and pulser architecture, including configuration, control strobes, gated clocks, and status write-back.Table I is identified as a comparison of ultrasound transmit timing generators.Source: Figure 1 · p. 2, Table I · p. 2
B. Croc Platform Overview
Croc is an open-source, 32-bit MCU-class RISC-V SoC designed for education and domain-specific hardware integration. Its user domain and development infrastructure support custom memory-mapped IP and system validation.
B. Croc Platform Overview
- Croc is an open-source 32-bit MCU-class SoC built around the CVE2 RISC-V core, with configurable instruction-set options and an optional application-specific extension interface.It is designed as a compact, extensible platform for education and domain-specific hardware integration.Source: B. Croc Platform Overview · p. 2
- The Croc domain contains the processor, SRAM, optional DMA, debug support, and memory-mapped peripherals connected through a single-cycle OBI crossbar.Independent instruction and data interfaces enable concurrent access to separate SRAM banks.Source: B. Croc Platform Overview · p. 2
- The user domain exposes OBI interfaces, external I/Os, and interrupts for custom IP, with bare-metal software, simulation, FPGA prototyping, and an open IHP 130 nm implementation flow.Higher-throughput peripherals can access on-chip SRAM through an OBI manager interface.Source: B. Croc Platform Overview · p. 2
C. Peripheral and Register Interface
U-Sonic connects behind Croc’s peripheral demultiplexer as an OBI subordinate. Repeated per-core register windows and shared control registers configure and coordinate the pulser cores.
C. Peripheral and Register Interface
- The peripheral is an OBI subordinate behind Croc’s peripheral demultiplexer and occupies a 4 kB address window, driving 8 outputs through 16 mA pads.The passage identifies the UART, GPIO, and timer blocks as neighboring peripherals.Source: C. Peripheral and Register Interface · pp. 2–3
- Each core has a 0x20 register window, and the shared general register bank follows the N core windows at offset N·0x20.Shared START, STOP, and EN fields are 16 bits wide, setting a maximum of 16 cores; per-core clock gates use EN to keep inactive cores static.Source: Table II · p. 3, C. Peripheral and Register Interface · p. 3
- The state machine’s F1 and F2 states generate the tone phases, while Stop supplies inverted damping periods and a stop strobe returns the core to Idle.Zero-count phases are skipped.Source: Figure 2 · p. 3
- Core-local and shared register banks are specified in HJSON and translated into SystemVerilog register logic and C headers, with a Croc bare-metal driver wrapping the headers..Source: C. Peripheral and Register Interface · p. 3
D. Pulser Core
Each pulser core uses a five-state machine to generate programmable single- or dual-tone bursts, with optional inverted stop pulses and configurable polarity and idle level.
D. Pulser Core
- The five states are Idle, F1, F2, Stop, and Done, with 16-bit phase and 8-bit pulse counters.During F1 and F2, each period lasts Np cycles and the output is high for Ns cycles.Source: D. Pulser Core · p. 3
- Np ranges from 2 to 65,535 cycles, while each phase generates 0–255 pulses at one-clock-cycle resolution.At 100 MHz, one clock cycle is 10 ns; setting either phase's pulse count to zero skips it, enabling single- or dual-tone bursts.Source: D. Pulser Core · p. 3
- CNT_STOP appends inverted periods of the last active phase to reduce transducer ringdown; INVERT_OUT sets active-phase polarity, and IDLE_OUT sets Idle and Done levels.STATUS exposes the current state and a READY flag for software polling.Source: D. Pulser Core · p. 3
- Configuration registers must remain unchanged during an active burst; a shared CTRL write starts or stops selected cores, with stop taking priority and resetting both counters.Selected cores leave Idle on the following clock edge, while a stop returns a core to Idle within one cycle.Source: D. Pulser Core · p. 3
E. Multi-Channel Synchronization and Drive Modes
A shared control register synchronizes start and stop commands across selected channels, and independently configured cores can form composite drive schemes. The current design uses a common time base without per-channel delay.
E. Multi-Channel Synchronization and Drive Modes
- One shared CTRL write starts or stops any selected output on the same clock edge, avoiding sequential software triggering and providing cycle-accurate synchronization.Each selected core is controlled through the shared register.Source: E. Multi-Channel Synchronization and… · p. 3
- Independently configured cores support bipolar bursts, gated bursts, and three-level drives of +V, 0, and −V across a load.The three-level scheme uses different switch points and an inverted output.Source: E. Multi-Channel Synchronization and… · p. 3
- The current peripheral generates periodic dual-tone bursts on a common time base but has no per-channel delay, pattern memory, or drive stage.A delay stage for focusing and steering is left as future work.Source: E. Multi-Channel Synchronization and… · p. 3
III. IMPLEMENTATION AND RESULTS
The design was verified against a Python model and demonstrated on an FPGA, then physically implemented in IHP 130 nm. The 8-channel instance occupies 14.9 kGE, and the comparison notes that the design lacks per-channel delay and a high-voltage drive stage.
III. IMPLEMENTATION AND RESULTS
- Across 4,379 checked cycles, RTL matched the Python golden model without discrepancies; the 8-channel instance occupies 14.9 kGE, about 14.3% of the 104 kGE SoC.The implemented instance has 8 channels, while the architecture supports up to 16 synchronized TX channels.Source: §III · pp. 3–4
- On a Terasic DE10-Lite FPGA, a representative subset of pulse configurations produced observed waveforms and multi-channel synchronization.The FPGA test supplements the directed and randomized Verilator checks.Source: §III · p. 3
- Fig. 3 depicts the F1/F2 burst phases and inverted stop pulses, and two same-edge-started cores producing a three-level load drive.The drive uses different switch points and the invert flag rather than per-channel delay.Source: Figure 3 · p. 4
- The design was synthesized and placed-and-routed in IHP 130 nm using the ETH EZ130 8T standard-cell library, Yosys, and OpenROAD.Gate equivalents are referenced to that library's NAND2 cell.Source: §III · p. 4
- Compared with representative TX timing generators, U-Sonic combines programmable burst and polarity controls with synchronous triggering through memory-mapped OBI, but lacks per-channel delay and a high-voltage drive stage.Its RTL and register descriptions are openly released.Source: §III · p. 4
IV. CONCLUSION
The work demonstrates a compact, reproducible TX subsystem for multi-element ultrasound front-end research, with RTL verification, FPGA prototyping, and physical implementation in IHP 130 nm.
IV. CONCLUSION
- The TX subsystem is presented as a compact and reproducible platform for multi-element ultrasound front-end research.The design was functionally validated and physically implemented in IHP 130 nm.Source: §IV · p. 4
- Future work will focus on silicon characterization of the taped-out SoC and integration of a programmable per-channel delay stage for TX focusing and steering.Source: §IV · p. 4
- The release includes RTL, register descriptions, verification collateral, and software support.The materials are available as open source.Source: §IV · p. 4