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Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology

Wajid Ali, Muhammad Hadir Khan, Dalton Gaddy, Matthew Guthaus

arXiv:2610.02401v1cs.AR

TL;DR

Clock meshes can reduce skew and variation but consume scarce routing tracks, and backside power delivery offers low-resistance metal for a possible alternative. This paper explores backside clock meshes in OpenROAD with Bayesian design-space search and SPICE verification. Across four designs, backside meshes outperform corresponding frontside meshes on reported clock metrics, and their skew spread under variation is smaller.

  • Problem

    Backside power delivery offers low-resistance metal, but a backside mesh must accommodate the power grid, reach frontside flip-flops through TSVs, and undergo transistor-level evaluation.

    Source: §I · p. 1

  • Method

    The paper builds an OpenROAD backside-mesh flow and uses multi-objective Bayesian exploration with full-network HSPICE verification of every design point.

    Source: §I · pp. 1–2

  • Results

    45% lower worst-case skew on average than the same-LCB-tier frontside mesh; the backside mesh’s Ibex skew spread under Monte Carlo is one third of the frontside mesh’s.

    Source: B. Backside vs. Frontside · p. 3, D. Skew Under Variation · p. 4

  • Takeaways & Limitations

    On the four evaluated benchmarks, backside meshes beat identical frontside meshes in skew, slew, power, and frontside wiring, while retaining their lead under process and supply variation.

    Source: §VI · p. 4

Abstract

from arXiv · show

Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power delivery creates a new option: it adds thick, low-resistance metal layers on the back of the wafer, and the power grid does not consume all of them. Flip-flops remain on the frontside; a backside mesh therefore cannot drive them directly, and every connection passes through a through-silicon via. We present the first design-space exploration of backside clock meshes, implemented in OpenROAD on GT2N, a 2 nm nanosheet technology. Four benchmarks (1,938 to 15,311 flip-flops) are explored with multi-objective Bayesian optimization, and every design point is verified by transistor-level SPICE simulation, since the cyclic mesh cannot be evaluated by static timing analysis. Across all four designs, the backside mesh consistently outperforms an identical frontside mesh, with on average 45% lower skew, 25% lower sink slew, 4.5% lower power, and 28% less frontside clock wiring, and its skew spread under 10,000-sample Monte Carlo is a third of the frontside mesh's.

I. INTRODUCTION

Clock meshes reduce skew and variation but consume routing resources, while backside power delivery offers low-resistance metal that may be available for clocking. This paper explores whether a backside mesh remains beneficial after accounting for TSV connections, rail cuts, and transistor-level simulation requirements.

I. INTRODUCTION

  • Backside power delivery adds thick, low-resistance metal layers, and GT2N backside wires have 3.5× lower resistance per micron than M6–M9 and 22× lower than M4/M5.These metal tracks are not all used by the power grid.Source: §I · p. 1
  • Prior backside clocking work has focused on clock trees; the paper states that backside clock meshes had not yet been explored.Backside metals have also been used for tree trunks and selected clock nets.Source: §I · p. 1
  • A backside mesh must fit around the power grid, connect frontside flip-flops through TSVs that cut buried power rails, and be evaluated with transistor-level simulation.The shorted cyclic network cannot be evaluated by static timing analysis.Source: §I · p. 1, Figure 1 · p. 1
  • The paper presents a first backside clock-mesh construction flow and a multi-objective Bayesian exploration with full-network HSPICE verification of every design point.The flow is implemented in OpenROAD on GT2N, a 2 nm nanosheet BSPDN technology.Source: §I · pp. 1–2
  • Across all four designs, backside meshes have lower skew, maximum sink slew, and frontside clock wirelength than corresponding frontside meshes, and are less sensitive to variation.The comparison uses four benchmarks and includes 10,000-sample Monte Carlo analysis.Source: §I · p. 2

II. BACKSIDE CLOCK MESH SYNTHESIS

The synthesis flow constructs a backside mesh while accommodating the existing power grid and routing clock connections back to frontside sinks through TSVs and local clock buffers.

II. BACKSIDE CLOCK MESH SYNTHESIS

  • The construction flow places the mesh on backside tracks around the power grid, crosses between sides through TSVs and buried power rails, and connects frontside sinks through local clock buffers.The flow follows power-grid construction.Source: §II · p. 2

A. Target Technology

The target is GT2N, an open-source 2 nm nanosheet technology with buried power rails and backside power delivery.

A. Target Technology

  • GT2N provides fourteen frontside metal layers and four backside metals; BM1/BM2 are 3.5× less resistive per micron than M6–M9 and 22× less resistive than M4/M5.Cross-side connections use TSV cells modeled as a 6 Ω series resistance.Source: A. Target Technology · p. 2

B. Mesh Construction over a Backside PDN

The mesh uses backside tracks left available after power-grid construction, while a frontside buffer architecture drives the mesh and returns the clock to sink clusters.

B. Mesh Construction over a Backside PDN

  • Backside mesh wires use horizontal BM2 and vertical BM1 tracks left available after power-grid construction, shifting or removing wires that conflict with power straps.Vias at remaining intersections form a single electrically shorted mesh net.Source: B. Mesh Construction over a Backside PDN · p. 2

C. Clocking Architecture and Buffering

  • A frontside buffer tree drives mesh-driver inputs, and the shorted mesh averages their arrival differences before sink connections return through TSVs and local clock buffers.Drivers occupy alternating grid intersections in a checkerboard, halving driver and TSV count without changing the wire grid.Source: C. Clocking Architecture and Buffering · p. 2, Figure 2 · p. 2
  • The exploration consistently prefers small mesh drivers (x1–x4), even on the largest design.The LCB tier is sized independently and regenerates the clock edge for small flip-flop groups.Source: C. Clocking Architecture and Buffering · p. 2

D. TSV Insertion and Buried Power Rail Breaking

The construction flow routes clock through TSVs while cutting buried power rails at their landings, then connects frontside flip-flops through clustered local clock buffers. This reduces sink crossings by sharing one LCB and sink TSV among a bounded cluster of flip-flops.

D. TSV Insertion and Buried Power Rail Breaking

  • For clock TSVs carrying the clock net through the BPR layer, the flow cuts the rail at every landing by the TSV footprint plus 0.224 µm clearance on each side and removes floating fragments.The largest design requires about 2,500 cuts; power delivery is unaffected because remaining rail pieces are fed through their own via stacks.Source: D. TSV Insertion and Buried Power Rail… · pp. 2–3
  • Drive TSVs connect mesh drivers, while sink TSVs connect LCB inputs; Ibex uses 41 drive TSVs and 382 sink TSVs at a 5 µm pitch.A clock TSV carries the clock through the buried power rail layer using the same via-stack structure as the rail-to-backside-grid connection.Source: D. TSV Insertion and Buried Power Rail… · p. 2

E. Local Clock Buffers and Sink Clustering

  • Flip-flops join the nearest tap with an available cluster slot, and each cluster receives one LCB and one sink TSV.With Ffanout = 6, Ibex uses 382 LCBs for 1,938 flip-flops; the same LCB tier connects frontside baselines to their mesh without TSVs.Source: E. Local Clock Buffers and Sink… · p. 3

III. DESIGN-SPACE EXPLORATION

The design-space exploration jointly tunes four interacting mesh parameters with a multi-objective Bayesian search, using infeasible trials to steer later sampling. Experiments evaluate four benchmarks in OpenROAD and use transistor-level HSPICE simulation for clock-network metrics.

III. DESIGN-SPACE EXPLORATION

  • The four mesh parameters are searched jointly with MOTPE, which natively handles categorical choices and learns parameter combinations while minimizing worst-case sink skew and clock-network power.Each full-flow evaluation plus HSPICE simulation takes 10–50 minutes, making exhaustive search impractical; one-at-a-time sweeps can miss parameter interactions.Source: §III · p. 3, Table I · p. 3
  • Trials are infeasible when routing fails, a flip-flop is missing or fails to toggle, or worst sink slew exceeds 10% of the clock period; these trials still steer sampling.The four parameters interact enough to require a per-design joint search.Source: §III · p. 3, Table I · p. 3

IV. EXPERIMENTAL SETUP

  • Nominal metrics come from full-network transistor-level HSPICE simulations in OpenROAD on GT2N at TT, 0.7 V, and 25 °C.GT2N provides libraries and device models at a single corner.Source: §IV · p. 3
  • The four benchmarks are Ibex, JPEG, Minimax, and FlooNoC; 300–500 trials are run per design, and most infeasible trials fail the slew bound at sparse pitches.Sink locations are held identical across clock networks on each design, and backside power straps are checked with OpenROAD IR analysis.Source: §IV · p. 3

A. Variation Model

The variation analysis uses 10,000 HSPICE samples per network on Ibex with independently drawn device and wire variation. Across the four designs, the skew–power frontier falls steeply in skew as power rises from the sparsest feasible pitch.

A. Variation Model

  • Each Ibex Monte Carlo run uses 10,000 HSPICE samples, with device σ following N3 nanosheet projections, wire σ following, and independent draws for every device and wire element.Nominal values are GT2N's; the variation parameters are listed in Table IV.Source: A. Variation Model · p. 3

A. Pareto Frontiers

  • Across all four designs, skew falls steeply as power rises from the sparsest feasible pitch.Fig. 3 shows the skew–power frontier for each design.Source: A. Pareto Frontiers · p. 3
  • Representative Table II points are selected at the frontier knee, and each frontside baseline uses the identical grid, pitch, and driver configuration.These choices set the reported operating points and comparison baseline.Source: A. Pareto Frontiers · p. 3

B. Backside vs. Frontside

Across the evaluated designs, the backside mesh improves skew, slew, power, and frontside clock wirelength relative to the frontside mesh with the same LCB tier, with a small latency cost. On Ibex, sharing backside metal layers with the clock mesh keeps reported supply drops within the strap-sizing budget.

C. Power Delivery

  • On Ibex, worst-case VDD drop is 30.7 mV for the backside configuration versus 32.2 mV for the frontside mesh, while VSS drop rises from 16.8 to 22.5 mV; both remain within budget.The backside configuration shares BM1/BM2 with the clock mesh and cuts buried power rails at TSV sites.Source: C. Power Delivery · pp. 3–4

B. Backside vs. Frontside

  • The backside mesh lowers worst-case skew by 20% on JPEG and 49–57% on the other three designs (45% on average), and sharpens worst sink slew by 16–38% versus FS+LCB.It uses 1.5–6.5% lower clock power and 20–40% less frontside clock wirelength; latency rises 2–10 ps on three designs and falls on Minimax. The direct-attach frontside mesh's worst sink edge is 2.6–4.7× slower and exceeds the 10% slew budget on Minimax.Source: B. Backside vs. Frontside · p. 3, Table II · p. 4

D. Skew Under Variation

On Ibex, the backside mesh has the smallest mean skew and skew spread among the evaluated networks. Its skew standard deviation is one-third of the frontside mesh’s in 10,000-sample Monte Carlo results.

D. Skew Under Variation

  • Table V reports Monte Carlo clock skew on Ibex from 10,000 HSPICE samples per network.Source: Table V · p. 4
  • The backside mesh has the smallest mean skew and spread among the evaluated networks.The Monte Carlo comparison includes a conventional TritonCTS tree.Source: D. Skew Under Variation · p. 4
  • 0.34 ps is the backside mesh’s σ_skew, one-third of the frontside mesh’s and one-fifth of the tree’s.Source: D. Skew Under Variation · p. 4

VI. CONCLUSION

The paper presents an OpenROAD construction flow and design-space exploration for backside clock meshes on BSPDN technology. Across four benchmarks, the backside mesh outperforms an identical frontside mesh in skew, slew, power, and frontside wiring, including under process and supply variation.

VI. CONCLUSION

  • Across four benchmarks, the backside mesh beats an identical frontside mesh in skew, slew, power, and frontside wiring, and retains its lead under process and supply variation.Source: §VI · p. 4
  • The OpenROAD flow builds the mesh around the backside power grid, reaches it through TSVs that cut buried power rails, and connects frontside sinks through a local clock buffer tier.Source: §VI · p. 4
  • Every design point is verified in SPICE as part of the backside-mesh design-space exploration.Source: §VI · p. 4

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