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A Timing-Robust Frequency-Interleaved ADC with Embedded Analog Fourier Transform
Xingchen Chao, Yunqiang Xu, Qiang Yu, Christian Adam, Qiang Li
TL;DR
Timing errors are a fundamental challenge in high-speed ADCs, particularly in time-interleaved architectures. This paper uses an embedded analog Fourier transform to implement frequency interleaving, then demonstrates a calibration-free 10-bit, 13-GS/s ADC with measured Nyquist performance.
Problem
Timing errors in time-interleaved ADCs are frequency-dependent and become more severe as sampling rates and interleaving factors increase.
Source: §I · p. 1Method
An 8-point charge-based analog Fourier transform embedded in the sub-ADC capacitive DAC provides frequency interleaving, with a lossless implementation of its complex irrational coefficients.
Source: §I · p. 2, §III · p. 4Results
At Nyquist, the 10-bit, 13-GS/s ADC measures 45.8-dB SNDR and 56.1-dB SFDR.
Source: §V · p. 7Takeaways & Limitations
The frequency-interleaved prototype eliminates timing-error calibration and achieves performance described as competitive with time-interleaved implementations.
Source: §V · p. 8
Abstract
from arXiv · showhide
Timing errors represent a fundamental challenge in high-speed analog-to-digital converters (ADCs). This paper presents a frequency-interleaved architecture with inherent robustness to timing errors. The frequency interleaving is achieved by an embedded analog Fourier transform (AFT), allowing accurate channel spacing. The charge-based passive AFT is able to share the capacitor array with the capacitive DAC of the subsequent data conversion. A circuit implementation for the complex-valued irrational coefficients in the AFT matrix is proposed, which eliminates the device-ratio-induced systematic errors. Measured at 10b 13GS/s, the calibration-free ADC achieves 45.8-dB SNDR and 56.1-dB SFDR at Nyquist. The ADC consumes 26.4mA from a single 1V supply, resulting in a Walden FoM of 12.7 fJ/conv.-step.
I. INTRODUCTION
High-speed ADCs face increasingly demanding bandwidth and sampling-rate requirements, while timing errors in time-interleaved architectures are difficult to correct. This work demonstrates a calibration-free frequency-interleaved ADC using an embedded analog Fourier transform, with measured 10-bit, 13-GS/s performance.
I. INTRODUCTION
- Timing errors in time-interleaved ADCs are frequency-dependent and become more severe at higher sampling rates and larger interleaving factors.Offset and gain mismatches are relatively straightforward to mitigate because they are independent of input frequency.Source: §I · p. 1
- Calibration approaches estimate skew using reference channels, signal statistics, or test signals, then correct it through analog delay tuning or digital filtering.Bandwidth-mismatch calibration has been explored more narrowly; calibration adds design overhead, and estimation accuracy can depend on input statistics and WSS.Source: §I · p. 1
- Hybrid filter-bank frequency interleaving reduces each sub-ADC’s bandwidth, but unique channel center frequencies require customized filters and mixers whose responses are difficult to match.The paper identifies Fourier-transform-based channelization as a route to frequency interleaving, while noting that a compelling timing-robust FI ADC had not yet been demonstrated.Source: §I · p. 2
- 45.8-dB SNDR and 56.1-dB SFDR at Nyquist were measured in the 10-bit, 13-GS/s prototype, which needs no timing-error calibration.Fabricated in 28-nm CMOS, it consumes 26.4 mW and achieves a 12.7 fJ/conv.-step Walden FoM.Source: §I · p. 2
- An 8-point charge-based AFT embedded in the sub-ADC capacitive DAC enables frequency interleaving; a lossless circuit implementation addresses systematic errors from irrational coefficients.The paper presents a 10-bit, 13-GS/s prototype and reports calibration-free timing robustness.Source: §I · p. 2
II. AFT-BASED FREQUENCY INTERLEAVING: ARCHITECTURE AND TIMING ROBUSTNESS
The proposed frequency-interleaved architecture uses an analog Fourier transform to channelize a broadband input. Its channels act as complex FIR filters, and a digital inverse transform reconstructs the time-domain signal.
II. AFT-BASED FREQUENCY INTERLEAVING: ARCHITECTURE AND TIMING ROBUSTNESS
- AFT derives frequency-domain outputs from discrete-time input samples using the orthogonality of the discrete Fourier basis.The DFT expression defines the mathematical foundation of the illustrated 4-point AFT.Source: §II · p. 2
- Each AFT channel is equivalent to a complex FIR filter with a distinct center frequency, enabling broadband channelization across −fs/2 to fs/2.For the illustrated 4-point operation, the weighted sum uses coefficients 1, −j, −1, and j.Source: §II · p. 2
- The digital IDFT reconstructs the time-domain signal by weighting and summing the channelized spectral components.In the system description, Y[k] denotes AFT-generated frequency components and x′[m] the reconstructed signal.Source: §II · p. 2
- Timing skew acts as input phase modulation, while tracking-bandwidth mismatch changes each channel’s frequency response and produces gain and phase mismatches.These are the timing-error effects illustrated for the proposed AFT-based FI system.Source: §II · p. 3, Figure 4 · p. 3
A. Timing Skew
The AFT-based FI system attenuates timing-skew errors through a periodic sinc factor and is theoretically immune at input frequencies that are integer multiples of fs/N. Simulations show error-free operation at several such frequencies and a 5 dB worst-case improvement over TI.
A. Timing Skew
- The analysis assumes a single-tone input and channel skews with a periodic pattern of period N/fs.The channel input is sampled, transformed into frequency components, and reconstructed by an IDFT.Source: A. Timing Skew · p. 3
- The periodic sinc factor significantly attenuates skew-error power, yielding theoretical immunity when fin is an integer multiple of fs/N.The reconstructed output consists of an ideal term and a term representing timing-skew error.Source: A. Timing Skew · p. 3
- 5 dB worst-case improvement over an 8-channel TI ADC, with error-free operation at fin/fs = 1/8, 1/4, 3/8, and 1/2 under 2% timing skew.Both simulated ADCs use ideal 10b sub-ADCs.Source: A. Timing Skew · p. 3
B. Tracking Bandwidth Mismatch
The AFT-based FI system suppresses tracking bandwidth mismatch through the same periodic sinc attenuation factor that reduces skew errors. Behavioral simulations with a first-order RC mismatch model show a trend consistent with the skew analysis.
B. Tracking Bandwidth Mismatch
- Bandwidth mismatch is modeled as channel-dependent gain and phase mismatches, with the error analysis using a simplified first-order RC network.The channel input includes gain and phase changes attributed to bandwidth mismatch.Source: B. Tracking Bandwidth Mismatch · pp. 3–4
- The periodic sinc factor attenuates bandwidth-mismatch errors in the AFT-based FI system relative to its TI counterpart.This is the same attenuation factor identified for timing-skew errors.Source: B. Tracking Bandwidth Mismatch · p. 4
- Under a first-order RC bandwidth-mismatch model with σRC = 2%, simulated SNDR trends closely match those in the skew analysis.The simulations are for the 8-point AFT-based FI ADC and 8-channel TI ADC shown in Fig. 6.Source: B. Tracking Bandwidth Mismatch · p. 4, Figure 6 · p. 4
C. System Perspective
At fin = n·fs/N, the periodic sinc factor creates a notch in timing errors and theoretically makes the AFT-based FI architecture immune to them. Simulations at fin = 1/4fs show an advantage over TI as timing errors worsen.
C. System Perspective
- When fin = n·fs/N for integer n, the periodic sinc factor drops to zero, creating a notch that theoretically eliminates timing errors.The paper notes that this condition may not hold in blind ADC applications with arbitrary, unknown inputs.Source: C. System Perspective · p. 4
- At fin = 1/4fs, simulations show the AFT-based FI architecture has a prominent advantage over TI as skew and bandwidth mismatch worsen.Fig. 7 plots SNDR against skew and bandwidth mismatch at this input frequency.Source: C. System Perspective · p. 4, Figure 7 · p. 4
- The immunity can be leveraged in coherent sampling and OFDM, whose input or sub-carrier frequencies align with multiples of fs/N; it can eliminate power-hungry calibration in these settings.The paper contrasts these applications with blind ADCs, where the input is arbitrary and unknown a priori.Source: C. System Perspective · p. 4
III. CIRCUIT IMPLEMENTATION OF COMPLEX-VALUED IRRATIONAL COEFFICIENTS
The section addresses systematic errors that device-ratio implementations introduce for irrational AFT coefficients, proposing a lossless implementation for an 8-point AFT. It uses charge redistribution and describes an implementation that can extend to arbitrary AFT point sizes.
III. CIRCUIT IMPLEMENTATION OF COMPLEX-VALUED IRRATIONAL COEFFICIENTS
- Larger AFT point sizes provide greater timing-error robustness, but irrational coefficients make implementation more complex and ratio-based methods introduce systematic errors.The proposed solution is a lossless implementation of an 8-point AFT.Source: §III · p. 4
- Rational coefficients can be implemented with differential I/Q signaling as 90° or 180° phase shifts.For example, multiplying by j corresponds to a 90° shift, while multiplying by −1 corresponds to a 180° shift.Source: §III · p. 5
- The complex irrational coefficient Vi+[1] × D is implemented by rewiring to Vq+[0], with the same procedure applying to the remaining irrational coefficients.The coefficient matrix includes complex-valued irrational terms A, B, C, and D.Source: §III · pp. 4–5
- Equal-sized capacitors perform the AFT calculation through charge redistribution, avoiding device-ratio dependence and its systematic errors.The single-ended Y[7] example uses capacitors of size Cu.Source: §III · p. 5
- Because DFT twiddle factors correspond to complex exponentials on the unit circle, the proposed implementation generalizes to arbitrary AFT point sizes.The unit-circle illustration distinguishes rational and irrational complex-valued twiddle factors.Source: §III · p. 5, Figure 9 · p. 5
IV. DESIGN OF THE PROPOSED AFT-BASED FREQUENCY-INTERLEAVED ADC
The proposed 8-point AFT-based frequency-interleaved ADC embeds the AFT in a partially shared capacitor array and uses local clock generation in each channel.
IV. DESIGN OF THE PROPOSED AFT-BASED FREQUENCY-INTERLEAVED ADC
- The AFT calculation is embedded in the sub-ADC through a partially shared capacitor array.The architecture has eight frequency-interleaved sub-channels in each I/Q channel.Source: §IV · p. 5
- A symmetric Y-tree distributes input and clock signals to each channel, which generates its sampling clocks locally and simplifies global clock distribution.Source: §IV · p. 5
- Each I/Q channel consists of eight frequency-interleaved sub-channels.Source: §IV · p. 5
A. AFT-Embedded CDAC
The AFT is embedded in the 10-bit SAR ADC's CDAC, reusing capacitors for the transform and conversion. The design combines AFT redistribution with MSB conversion, while the sampling arrangement introduces an attenuation factor of 0.89.
A. AFT-Embedded CDAC
- The 10-bit SAR ADC embeds the AFT in its CDAC, with a unit capacitance Cu of 0.5 fF.The single-channel implementation is shown in Fig. 12.Source: A. AFT-Embedded CDAC · p. 5, Figure 12 · p. 6
- The first eight C1 capacitors are reused for the AFT and CDAC, and non-overlapping 76.8-ps clock pulses yield a sampling rate of 13 GS/s.The timing diagram is shown in Fig. 13.Source: A. AFT-Embedded CDAC · p. 6, Figure 13 · p. 6
- A monotonic switching scheme lets MSB conversion occur concurrently with AFT charge redistribution, saving conversion time and power.C2–C7 form a binary-scaled array, and C1 implements one redundant bit.Source: A. AFT-Embedded CDAC · p. 6
- An attenuation factor of 0.89 results because C2–C7 are unused during sampling; the paper considers it generally acceptable given the embedded AFT's area, speed, and power-efficiency advantages.Source: A. AFT-Embedded CDAC · p. 6
B. Input and Clock Distribution
The input and clock network is designed to preserve differential signaling and I/Q phase orthogonality through matched routing and controlled parasitics.
B. Input and Clock Distribution
- Maintaining differential signaling and I/Q phase orthogonality remains critical despite the architecture's reduced sensitivity to timing errors.A Y-tree distributes differential clock and input I/Q signals with routes placed side-by-side for matched lengths and parasitics.Source: B. Input and Clock Distribution · p. 7
- The Y-tree routes the I/Q and clock traces side-by-side to match lengths and associated parasitics.Source: B. Input and Clock Distribution · p. 7
- Swapping differential routes at detours creates a symmetric parasitic environment, while layout tuning can match cross-coupling capacitances and suppress their overall effect.The described layout has three differential signals, six traces, and twelve cross-coupling capacitors between adjacent traces.Source: B. Input and Clock Distribution · p. 7
V. MEASUREMENT RESULTS
The 10-bit, 13-GS/s FI ADC shows measured Nyquist performance with interleaving spurs buried under the noise floor. Its measured SNDR varies by less than 2 dB across the input-frequency range at 13 GS/s.
V. MEASUREMENT RESULTS
- Measured DNL was +1.2/-1 LSB and measured INL was +1.7/-1.5 LSB.Fig. 16 presents the static performance measurements at 10-bit, 13-GS/s operation.Source: Figure 16 · p. 7, §V · p. 7
- 26.4 mW consumption under a single 1 V supply yielded a Walden FoM of 12.7 fJ/conv.-step.The reported Schreier FoM was 159.7 dB; clocks consumed a large portion of total power because each AFT-embedded sub-ADC channel samples at all phases.Source: §V · pp. 7–8
- 45.8 dB SNDR and 56.1 dB SFDR were measured at Nyquist, with interleaving spurs buried under the noise floor.At a low-frequency input of 11.34 MHz, measured SNDR and SFDR were 47.1 dB and 56.9 dB, respectively.Source: §V · pp. 7–8, Figure 17 · p. 8
- Less than 2 dB variation in SNDR and SFDR was observed across the measured input-frequency range at 13 GS/s.The measured effective resolution bandwidth was 12 GHz; SNDR degraded 4.22 dB at 13 GS/s.Source: §V · p. 7, Figure 19 · p. 8, Figure 18 · p. 8
VI. CONCLUSION
The conclusion presents an 8-point charge-based AFT embedded in the sub-ADC CDAC as a timing-robust FI approach. Its 28-nm, 10-bit, 13-GS/s prototype achieves reported Nyquist performance and Walden FoM without timing-error calibration.
VI. CONCLUSION
- 45.8-dB SNDR, 56.1-dB SFDR at Nyquist, and 12.7 fJ/conv.-step Walden FoM were measured for the 10-bit, 13-GS/s prototype.The prototype was fabricated in 28-nm CMOS.Source: §VI · p. 9
- An 8-point charge-based AFT with lossless implementation of complex-valued irrational coefficients is embedded in the sub-ADC CDAC array.The conclusion describes this AFT-based FI architecture as inherently robust to timing errors and validated by a calibration-free prototype.Source: §VI · p. 9
- The paper presents this calibration-free FI ADC as its first prototype with performance competitive with state-of-the-art TI ADCs.The conclusion frames the prototype as a foundation for future high-speed ADC designs.Source: §VI · p. 9