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Probabilistic Algorithms for Ising Machines from Optimization to Generative AI
Corentin Delacour, Xiuqi Zhang, Abdelrahman S. Abdelrahman, Saleh Bunaiyan, Kyle Lee, Shuvro Chowdhury, Kerem Y. Camsari
TL;DR
Ising machines promise hardware acceleration for optimization and sampling, but many existing dynamics lack guarantees needed for controlled sampling. This Review surveys algorithm–hardware co-design approaches, including annealing, tempering, variational methods, and AI connections. It identifies instance-specific training as an open generality challenge for learned proposals.
Problem
Many physics-based Ising-machine dynamics lack detailed balance and convergence guarantees, limiting their use for tasks requiring controlled exploration, such as Bayesian inference and generative-model training.
Source: §1 · p. 3Method
The Review surveys probabilistic algorithms through a hardware-software co-design lens, covering principled sampling, optimization, and connections between Ising machines and generative AI.
Source: §1 · p. 3Results
The review describes co-design as bidirectional: algorithmic requirements shape hardware architectures, while dedicated probabilistic hardware has catalyzed algorithms such as PAOA.
Source: §1 · p. 3Takeaways & Limitations
The surveyed approaches connect learned global proposals for optimization with probabilistic primitives for AI inference, within the review's co-design framework.
Source: §1 · p. 3Most learned-proposal demonstrations train a separate model per instance, so extending transfer across Hamiltonians remains an open direction.
Source: §6.1 · p. 13
Abstract
from arXiv · showhide
Ising machines have emerged as promising hardware accelerators for intractable optimization and sampling problems, yet their practical impact increasingly hinges on the co-design of algorithms and hardware, where algorithmic demands shape new architectures and new hardware capabilities inspire entirely new algorithms. In this Review, we survey probabilistic algorithms designed for portability across diverse Ising platforms, advocating a top-down perspective that prioritizes principled methods with provable guarantees. We cover foundational methods such as simulated annealing and parallel tempering, including two-dimensional extensions that natively encode hard constraints, and examine approaches that expand the scale of solvable problems from cluster mean-field methods to variational samplers. We highlight the Probabilistic Approximate Optimization Algorithm (PAOA), a classical analog of QAOA that emerged directly from probabilistic hardware development, and explore how generative AI and Ising machines might reinforce each other: learned models propose global moves to accelerate optimization, while probabilistic techniques improve inference in large language models. Much as quantum computing has seen algorithms co-evolve with hardware, probabilistic and Ising computing stand at a similar inflection point. We outline a co-design framework for accelerating the capabilities and adoption of next-generation Ising machines.
1 Introduction
Ising machines encode optimization and sampling tasks as Ising problems, but many physics-based dynamics lack formal sampling guarantees. This Review takes a top-down co-design perspective, surveying principled probabilistic algorithms and how hardware constraints shape them.
1 Introduction
- The pairwise Ising formulation is NP-hard, while higher-order, multistate, and asymmetric variants broaden the problems these machines can represent.The extensions include PUBO, Potts-model, and directed graphical-model formulations.Source: §1 · p. 1
- Ising machines aim to exploit hardware parallelism and intrinsic dynamics to solve hard problems encoded in their computational models.The review describes physical and digital approaches, including coherent, photonic, oscillatory, memristor-based, CMOS, FPGA, and GPU implementations.Source: §1 · p. 2
- Many physics-based approaches lack detailed balance, formal convergence guarantees, and controlled sampling, limiting their use in inference and generative-model training.MCMC methods provide detailed balance and convergence to defined target distributions, supporting methods such as parallel tempering and variational sampling.Source: §1 · pp. 2–3
- Programmable Ising hardware can implement Gibbs or Metropolis updates, while p-bits with symmetric weights and biases directly implement Gibbs sampling.The review defines probabilistic computing by co-design around controlled, programmable randomness rather than any single device technology.Source: §1 · p. 3
- The Review surveys probabilistic algorithms across Ising accelerators and presents co-design as bidirectional: hardware needs shape architectures, while dedicated hardware has catalyzed PAOA.The authors compare this algorithm–hardware co-evolution with quantum computing.Source: §1 · p. 3
- The review progresses from annealing and parallel tempering through cluster mean-field and variational methods to generative-AI and Ising-machine synergies.The latter include learned global state updates for optimization and probabilistic primitives for AI inference.Source: §1 · p. 3
2 Annealing algorithms and their hardware realizations
Simulated annealing samples an energy-mapped system under a temperature schedule, shifting from broad exploration toward energy-minimizing moves as inverse temperature rises. Hardware must support this time-varying control, while related approaches differ in their dynamics and guarantees.
2 Annealing algorithms and their hardware realizations
- SA samples states from a Boltzmann distribution, with increasing inverse temperature shifting the search from global exploration toward local energy minimization.At high temperature the system explores broadly; as β rises under a cooling schedule, moves become more focused on minimizing energy.Source: §2 · pp. 3–4
- Digital SA may require multiplying synaptic inputs by β or reloading scaled weights, while analog designs can map β to a global physical variable.If temperature updates take longer than device sampling, the hardware can lose the speed advantage of intrinsic dynamics.Source: §2 · p. 4
- CIM, OIM, and simulated bifurcation modulate global controls to traverse continuous relaxations, but their relation to equilibrium sampling remains open.These physics-driven approaches can scale to 100,000 spins, yet ground-state search lacks MCMC-based annealing's theoretical convergence guarantees.Source: §2 · p. 4
- SQA uses coupled Trotter replicas and Gibbs updates to retain MCMC convergence guarantees while emulating quantum tunneling.Implementations reached 32 replicas and 32,768 total spins; its advantage over best-of-R SA is problem-dependent.Source: §2 · p. 4
- PAOA generalizes SA by variationally optimizing multiple schedules and recovers single-schedule SA as a special case.Its trajectories are out of equilibrium and optimized for a given problem class.Source: §2 · p. 4
3 Parallel Tempering for Ising machines
Parallel tempering uses replicas at fixed temperatures to exchange states, adding communication and energy-calculation costs that hardware implementations must justify. Two-dimensional parallel tempering also varies constraint penalties, enabling feasible states found under softer constraints to inform more constrained searches.
3 Parallel Tempering for Ising machines
- PT runs replicas at distinct fixed temperatures and swaps states so high-temperature exploration can help colder replicas escape local minima.Unlike SA's time-varying temperature, PT's swaps satisfy detailed balance, and replicas can map to separate Ising processors.Source: §3 · p. 5
3.1 Parallel tempering in hardware
- PT's hardware overhead includes global energy calculations and swap synchronization, so its advantage over independent SA runs should be demonstrated.Adaptive PT has outperformed conventional PT and R-SA on spin-glass benchmarks, though margins can be modest for weakly frustrated instances; frequent swaps can make communication a bottleneck.Source: §3.1 · p. 5
3.2 Enforcing constraints with 2D-Parallel Tempering
- Constrained optimization creates a penalty trade-off: weak penalties permit infeasible states, while strong penalties can trap search behind energy barriers.TSP encodings use N^2 spins for one-hot constraints, while outer-loop penalty tuning can interrupt sampling through machine reprogramming.Source: §3.2 · pp. 5–7
- 2D-PT adds a penalty-strength axis to the temperature ladder, letting lower-penalty columns discover feasible states that can move to higher-penalty replicas.The swap rule uses inverse temperature, penalty difference, and constraint-violation difference; adaptive scheduling addresses copy constraints without manual tuning.Source: §3.2 · p. 7
- 2D-PT reports orders-of-magnitude speedups over classical PT on Wishart graph-sparsification instances, 250× acceleration for 64-node Sherrington-Kirkpatrick spin glasses, and over 10× decoding speedup for 128-node MIMO problems.For TSP, fixing constraint temperature and tempering only the target energy reduces the method to a one-dimensional PT ladder with improved convergence on traveling-salesman instances.Source: §3.2 · p. 7
4 Scaling Ising Machines beyond single-chip limits
Cluster mean-field theory (CMFT) addresses problems larger than a single Ising-machine chip by partitioning the graph and updating clusters with hardware while approximating boundary interactions on a host processor. Its approximation can retain useful scaling, and two-cluster CMFT improves wall-clock residual-energy descent on a problem beyond single-FPGA capacity.
4 Scaling Ising Machines beyond single-chip limits
- CMFT partitions an oversized graph into hardware-sized clusters, updates one active cluster at a time, and uses host-computed mean-field biases for frozen boundary spins.Balanced partitions can be identified heuristically with minimum-cut algorithms; dynamic partitioning can reduce boundary errors.Source: §4 · p. 7
- κ=0.40 for two clusters is close to the exact-graph κ=0.43, while three clusters yield κ=0.29 and naive mean field is nearly flat at κ=0.02.These are log–log slopes of residual energy versus Monte Carlo sweeps for the 216-spin CPU results.Source: §4 · p. 7, Figure 2 · p. 8
- 10,648-spin two-cluster CMFT achieves steeper residual-energy descent over wall-clock time than an unpartitioned CPU solver on a problem beyond single-FPGA capacity.The figure reports residual energies comparable to the unpartitioned CPU baseline at shorter wall-clock times.Source: §4 · p. 8, Figure 2 · p. 8
- When inter-chip communication is slower than within-chip spin dynamics, distributed Ising machines implicitly approximate cluster mean field using boundary values that lag behind updates.The passage says a detailed analysis of CMFT convergence and its FPGA implementation will be presented elsewhere.Source: §4 · p. 8
- CMFT and neural-network accelerator partitioning share engineering challenges: balancing local work against communication while dividing large problems across devices.CMFT summarizes the external system through approximate mean fields at cluster boundaries.Source: §4 · pp. 8–9
5 Variational approaches for general Hamiltonians
Variational approaches complement fixed Monte Carlo update rules by optimizing parameterized stochastic processes, while neural quantum states use probabilistic hardware to accelerate sampling. Their reach is bounded by unresolved questions about reliable PAOA advantages and by the sign problem when amplitude cancellations matter.
5.1 Probabilistic approximate optimization algorithm
- PAOA optimizes a stochastic transition process, offering a classical probabilistic counterpart to QAOA for combinatorial optimization.The original proposal used classical probabilistic circuits built from low-dimensional stochastic matrices [60].Source: §5.1 · p. 9
- Simulated annealing is a restricted one-schedule case in a broader variational family, while richer parameterizations can learn non-equilibrium trajectories adapted to problem structure.Highly expressive ansatze may overfit individual instances, so generalization requires representative training families or lower-dimensional parameterizations.Source: §5.1 · pp. 9–10
- PAOA alternates hardware sampling with classical objective evaluation and parameter updates; FPGA-based p-computers have accelerated sampling for 3D spin-glass problems.Reproducible sampler nonidealities can in principle be incorporated into the optimized objective, and operating-point drift can be absorbed by retuning fields and couplings.Source: §5.1 · p. 10
- Reliable PAOA advantages remain an open question across restricted variational families, hardware substrates, and problem classes.Candidate dynamics include spatially varying schedules, learned local temperatures, adaptive fields, and continuous-spin rotations.Source: §5.1 · p. 10
5.2 Neural quantum states for quantum simulation
- Sparse neural quantum states mapped to FPGA probabilistic computers have enabled simulations of two-dimensional quantum systems with several thousand spins, with sampling effectively negligible relative to classical optimization.Local connectivity reduces routing complexity; conditional sampling supports more expressive architectures without sacrificing hardware compatibility.Source: §5.2 · pp. 10–11
5.3 Positive probabilities and the sign problem
- Probabilistic Ising machines naturally sample positive distributions, but reconstructing quantum amplitudes can require phase-weighted paths whose cancellations create a Monte Carlo sign problem [117].The sign problem is representation-dependent; no general efficient transformation is known to remove it for arbitrary non-stoquastic Hamiltonians or quantum circuits [118].Source: §5.3 · p. 11
6 Synergies with generative AI
Generative models and Ising machines can complement one another: learned global proposals aid Ising sampling and optimization, while probabilistic hardware primitives can support large-language-model inference. The section describes Transformer-augmented tempering and probabilistic attention as examples of this two-way synergy.
6.1 Augmenting Ising machines with learned proposals
- Other learned Ising-sampling approaches include spin relaxation and policy-gradient training, but these heuristics generally lack guarantees of reaching the true ground state.The methods described include relaxed-variable GNNs, learned MCMC proposals, autoregressive and diffusion models, PPO, and variational annealing.Source: §6.1 · p. 12
- IsingFormer proposes non-local states trained from equilibrium samples, while a Metropolis–Hastings step can preserve detailed balance for exact sampling.Learned exchange moves can reduce the need for dense intermediate temperature rungs in parallel tempering.Source: §6.1 · p. 12, Figure 4 · p. 12
- An inverse-temperature-conditioned IsingFormer accelerates ground-state searches on 3D spin glasses and integer factorization compared with vanilla PT.A single model trained on a fixed multiplier circuit transfers across a family of factorization instances without retraining and generalizes to unseen β values, including the critical region, for 2D Ising sampling.Source: §6.1 · p. 13
- Most demonstrations train a separate model per instance, leaving transfer beyond invertible-logic encodings an open question.The review identifies training over coupling distributions or conditioning proposals on a family-parameterizing master Hamiltonian as possible directions.Source: §6.1 · p. 13
6.2 Probabilistic attention for the KV-cache memory wall
- SANTA samples a small number of token indices from attention’s Boltzmann-like distribution and averages their value vectors, yielding an unbiased estimator.At 32k-token contexts, SANTA kernels achieve up to a 1.5× decode-step attention-kernel speedup over FlashInfer and FlashDecoding while matching baseline performance on reasoning and long-context benchmarks [135].Source: §6.2 · p. 13
- SANTA reduces value-row access without permanently discarding past tokens, complementing KV-cache compression, quantization, and grouped-query attention; p-bit experiments have demonstrated hardware softmax sampling.The proposed hardware connection is sampling from a Boltzmann-like distribution to reduce memory traffic in AI inference.Source: §6.2 · p. 13
7 Outlook
The outlook emphasizes top-down algorithm–hardware co-design: principled probabilistic methods provide a foundation for hardware-specific implementations, while hardware can motivate new algorithms. It presents hardware-enabled algorithms as an emerging opportunity and identifies the sign problem as a boundary for probabilistic Ising machines.
7 Outlook
- Bidirectional algorithm–hardware development is presented as the field’s defining opportunity, with the surveyed methods representing only part of a growing design space.Examples include cluster mean-field decompositions, neural quantum states, Transformer-augmented tempering, and stochastic sparse attention.Source: §7 · p. 13
- Top-down methods such as simulated annealing, parallel tempering, and cluster mean-field have understood convergence properties; co-design can add hard-constraint encoding and capacity scaling.Two-dimensional parallel tempering natively encodes hard constraints, while cluster mean-field decompositions use finite chip capacity as a feature.Source: §7 · p. 13
- Purely bottom-up approaches relying on intrinsic device dynamics may lack flexibility when problem structure changes.The review presents algorithms with provable guarantees as a foundation for layering hardware-specific optimizations.Source: §7 · p. 14
- Probabilistic hardware has motivated PAOA and stochastic attention, which repurpose native sampling and additive primitives for language-model inference.PAOA is described as a classical analog of QAOA made practical by non-equilibrium driving schedules; the review suggests scaling hardware may open further algorithmic possibilities.Source: §7 · p. 14
- Positive-probability sampling has a boundary: genuine quantum advantage ultimately requires controlled interference among signed or complex amplitudes.Source: §7 · p. 14