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PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron

Samira Mirbagher-Ajorpaz, Gilles Pokam, Esmaeil Mohammadian-Koruyeh, Elba Garza, Nael Abu-Ghazaleh, Daniel A. Jiménez

arXiv:2610.07691v1cs.CR

TL;DR

Software-based attack detection faces challenges in selecting discriminatory features, while PerSpectron uses replicated perceptrons and invariant microarchitectural features in hardware. The authors report competitive classification and describe the approach as a way to detect attacks in progress and support proactive countermeasures.

  • Problem

    Selecting strongly correlated, discriminatory features for hardware detection is challenging because attack signatures involve subtle interactions across processor pipeline stages.

    Source: §I · p. 3

  • Method

    PerSpectron uses replicated perceptron detectors with invariant features selected from a broad set of microarchitectural signals to detect attack footprints.

    Source: §I · p. 3, A. General Approach · p. 5, §IX · p. 13

  • Results

    PerSpectron maps a non-linearly separable problem to a linear one that perceptrons can separate, with results described as competitive with a more complex deep neural network.

    Source: §IX · p. 13

  • Takeaways & Limitations

    The approach is intended to detect attacks in progress so countermeasures can be deployed before an attack succeeds.

    Source: §I · p. 2

    RowHammer was not simulated because of simulator limitations.

    Source: C. Interpretation through feature… · p. 12

Abstract

from arXiv · show

Detecting microarchitectural attacks is critical given their proliferation in recent years. Many of these attacks exhibit intrinsic behaviors essential to the nature of their operation, such as creating contention or misspeculation. This study systematically investigates the microarchitectural footprints of hardware-based attacks and shows how they can be detected and classified using an efficient hardware predictor. We present a methodology to use correlated microarchitectural statistics to design a hardware-based neural predictor capable of detecting and classifying microarchitectural attacks before data is leaked. Once a potential attack is detected, it can be proactively mitigated by triggering appropriate countermeasures. Our hardware-based detector, PerSpectron, uses perceptron learning to identify and classify attacks. Perceptron-based prediction has been successfully used in branch prediction and other hardware-based applications. PerSpectron has minimal performance overhead. The statistics being monitored have similar overhead to already existing performance monitoring counters. Additionally, PerSpectron operates outside the processor's critical paths, offering security without added computation delay. Our system achieves a usable detection rate for detecting attacks such as SpectreV1, SpectreV2, SpectreRSB, Meltdown, breakingKSLR, Flush+Flush, Flush+Reload, Prime+Probe as well as cache-attack calibration programs. We also believe that the large number of diverse microarchitectural features offers both evasion resilience and interpretability---features not present in previous hardware security detectors. We detect these attacks early enough to avoid any data leakage, unlike previous work that triggers countermeasures only after data has been exposed.

I. INTRODUCTION

PerSpectron addresses gaps in software-based attack detection by moving detection into hardware, where it can monitor a richer feature space and identify attacks in progress. It combines correlated-feature selection with replicated perceptron detectors to detect and classify microarchitectural attacks, with the stated aim of enabling proactive countermeasures.

I. INTRODUCTION

  • Prior software detectors face limited counter capacity, multiplexing costs, attacker access to counters, and sampling intervals that attacks may evade.Recent Intel processors can monitor up to four events at a time.Source: §I · p. 2
  • The hardware detector monitors features beyond committed state, including speculative instructions, and is described as resistant to software disabling and sampling-interval timing.The authors state that hardware monitoring cannot be disabled by software even if the kernel is compromised.Source: §I · p. 3
  • PerSpectron selects 106 strongly correlated features from 1,159 simulator features for a hardware predictor that detects and classifies a range of attacks.The examined attacks include SpectreV1, SpectreRSB, Meltdown, breakingKSLR, Flush+Flush, Flush+Reload, Prime+Probe, and Calibration.Source: §I · p. 3
  • Replicated hardware perceptrons with overlapping low-level features aim to recognize complex attack patterns without the hidden layers used by software neural networks.The design targets rapid prediction and classification with high precision and recall.Source: §I · p. 3
  • The authors report low false-positive rates while identifying attacker evasion as a concern and positioning the detector as a first-line alert for operating-system responses.Subsequent responses may isolate a suspicious process or monitor it more closely.Source: §I · p. 3

II. BACKGROUND AND MOTIVATION

The background distinguishes cache side-channel attacks from speculative attacks and identifies the attacks used for training. It introduces the perceptron as a small, single-layer network suited to hardware implementation.

II. BACKGROUND AND MOTIVATION

  • The study categorizes cache side-channel attacks and speculative attacks, and limits its training set to six named attacks.The set comprises Prime+Probe, Flush+Reload, Flush+Flush, SpectreV1, Meltdown, and SpectreRSB; the authors note that it excludes other known attacks.Source: §II · p. 3
  • A perceptron is introduced as a small, single-layer learning network that is cheaply implementable in hardware.Source: §II · p. 3

A. Cache attacks

  • Prime+Probe infers victim cache use from evicted cache lines, while Flush+Reload uses shared pages and reload latency to infer victim access.Both are described as cache side-channel attacks.Source: A. Cache attacks · p. 4
  • Flush+Flush infers cache presence from flush-instruction timing without attacker memory accesses or cache misses.The passage notes that this stealth makes it undetectable by Cyclone’s cache-hit and cache-miss mechanisms.Source: A. Cache attacks · p. 4

B. Speculative attacks

  • SpectreV1 mis-trains branch prediction to access secret data speculatively, while Meltdown exploits delayed permission checks and SpectreRSB pollutes the return stack buffer.The attacks leak data through cache side channels or speculative control-flow effects.Source: B. Speculative attacks · p. 4

C. Perceptron

PerSpectron uses perceptron learning and replicated, overlapping features to detect attack signatures that shift across processor components. Its threat model centers on microarchitectural attacks, while its feature approach is intended to address variant-specific signatures and evasion.

C. Perceptron

  • A single-layer perceptron is proposed as a hardware-friendly alternative to deep multilayer networks, with weights correlating input vectors to attack or benign targets.Its weighted sum is thresholded, and weights are updated when the prediction differs from the desired outcome.Source: C. Perceptron · p. 4

III. THREAT MODEL

  • The defense targets cache-based and speculative attacks, including attacks on secure enclaves, while excluding traditional software vulnerabilities and physical side channels.The assumed attacker may have normal-user privileges; an enclave attack may involve operating-system privileges.Source: §III · pp. 4–5

A. General Approach

  • Attack information can shift between processor domains across variants, so PerSpectron uses replicated detectors to find similar signals at different input positions.The paper notes that different attacks can manifest through different branch-prediction, return-stack, or cache-related features.Source: A. General Approach · p. 5
  • Different attacks can produce distinct microarchitectural signals: Flush+Flush is associated with abnormal commitNonSpecStalls, while Flush+Reload is associated with abnormal PendingQuiesceStallCycles.The passage also describes an abnormal tol2bus.transdist.CleanEvict value for Prime+Probe.Source: A. General Approach · p. 5
  • Overlapping, redundant pipeline features capture relationships such as propagated fetch stalls, helping address domain hopping without explicitly representing feature relationships.The authors argue that timing-sensitive attack footprints make evasion difficult, though they also describe evasion resilience as an area for future work.Source: A. General Approach · p. 5

B. Feature selection

Feature selection groups correlated counters by pipeline component, then retains informative features across those components to build a bank of invariant features.

B. Feature selection

  • For each of 1,159 features, the procedure derives mutual information, uses Pearson correlations to form a matrix, and groups features whose absolute correlation exceeds 0.98 into 17 components.Source: B. Feature selection · p. 6
  • Within each component, the method discards redundant correlated features while retaining one from each group; discarding correlated features across components significantly reduces validation accuracy.Removing correlated features within a group caused no statistically significant validation-accuracy decrease.Source: B. Feature selection · p. 6
  • A greedy process ranks features by information about benign versus suspicious classes and selects one per pipeline component until accuracy gains are small or the feature limit is reached.This selection strategy enforces replication of invariant features.Source: B. Feature selection · p. 6

C. Hardware Design

PerSpectron encodes normalized microarchitectural statistics as binary features, trains a perceptron on the selected inputs, and computes predictions outside the processor’s critical path.

C. Hardware Design

  • Normalized counter values become k-sparse binary vectors, with each bit indicating whether a scaled statistic is below or above 0.5.The feature vector has k ones and zeros elsewhere; statistics are scaled by the maximum value for that counter at the execution point. The example represents distinct signatures using binary values.Source: C. Hardware Design · p. 6

D. Training and prediction

  • Offline training on 106 selected features produces 106 weights for the final hardware perceptron.The weights are used for prediction in the hardware design.Source: D. Training and prediction · p. 6

E. Computing the perceptron output

  • Because inputs are binary, the perceptron can add or subtract weights and use only the output sign to predict, without waiting for all output bits.The dot product adds the weight for an input of 1 and subtracts for an input of -1.Source: E. Computing the perceptron output · p. 6

F. Performance Overhead

  • Sampling and prediction run in hardware in parallel with execution, keeping inference off the processor’s critical path and yielding negligible performance impact.The dot product can be computed sequentially in about 100 cycles, with negligible area and energy and a result timely relative to the sampling interval.Source: F. Performance Overhead · pp. 6–7

C. Hardware Design

  • Table I ranks highly correlated features by class-label correlation and groups features from different pipeline components for replicated perceptron detectors.The displayed table is a subset of those features.Source: Table I · p. 7

G. Using PerSpectron within the System

PerSpectron supplies attack-suspicion information for system mitigations rather than process termination, and the evaluation uses gem5 traces of attacks and benign workloads.

G. Using PerSpectron within the System

  • Because low-level detection can produce false positives, PerSpectron is intended to inform further mitigations rather than terminate suspected processes.The paper discusses hardware and software mitigation classes.Source: G. Using PerSpectron within the System · p. 7
  • Replicated detectors can be reconfigured through secure weight updates, allowing classifiers for additional attacks when those attacks are included in training.The paper describes weights distributed in vendor patches and detectors replicated per pipeline component.Source: 1) Hardware Mitigations · p. 7, 2) Software Mitigations · p. 7
  • The system can pass pre-threshold perceptron output as confidence, enabling category-specific responses such as cache changes or branch-predictor noise and load fences.Increasing branch-predictor noise can slow an attack while reducing performance.Source: 1) Hardware Mitigations · p. 7

V. METHODOLOGY

  • The evaluation uses gem5 to simulate speculative and cache attacks, their calibration phases, and benign SPEC CPU 2006 applications.The benign suite includes applications spanning compression, scheduling, networking, AI, simulation, gene analysis, and search.Source: §V · pp. 7–8
  • Traces sample 1,159 microarchitectural counters every 10K, 50K, or 100K instructions, normalize statistics by counter maxima, and use randomized stratified three-fold validation.Perceptrons train for up to 1,000 epochs or until training error falls below 0.4; monitored statistics cover pipeline stalls, memory and latency events, branches, energy, and power states.Source: §V · p. 8

VI. SECURITY ANALYSIS

The analysis reports detection of trained attack classes and novel attacks, then tests resistance to polymorphic and bandwidth-reduction evasion strategies.

VI. SECURITY ANALYSIS

  • PerSpectron detected attack classes seen in training, resisted tested evasion attempts, and detected novel cache-based or speculative attacks, suggesting it recognizes underlying microarchitectural signatures.The authors describe this as an encouraging sign for detecting attacks not seen before training.Source: §VI · p. 8

A. Resilience to evasion

  • The authors argue that hiding attack features without interfering with the attack is difficult because those features strongly discriminate microarchitectural attacks.The section examines polymorphic changes to attack binaries and reduced attack bandwidth as evasion strategies.Source: A. Resilience to evasion · p. 8
  • Untrained polymorphic Spectre variants were flagged as suspicious at the same sampling interval despite changes to their code.The variants included changes such as moving the leak, altering index and bounds-check logic, and changing how the safety check is communicated.Source: 1) Polymorphic evasion · pp. 8–9, Figure 3 · p. 9
  • Even with SpectreV1 bandwidth reduced by 75%, 50%, or 25%, output stayed above cutoff after the first complete attack phase; below 25%, no data leaked within 2,000,000,000 instructions.The reduced-bandwidth variants were produced by injecting safe code before priming and after disclosure; the stated no-leak result applies to reductions below 25%.Source: 2) Bandwidth reduction evasion · p. 9, Figure 4 · p. 9
  • A 3 µs sampling interval yields 20 samples during the 61 µs run of essential attack tasks, contrasting with a prior 100 ms software-detector interval.The paper argues that sampling faster than the attack’s essential tasks makes sleep-based bandwidth evasion more difficult.Source: 2) Bandwidth reduction evasion · p. 9

B. Generalization to Other Attacks

PerSpectron was evaluated for generalization to attacks excluded from model development, including CacheOut, disclosed later, and held-out SpectreV2. The authors attribute this robustness to invariant features that capture attack signatures across variations and cache channels.

B. Generalization to Other Attacks

  • Cross-validation withheld test attacks from model selection, simulating detection on attacks absent from training and validation.The reported cross-validation confidence interval was (0.9979±0.0065).Source: B. Generalization to Other Attacks · p. 9
  • CacheOut, disclosed after development, was detected with 94% true-positive detection; held-out SpectreV2 was detected with 91% true-positive detection.CacheOut reads from the Line Fill Buffer, a feature PerSpectron had identified as invariant before CacheOut was disclosed.Source: B. Generalization to Other Attacks · p. 9
  • Using different cache channels across training and test sets, the authors found signatures that hold across attack variations, supported by detectors monitoring contention in CPU buffers and ports.PerSpectron does not rely on a cache channel for detection.Source: B. Generalization to Other Attacks · p. 10

C. Attack Coverage

PerSpectron detects a range of evaluated attacks before leakage, and the evaluation reports stronger accuracy than other tested models for the considered attacks. The authors also report that 10K-instruction sampling outperforms coarser intervals.

C. Attack Coverage

  • PerSpectron detected all evaluated attacks before leakage, with false negatives limited to initial and pre-leakage samples, including Prime+Probe and Flush+Flush.With PerSpectron features, a neural network detected 11 of 12 polymorphic attacks with fewer false positives.Source: C. Attack Coverage · p. 10

VII. EXPERIMENTAL EVALUATION

  • PerSpectron achieved substantially higher accuracy than other tested models for the attack types considered.The evaluation also examined individual feature behavior across the pipeline for interpretability and evidence relevant to generalizability and evasion resistance.Source: §VII · p. 10

A. Sampling granularity and threshold

B. Comparison with other models and feature sets

PerSpectron achieved the highest reported accuracy in model comparisons, while the feature analysis identifies interpretable signals across processor components. The evaluation uses binary classification because the limited number of attacks per category made multi-way cross-validation impractical.

B. Comparison with other models and feature sets

  • K-fold cross-validation excluded attack and benign samples from each test fold during training, with roughly balanced benign-program proportions; Table III describes excluding one attack version per category.The authors characterize standard K-fold cross-validation as an unbiased estimate of prediction error on future instances.Source: B. Comparison with other models and… · p. 10, Table III · p. 11
  • Limited attacks per category made multi-way cross-validation impractical, so this comparison reports binary-classification accuracy; CacheOut was excluded from all folds to stress-test advanced MDS detection.The authors report near-perfect multi-way F1 on the training set, but do not use that as the cross-validation result.Source: B. Comparison with other models and… · p. 10

C. Interpretation through feature analysis

  • Perceptron feature weights provide an interpretable attack footprint, and CommittedMaps was invariant across attack classes and enabled preleakage detection of register-file contention evasions.CommittedMaps holds speculative mappings from ISA registers to physical registers, supporting single-cycle pipeline recovery on flushes and exceptions.Source: C. Interpretation through feature… · p. 11
  • bytesReadWrQ was elevated across attacks early, while bytesPerActivate and wrPerTurnAround remained discriminatory for reduced-bandwidth attacks and reduced false positives.The authors relate elevated write-queue reads to attacks reading freshly evicted data while constructing a covert channel in a tight speculative window.Source: C. Interpretation through feature… · p. 11

B. Comparison with other models and feature sets

  • 99.7% accuracy was highest; PerSpectron-feature models reached 98.2% for neural networks, 90.5% for CART, 89.7% for logistic regression, and 94.8% mean accuracy for KNN (k=3).The authors note that KNN and deep neural networks have hardware overhead or classification latency that makes them unsuitable for hardware implementation.Source: B. Comparison with other models and… · p. 11, Table IV · p. 12

C. Interpretation through feature analysis

  • Including selfRefreshEnergy reduced false positives by 2% and improved resilience to polymorphic evasions; ReadCleanReq, WritebackClean, and readsharedreq detected Prime+Probe without increasing false positives.The L2-bus features capture cache evictions without focusing on whether flushes or cache priming caused them.Source: C. Interpretation through feature… · p. 12
  • Fetch-unit stall and trap features, decorrelated from one another but correlated with signals in other components, helped perceptrons classify orthogonal speculative techniques in a linearly separable space.The cited examples contrast speculative reads in Spectre with page-fault traps in Meltdown.Source: C. Interpretation through feature… · p. 12
  • The authors connect broad, interpretable feature coverage to generalization when attack signals appear in one or more monitored components, but did not simulate Rowhammer because of simulator limitations.Flush operations are essential to Rowhammer, so the authors describe the observation as promising rather than as a Rowhammer evaluation.Source: C. Interpretation through feature… · p. 12

VIII. RELATED WORK

Related detection work uses performance counters, malware-oriented classifiers, or other hardware strategies, but the paper argues that microarchitectural attacks require more detailed pipeline features. Its comparison highlights constraints in counter-based approaches and the distinction between committed-state malware signatures and processor-wide attack behavior.

A. Detection based solutions

  • Counter-based cache-attack detectors rely on unusual cache access patterns and can miss Flush+Flush, which does not access the cache.The authors also note that approaches using only a few simple counters may be easy to evade.Source: A. Detection based solutions · p. 12
  • FortuneTeller tested 36 counters but profiled with three—L1InstMiss, L1InstHit, and LLCMiss—and reported 24.88% overall performance degradation at a 10µs sampling rate.The cited processors were limited to three programmable counters.Source: A. Detection based solutions · p. 12
  • Malware detectors focus on committed instructions, whereas microarchitectural attack signatures can appear across processor-pipeline behavior and require a different feature space.The paper contrasts PerSpectron's detailed pipeline features with prior work using high-level cache-hit/miss or branch-misprediction features.Source: A. Detection based solutions · pp. 12–13
  • CC-Hunter detects contention patterns, ReplayConfusion tests sensitivity to cache configuration through replay, and GPUGuard applies decision-tree detection in the GPU context.The authors note that GPUGuard is limited to GPUs, where such attacks remain limited.Source: A. Detection based solutions · pp. 12–13

B. Other Defenses

The paper reviews cache and transient-execution defenses that partition, randomize, add noise, fence, or contain speculative effects. It contrasts those interventions with PerSpectron's detection-and-response approach and concludes that replicated detectors and invariant features support broad hardware coverage, while adversarial-ML robustness remains future work.

B. Other Defenses

  • Cache defenses include partitioning ways or security regions, randomizing address-to-set mappings, adding clock noise, and using LLC inclusion to prevent local-cache replacement of victim data.The reviewed approaches include NoMo, CATalyst, RPCache, CEASER, TimeWarp, FuzzyTime, and RIC.Source: 1) Defenses against Cache-based Side… · p. 13
  • Transient-execution defenses use serializing instructions or dynamic fencing for SpectreV1, IBRS or retpoline for Spectre-BTB and SpectreRSB, and hardware isolation or taint techniques to limit speculative leakage.The paper notes that IBRS instructions impose high overhead.Source: 2) Defenses against transient… · p. 13
  • PerSpectron detects attack footprints to enable rapid reaction, rather than rearchitecting the processor to interfere with attacks.The authors describe combining it with other defenses to activate them only when an attack is suspected.Source: 2) Defenses against transient… · p. 13

IX. CONCLUSION AND FUTURE WORK

  • PerSpectron combines replicated detectors and invariant feature selection over hardware features from processor ports, buffers, buses, and uncore.The conclusion presents this as a hardware mechanism for detecting a broad range of microarchitecture side-channel attacks.Source: §IX · p. 13
  • PerSpectron maps a non-linearly separable problem to a linear one for perceptron implementation, with results competitive with a more complex deep neural network.The authors say future coverage could expand through feature-set updates and perceptron-weight updates.Source: §IX · p. 13
  • The authors say many selected features are invariant and difficult to evade, but plan to evaluate and, if needed, improve security against adversarial machine-learning attacks.One proposed direction is randomizing the feature subset used over time.Source: §IX · p. 13
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