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Climbing the Design Ladder: Sequential Knowledge Distillation for Early-Stage Circuit Timing Prediction

Reza Moravej, Fahad Rahman Amik, Zhanguang Zhang, Didier Chételat, Yingxue Zhang

arXiv:2610.08457v1cs.LGcs.AR

TL;DR

Late discovery of timing violations can require costly iterations, while early-stage data is separated from post-routing timing by an abstraction gap. STEP-KD transfers knowledge sequentially through intermediate design stages to predict post-routing timing from post-synthesis data. It outperforms direct-distillation baselines across both reported datasets and, in most settings, the industry-standard STA tool.

  • Problem

    Post-routing timing is known only after routing, so predicting it accurately from post-synthesis data is challenging despite the cost of late-discovered violations.

    Source: §1 · pp. 1–2

  • Method

    STEP-KD trains stage-specific models from post-routing back to post-synthesis, sequentially distilling representations through intermediate design stages.

    Source: §1 · p. 2, §4.3 · p. 5

  • Results

    On both datasets, STEP-KD outperforms No KD and every Direct KD variant on every metric; it is on par with post-synthesis STA for OpenLLM-RTL WNS.

    Source: §6 · p. 6

  • Takeaways & Limitations

    STEP-KD may help engineers identify timing violations earlier in the design cycle and avoid expensive late-stage redesigns.

    Source: §7 · p. 9

Abstract

from arXiv · show

Integrated circuit design involves multiple design stages: logic synthesis, floorplanning, placement, and routing, with each stage taking hours to weeks to complete. Discovering timing violations late in this flow forces costly iterations back to earlier stages, wasting computational resources and delaying product launches. While predicting post-routing timing from early-stage data could prevent these failures, existing machine learning approaches struggle with the massive abstraction gap between post-synthesis logical descriptions and post-routing physical layouts. We propose STEP-KD (Sequential Timing Evaluation via Progressive Knowledge Distillation), which leverages intermediate design stages as ``stepping stones'' for progressive knowledge transfer rather than attempting direct prediction. STEP-KD trains teacher models at the post-routing, post-placement, and post-floorplan stages, then sequentially distills their knowledge to a post-synthesis student model through representation alignment. Experiments on diverse circuits demonstrate that STEP-KD reduces timing prediction error compared to direct distillation and supervised baselines, and in most settings compared to the industry-standard Static Timing Analysis (STA) tool. STEP-KD reduces the weighted mean absolute percentage error of Total Negative Slack prediction to 19.78\%, compared with 74.84\% for STA. Our proposed method is step forward to identify timing problems earlier, avoiding expensive late-stage redesigns.

1 Introduction

Late-stage timing violations force costly redesigns, motivating prediction of post-routing timing from earlier-stage data. STEP-KD transfers timing knowledge sequentially through intermediate design stages to address the abstraction gap.

1 Introduction

  • Accurate timing is known only after routing, while early-stage STA estimates are inaccurate because wire delays, simplified cell-delay models, and physical constraints are not yet available.Complex design stages can take hours to weeks, and discovering violations after routing may require discarding days of work and delay time-to-market by weeks or months.Source: §1 · pp. 1–2
  • STEP-KD uses post-floorplan and post-placement stages as sequential teachers to transfer timing knowledge from post-routing toward post-synthesis, rather than making one direct leap.The authors report that the intermediate stages provide progressively refined physical information and better representation alignment.Source: §1 · p. 2
  • The paper frames the central challenge as predicting late-stage timing quality accurately from early-stage design data.STEP-KD is intended to estimate post-routing TNS and WNS immediately after logic synthesis.Source: §1 · p. 2
  • The authors report that STEP-KD outperforms direct-distillation baselines and enables accurate post-routing timing prediction from post-synthesis data.They also describe a dataset of about 12k circuit implementations from 922 RTL designs, represented at four design stages with source RTL.Source: §1 · p. 2

2 Related Work

Prior circuit-timing predictors either operate at physical-design stages or estimate timing at RTL without incorporating the physical information added across layout stages. STEP-KD relates to privileged-knowledge distillation by transferring internal representations across stages with differing information.

2.1 Circuit Timing Prediction

  • Post-placement methods predict net delay, slew, arrival times, or slacks, but are not readily extendable to earlier design stages.The cited work includes Barboza et al. [2019] and Guo et al. [2022].Source: §2.1 · p. 2
  • RTL-stage timing approaches use Boolean-operator graphs or LLM-augmented GNNs, while layout-aware distillation and contrastive alignment also bypass physical-design stages and pre-mapping library timing information.The passage notes that library-specific cell delays, drive strengths, pin capacitances, and setup/hold arcs are unavailable before technology mapping.Source: §2.1 · p. 2

2.2 Privileged Knowledge Distillation in Machine Learning

  • Privileged knowledge distillation describes teacher–student distillation in which the teacher has access to more inputs than the student.The passage identifies this as the broader machine-learning framework related to the paper.Source: §2.2 · p. 3
  • STEP-KD aligns internal representations with graph neural networks and extends the teacher-assistant idea across multiple networks to bridge information gaps between design stages.Teacher Assistant Knowledge Distillation [Mirzadeh et al., 2020] instead focused on bridging model-capacity gaps.Source: §2.2 · p. 3

3 Background: Circuit Representation and Timing Analysis

The paper represents synchronous circuits as directed graphs and uses slack at sequential elements to characterize timing. It summarizes violations with TNS and WNS, which capture aggregate and most-critical timing, respectively.

3 Background: Circuit Representation and Timing Analysis

  • A circuit graph G = (V, E) has circuit elements as nodes and signal connections as edges; timing paths run between sequential elements through combinational logic.Each edge delay comprises driving-gate switching delay and wire delay, and slack is required arrival time minus actual arrival time.Source: §3 · p. 3
  • TNS quantifies the aggregate severity of timing violations, whereas WNS captures the single most critical one; either metric can be large while the other is small.A circuit may have many moderately failing paths or one severely failing path.Source: §3 · p. 3

4 Method: STEP-KD

STEP-KD trains stage-specific graph neural networks from post-routing back to post-synthesis, aligning representations across successive design stages. Only the post-synthesis model is retained for inference, where it predicts post-routing slack from synthesis-stage circuit data.

4 Method: STEP-KD

  • STEP-KD trains one model per design stage in reverse flow order, from post-routing through placement and floorplanning to post-synthesis, and retains only the post-synthesis model at inference.All models predict post-routing slack; each earlier-stage model is distilled from the trained later-stage models.Source: §4 · p. 3, §4.3 · p. 5

4.1 Features and Encoding

  • Each stage encodes circuit-graph features with a GCN, using timing, topology, technology, and stage-dependent spatial information to form node embeddings.Spatial coordinates are available from post-placement onward and set to (0, 0) at post-synthesis and post-floorplan.Source: §4.1 · p. 3

4.2 Multi-Granularity Representations and Projections

  • STEP-KD represents each stage at node, subgraph, and graph granularities, then uses cascaded learned projections to map representations one design step at a time into later-stage spaces.The granularities capture sequential elements, their local combinational logic, and global circuit properties; alignment is weighted across granularities.Source: §4.2 · p. 4

4.3 Training

  • Training proceeds PR, PP, PF, then PS, with each model aligned to all frozen later-stage teachers; the PR model is trained with supervision alone.The PS student receives knowledge from PF, PP, and PR, with the intermediate teachers themselves distilled from later stages.Source: §4.3 · p. 5

4.4 Inference

  • At inference, the post-synthesis model projects its representations through the PF, PP, and PR spaces, predicts node-level slack, and derives circuit timing metrics from those predictions.Only the post-synthesis model is used, providing an early estimate of post-routing timing information.Source: §4.4 · p. 5

5 Experiments

The experiments use a multi-stage dataset of circuit implementations, evaluate methods on unseen RTL designs, and compare sequential distillation with STA, supervised prediction, and direct-distillation variants.

5.1 Dataset Generation

  • The dataset contains 12.2k implementations from 922 RTL designs, represented at synthesis, floorplan, placement, and routing stages.Implementations were generated with OpenROAD and ASAP7 across 15 placement-density and core-utilization configurations; all circuits derived from one RTL design stay in the same split.Source: §5.1 · p. 5

5.2 Training and Evaluation Setup

  • Models are evaluated on 178 held-out designs across 20 sampled implementation runs, using MedAE, WMAPE, and RSE to capture different error sensitivities.Training proceeds from PR to PP to PF to PS, freezing each model before training the next.Source: §5.2 · p. 6

5.3 Baselines and Model Variants

  • The baselines include post-synthesis STA, supervised No KD, single-teacher Direct KD, and STEP-KD without sequentially distilled teachers.Direct KD tests one-step transfer from a single stage; the no-sequential-KD variant isolates the contribution of distilling the teachers themselves.Source: §5.3 · p. 6

6 Results

STEP-KD outperforms the supervised and direct-distillation variants across both datasets, while its comparative advantage varies with metric and circuit complexity. The results also examine outliers, sequential teacher distillation, representation granularity, and projection depth.

Main results

  • On both datasets, STEP-KD beats No KD and every Direct KD variant on every metric; it leads all three metrics for held-out designs and TNS WMAPE and RSE on OpenLLM-RTL.On OpenLLM-RTL WNS, STEP-KD is on par with post-synthesis STA.Source: §6 · p. 6, Table 1 · p. 7

Teacher models and sequential distillation

  • Sequentially distilling teachers improves the PS student's six metrics; without it, its TNS WMAPE and RSE exceed every Direct KD variant.The table compares STA, independently trained models, and ladder-distilled models at intermediate stages; the PR teacher uses post-routing slack as an input feature.Source: Table 2 · p. 7, §6 · p. 8

Robustness to outliers

  • Held-out WNS has high, run-variable RSE because neither method anticipates extreme critical-path changes; simpler OpenLLM-RTL circuits make post-synthesis STA more representative.STEP-KD nevertheless has lower TNS WMAPE and RSE on OpenLLM-RTL, where STA underestimates some large-TNS circuits.Source: §6 · p. 7, Figure 2 · p. 8

Impact of multi-granular distillation

  • Aligning all three granularities gives the lowest error on both datasets and every metric; graph-level alignment is the strongest single granularity.Subgraph-only alignment is weakest and can underperform No KD on held-out TNS, but helps when combined with the other granularities.Source: Figure 3 · p. 8, §6 · pp. 8–9

Effect of projection network depth

  • STEP-KD beats Direct KD at every tested projection depth on both datasets and every metric; even the 10-layer direct projection trails its 9-layer cascade.Increasing direct-projection depth does not reliably narrow the gap and can be unstable.Source: Figure 4 · p. 8, §6 · p. 9

7 Conclusion

STEP-KD uses post-floorplan and post-placement stages as sequential teachers to improve transfer from post-synthesis data to post-routing timing prediction. The appendix explains how timing paths, arrival times, and required times are computed.

7 Conclusion

  • Sequential post-floorplan and post-placement teachers enable more effective knowledge transfer than direct distillation, potentially helping engineers identify violations earlier and avoid late-stage redesigns.The conclusion presents this as a potential benefit of STEP-KD.Source: §7 · p. 9

A Circuit Timing Definitions

  • A timing path runs from a register or primary input to a register or primary output, and STA checks whether signals arrive within the clock period using stage-specific delays.Path delay sums gate and interconnect delays; slack is the difference between required and actual arrival time, with negative slack indicating a timing violation.Source: A Circuit Timing Definitions · p. 12

Actual Arrival Time (AAT)

  • Actual arrival time at a combinational node is the latest input arrival plus its edge delay, propagating forward through the circuit graph.At sequential elements, actual arrival time is initialized from clock arrival time plus clock-to-q delay.Source: Actual Arrival Time (AAT) · p. 12

Required Arrival Time (RAT)

  • Required arrival time is set from clock period and setup time at destination registers, then computed using the earliest required time across fanout paths at combinational nodes.Required arrival time propagates backward from registers through combinational logic.Source: Required Arrival Time (RAT) · p. 12

B.1 Dataset Statistics

Timing labels change most after floorplanning, while placement has little effect on STA labels. The appendix also describes benchmark exclusions and the features used to represent circuits.

B.1 Dataset Statistics

  • Timing labels change most after floorplanning, while placement does not significantly change STA-produced labels.The comparison is between labels from different design stages.Source: §B.1 · p. 13

B.2 OpenLLM-RTL Benchmark

  • Five OpenLLM-RTL circuits with very large, identical post-routing and post-synthesis TNS and WNS were excluded because they would dominate WMAPE and RSE and mask method differences.Post-synthesis STA is exact on these circuits.Source: §B.2 · p. 13

B.3 Data Feature Details

  • Circuit features include normalized placement coordinates, stage-STA slack, and 61 topological and functional features.Coordinates are zeroed for post-synthesis and post-floorplan stages; placement and routing coordinates are normalized per circuit.Source: §B.3 · p. 13

C Input Encoding and Slack Bias

The post-synthesis model combines graph-derived node features with a learned representation of current-stage slack, which is passed directly to the timing predictor. Removing the slack embedding sharply worsens TNS prediction.

C Input Encoding and Slack Bias

  • Each node’s spatial, timing, topological, and technology feature vectors pass through separate linear layers, whose outputs are concatenated as its input feature.Source: C Input Encoding and Slack Bias · p. 13
  • A learned projection of each sequential element’s current-stage STA slack is added to its node representation before pooling and prediction.The projected slack acts as a latent bias that passes slack information directly to the timing predictor and improves accuracy and training stability.Source: C Input Encoding and Slack Bias · p. 13
  • Without the slack embedding, TNS WMAPE rises from 24.05% to 78.78%, while WNS RSE exceeds 100%.The full model sums the slack embedding and GNN node representation; using the slack embedding alone comes close to the full model.Source: C Input Encoding and Slack Bias · p. 14

D Comparison with Prior Timing Prediction Methods

The comparison distinguishes STEP-KD from prior timing-prediction methods by their input stage, prediction target, and training paradigm. These differences are summarized in Table 4.

D Comparison with Prior Timing Prediction Methods

E Complete Scatter Plots

The scatter plots show that intermediate-stage STA can substantially underestimate post-routing timing, particularly for high-WNS circuits. STEP-KD uses implementation parameters in its predictions, and later-stage distillation makes that use more precise.

E Complete Scatter Plots

  • For high-WNS circuits, earlier-stage estimates remain below post-routing WNS: about 700 at PF and PP versus about 950 to 1,820 after routing.Post-routing WNS also differs considerably across implementations sharing the same PF and PP estimate.Source: Figure 7 · p. 15, E Complete Scatter Plots · p. 15

F Complete Ablation Results

  • Table 6 reports complete held-out results for the multi-granularity ablation, comparing alignment at individual representation granularities with full STEP-KD.The full STEP-KD variant is labeled “All.”Source: Table 6 · p. 16, F Complete Ablation Results · p. 16

E Complete Scatter Plots

  • Distillation from later stages makes implementation-parameter use more precise; the No KD baseline shows much wider prediction spread despite receiving the same input features.Post-synthesis STA does not use implementation parameters and therefore predicts the same value for each implementation of a design.Source: E Complete Scatter Plots · pp. 15–16, Figure 8 · p. 15

G Results on OpenLLM-RTL

The OpenLLM-RTL results are organized across stage comparisons and ablations. The supplied table descriptions specify the comparisons but do not provide outcome values.

G Results on OpenLLM-RTL

  • Table 1 and Figures 3 and 4 report the OpenLLM-RTL main results.Source: G Results on OpenLLM-RTL · p. 16
  • Table 8 compares STA, models without later-stage distillation, and models distilled along the design ladder at each intermediate stage.Its post-routing teacher receives post-routing slack as an input, so its near-perfect score is expected and included for completeness.Source: Table 8 · p. 17
  • Table 9 compares single-granularity alignment variants with full STEP-KD, using the same PF, PP, and PR teachers.Source: Table 9 · p. 17
  • Table 10 reports the projection-depth ablation for Direct KD from the PR teacher and includes STEP-KD for reference.The default Direct KD uses 3-layer projections; STEP-KD composes three 3-layer projections.Source: Table 10 · p. 17

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