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X-OPM: Explainable Automatic Digital On-Chip Power Modeling for Enhanced Robustness

Jingbo Jiang, Xizi Chen, Jian Peng, Wei Zhang

arXiv:2610.08502v1cs.ARcs.AIcs.LG

TL;DR

Existing OPM approaches give limited attention to how selected features relate physically to power, despite the need for robustness on unseen workloads. X-OPM applies RTL-informed feature engineering with tree-based interaction construction and linear prediction; on C906 it maintained R2 > 0.93 across workloads with sampling windows below 8 cycles.

  • Problem

    Existing OPM methods span linear, tree, and MLP models, but discussions of how trained signals correlate with power remain scarce and robustness on unseen workloads is a concern.

    Source: §I · p. 1, §II · p. 2

  • Method

    X-OPM derives explainable features from RTL design knowledge and uses tree models to construct feature interactions before linear prediction.

    Source: §I · pp. 1–2

  • Results

    R2 > 0.93 across every C906 test workload below 8-cycle sampling windows, while APOLLO, COBIT, and MLP failed to maintain test accuracy on a different test set.

    Source: §I · p. 2

  • Takeaways & Limitations

    The conclusion reports a C906 test R2 of 0.955 on unseen benchmarks, versus 0.886–0.916 for raw-signal baselines, with deployed predictor area below 0.1% of the core.

    Source: §VII · pp. 10–11

Abstract

from arXiv · show

Proactive power management systems reduce processor dynamic power through runtime power prediction and power-aware scheduling. Accurate, stable and low-overhead digital on-chip power meters (OPMs) are crucial for improving the prediction quality. Recent studies have explored various modeling methods, including using linear models, decision trees, and multi-layer perceptrons (MLPs) to construct OPMs. However, most current approaches train models end-to-end without analyzing the physical interpretability of features, affecting their ability to generalize to unseen workloads. Grounded in the design principles of synchronous digital VLSI circuits, X-OPM introduces a robust feature engineering framework that uses tree-based models to capture feature interactions and linear models for prediction. It also incorporates a human-in-the-loop workflow to balance model accuracy against modeling effort. Evaluated on a commercial C906 vector processor, X-OPM consistently achieves $R^2 > 0.93$ across all workloads with sampling window size set below $8$ cycles. In contrast, state-of-the-art methods including APOLLO, COBIT, and standard MLPs fail to generalize across all test cases. Layout with commercial EDA tools shows that X-OPM incurs an area overhead below $0.1\%$, which is on par with lightweight tree-based and linear models, and significantly smaller than MLP-based models.

I. INTRODUCTION

Proactive power management depends on on-chip power meters that predict runtime power, but existing modeling approaches give limited attention to robustness on unseen workloads. X-OPM uses RTL-informed feature engineering and a hybrid tree-and-linear model, reporting strong C906 results with low area overhead.

I. INTRODUCTION

  • Proactive power management predicts dynamic-power fluctuations so runtime scheduling can mitigate imminent power events, including through instruction throttling or adaptive clock gating.Excessive processor power is associated with supply-voltage fluctuations, overcurrent, and overheating-related frequency drops.Source: §I · p. 1
  • Existing OPM work spans linear models, trees, and MLPs, but robustness on unseen workloads receives limited attention and is defined as test-workload R2 relative to training-set R2.Small pre-tape-out training sets and permanently hardened on-chip proxies make overfitting a practical concern.Source: §I · p. 1
  • X-OPM incorporates RTL design knowledge through white-box feature engineering and pairs tree-based interaction construction with linear prediction in an automated modeling framework.Its signals are categorized and processed, then iteratively added or removed so proxy-power relationships are explainable.Source: §I · pp. 1–2
  • R2 > 0.93 on every test workload below 8-cycle sampling windows; APOLLO, COBIT, and MLP fail to maintain test accuracy on a different test set, while area overhead is under 0.1%.The reported area overhead is on par with linear and tree models and far below the MLP model.Source: §I · p. 2

II. BACKGROUND AND RELATED WORKS

  • On-chip power models trade accuracy against implementation overhead, whereas the paper’s methodology is scoped to on-chip rather than off-chip architectural-design models.The background describes complex models such as deep neural networks as choices for off-chip modeling.Source: §II · p. 2
  • Prior feature-selection and tree flows can select signals or conjunctions without verifying that their relationship to power reflects real hardware gating, making them brittle under limited workload coverage.The paper proposes deriving structural proxy requirements from synchronous-circuit low-power design rules.Source: §II · p. 2

III. X-OPM METHODOLOGY

X-OPM derives its modeling approach from synchronous RTL design and the sources of dynamic power. It classifies signals by their circuit roles and uses those categories to build a white-box modeling pipeline.

III. X-OPM METHODOLOGY

  • Synchronous RTL designs provide the basis for deriving a white-box model of dynamic power in generalized pipelined designs.The section first analyzes a representative synchronous circuit and then generalizes its modeling approach.Source: §III · p. 2

A. Dynamic Power in Synchronous Circuit

  • Control signals enable pipeline-register data flow, configuration signals select logic modes, and data signals carry numerical values to be processed.In the example circuit, handshake signals gate register clocks, while mask gates data from the multiplier to the adder.Source: A. Dynamic Power in Synchronous Circuit · p. 3
  • X-OPM selects signals that map clearly to its signal categories, discards the rest, and feeds the processed signals into feature selection, interaction, and regression.RTL designers may provide signal lists or naming conventions such as *_stall and *_busy to support identification.Source: A. Dynamic Power in Synchronous Circuit · p. 3

B. Signal Post-processing and Feature Interaction

X-OPM processes control, configuration, and data signals differently to make their relationships to power more suitable for modeling. Binning can reduce signal width, with an accuracy trade-off.

B. Signal Post-processing and Feature Interaction

  • Control signals are transformed to correlate positively with power, while configuration values are one-hot encoded so their coefficients represent average power by operating mode.Data signals are transformed into the bitwise Hamming distance between consecutive cycles.Source: B. Signal Post-processing and Feature… · p. 3
  • Hamming distance counts bit toggles per cycle and therefore correlates positively with dynamic power consumption.It is computed using bitwise XOR followed by a popcount.Source: B. Signal Post-processing and Feature… · p. 3
  • Binning collapses signals with similar power magnitudes into fewer bits, reducing implementation width at the cost of model accuracy.For eight operating modes, the example replaces eight one-hot features and coefficients with four bin bits and one coefficient, forcing mode power into an arithmetic progression.Source: B. Signal Post-processing and Feature… · p. 3

12 // multiplicative interaction: control x data

The described interactions represent joint signal conditions that influence dynamic power. The examples distinguish multiplicative interactions from configuration-selected data paths.

24 // power model -- decision-tree style

  • A 4096-bit data signal can be divided into HD < 2048 and HD ≥ 2048 bins, reducing a 13-bit feature to 2 bits.Source: §24 · p. 4

18 // power model -- linear-model style

  • A clock-gated module’s mode and data sequence can jointly determine power, motivating multiplicative feature interaction.Source: §24 · p. 4

24 // power model -- decision-tree style

  • A configuration signal can selectively choose between data A and data B, defining a distinct interaction pattern.Source: §24 · p. 4

C. Modeling the Single-stage Module

The section shows how single-stage modules can be modeled with linear or tree forms after constructing feature interactions. Because the forms can be equivalent, the authors use a regularized linear model by default.

C. Modeling the Single-stage Module

  • The example synthesizable pseudo-Verilog model uses manually constructed feature interactions and coefficients fitted to Module A’s simulated power trace.Source: C. Modeling the Single-stage Module · p. 4
  • The tree form partitions interacted proxies into regions and selects the coefficient for the activated partition.Each region corresponds to a tree leaf, selected by an indicator function.Source: C. Modeling the Single-stage Module · p. 4
  • The linear and tree forms describe the same model when control and configuration signals separate operational modes, so either can model a single-stage module.Mutually exclusive mode indicators partition proxy space like tree leaves; the linear form is the default because it appears more robust to noise and outliers than bagged trees.Source: C. Modeling the Single-stage Module · p. 4

D. Modeling a Complete Design

A generalized additive model represents complete pipelined designs through module or function power signatures. The authors also propose reusing functional tests for training while reserving benchmark cases for testing.

D. Modeling a Complete Design

  • A GAM models a complete design by summing power signatures of module proxies, with an intercept for workload-independent power.The conditional expectation and link function relate proxy toggles to expected power.Source: D. Modeling a Complete Design · pp. 4–5
  • Pipelined designs are additive because successive combinational modules produce power responses to data arriving at their input registers in different cycles.The two-register example illustrates how activity in separate pipeline stages contributes to total dynamic power.Source: D. Modeling a Complete Design · p. 5
  • GAMs can model designs module by module or function by function; function-based proxies can be more hardware-efficient for repetitive structures such as Tensor Cores.In the function-based style, a proxy can represent an instruction’s power signature.Source: D. Modeling a Complete Design · p. 5

E. Construct Train and Test Dataset

  • The ideal training set has one sample per orthogonal feature, each with exactly one non-zero feature, allowing deterministic coefficient fitting.In practice, interacted features are not perfectly orthogonal, and manually crafting tests for every proxy in a billion-transistor SoC is intractable.Source: E. Construct Train and Test Dataset · p. 5
  • Reuse direct and random functional tests for training and benchmark tests for testing, supplementing random cases if training fails to converge.The split de-correlates training and testing distributions; training should span leakage-to-maximum power and toggle every proxy at least once.Source: E. Construct Train and Test Dataset · p. 5

IV. AUTOMATIC MODEL BUILDING PROCEDURE

The automatic procedure uses tree models to learn feature interactions while checking them against white-box principles. It combines this approach with feature screening and a human-in-the-loop workflow to reduce manual effort while retaining interpretable features.

IV. AUTOMATIC MODEL BUILDING PROCEDURE

  • Manual feature interaction is prohibitively labor-intensive for complex RTL, motivating automation that keeps learned feature meanings similar to the white-box approach.Source: §IV · p. 5

A. Characteristic of the Power Modeling Problem

  • Step-like, collinear power relationships, sparse strong features, and small training sets motivate feature engineering and robust model backends.Trees suit conditional, step-like mappings, while polynomial models suit smooth relationships with a few strong features.Source: A. Characteristic of the Power… · p. 6
  • A decision tree learns feature interactions from human-screened raw features, and a separate procedure checks those interactions against white-box principles.After interaction learning, the flow uses linear or tree models for single-stage modules and GAMs for complete designs.Source: A. Characteristic of the Power… · p. 6

B. Feature Selection

  • Prior work’s signal supersets can be orders of magnitude larger than the power-correlated subset, making rapid screening useful.An edge processor may contain over 10^6 RTL signals, while a few hundred can suffice for model fitting.Source: B. Feature Selection · p. 6
  • The feature-selection stage first removes zero-variance signals, then runs five algorithms in parallel and selects the one with the highest validation R^2.Hyperparameter optimization tunes each algorithm, while a timeout discards algorithms that do not converge in reasonable time.Source: B. Feature Selection · p. 6

C. Feature Interaction and Model Regression

The method uses a tree model to propose feature interactions, then applies human review and a linear regression model to fit power. Tree paths provide candidate interactions, while ElasticNet regularization addresses sparsity and collinearity.

C. Feature Interaction and Model Regression

  • Unlike COBIT, the tree model proposes possible interacted features rather than serving as the final predictive model.Source: C. Feature Interaction and Model… · pp. 6–7
  • The fitting flow processes signals, uses a deep GBDT to construct and rank interactions, then manually selects semantically valid features for linear fitting.Depth-one features are removed, and processed control signals are included in the linear model.Source: C. Feature Interaction and Model… · p. 7
  • The GBDT approximates power as an additive ensemble of regression trees fitted stagewise to squared-loss residuals.Each new tree targets the residual between the observed power and the current ensemble prediction.Source: C. Feature Interaction and Model… · p. 7
  • Each root-to-leaf path defines a candidate interacted feature whose depth is its number of split conditions and whose importance sums split loss reductions.A path gates a proxy’s power contribution through a conjunction of signals.Source: C. Feature Interaction and Model… · p. 7
  • ElasticNet combines L1 and L2 penalties to encourage sparse coefficients while stabilizing highly correlated proxy groups.The L1 penalty removes weak or physically meaningless coefficients; L2 reduces arbitrary coefficient splitting among correlated proxies.Source: C. Feature Interaction and Model… · p. 7

D. Training Skills

X-OPM’s training flow combines regression choices grounded in power behavior with automated tuning and designer review. It also handles rare high-power cases and recursively decomposes blocks that miss validation targets.

D. Training Skills

  • Weighted least squares prioritizes maximum-power vectors, emphasizing high-di/dt transients at the cost of low-power idle accuracy.Non-negative weights are aggressively scaled to focus prediction on critical anomalies.Source: D. Training Skills · p. 7
  • ElasticNet fixes its intercept to static leakage power and constrains coefficients to be non-negative.These constraints make zero-valued proxies predict baseline leakage and prevent negative modeled dynamic power.Source: D. Training Skills · p. 7
  • Bayesian optimization with TPE tunes GBDT and ElasticNet hyperparameters against validation R2 within temporal bounds.TPE also implements early stopping.Source: D. Training Skills · p. 7
  • ADASYN synthetically oversamples rare high-power edge cases before regression to address dataset imbalance.High-power vectors are scarce in standard testbenches, so ordinary least squares tends to favor idle and low-power states.Source: D. Training Skills · p. 7
  • When a top-level model misses its baseline R2 target, the flow descends into submodules and reruns the pipeline, with designers able to add or remove proxies.Submodules contributing less than 5% of parent power are skipped, with their footprint absorbed into the parent’s linear intercept.Source: D. Training Skills · pp. 7–8

A. OPM Hardware Design

The OPM predictor hardens processed proxies and a linear model into a time-multiplexed arithmetic datapath. Its area grows mainly with retained proxy count, while the time window has a smaller modeled effect.

A. OPM Hardware Design

  • The predictor evaluates hardened proxies with a coefficient-buffer MAC path, then adds bias, shifts for quantization and averaging, and rounds the result.Trained coefficients are quantized to 8-bit unsigned integers, and the predictor can be fully pipelined at core frequency.Source: A. OPM Hardware Design · p. 8
  • Register-file coefficients allow the OPM to be retrained with post-silicon data after tape-out.RFE removes the least-contributing proxy iteratively and refits ElasticNet, choosing the smallest proxy count that does not harm R2.Source: A. OPM Hardware Design · p. 8
  • Time-multiplexing uses K multipliers rather than N, steering each proxy set through a multiplexer and coefficient buffer across ⌈N/K⌉ cycles.The averaging window T is chosen as a power of two so averaging can use a right shift.Source: A. OPM Hardware Design · p. 8

B. Hardware Overhead Analysis

  • Modeled area scales as O(N log T), making proxy count N the more effective hardware-overhead lever.The passage states that increasing T adds at most T cycles of latency.Source: B. Hardware Overhead Analysis · pp. 8–9
  • At T = 8, reducing proxies from N = 372 to N = 30 cuts modeled area from 10.7k to 872 units, about 12.3×.At N = 30, modeled area is 850, 872, and 907 units for T = 4, 8, and 16, a 6.7% spread across a 4× range.Source: B. Hardware Overhead Analysis · p. 9

VI. EXPERIMENTS

The evaluation uses post-layout, cycle-resolution power labels from a TSMC 28 nm C906 implementation. On core-level x_aq_core power, X-OPM’s processed features outperform raw-signal baselines and show a smaller validation-to-test drop.

A. Experiment Setup

  • The evaluation uses cycle-resolution post-layout power simulation of the C906 synthesized and laid out in TSMC 28 nm HPC+.Power data were extracted at one-cycle resolution using Synopsys PrimePower 2025.Source: A. Experiment Setup · p. 9

B. Modeling Result of C906

  • The core-level x_aq_core power breakdown uses CoreMark, while x_aq_lsu_top and x_aq_vpu_top are modeled at submodule level for accuracy.Submodules contributing less than 5% of their parent module’s power are skipped.Source: B. Modeling Result of C906 · p. 9
  • Test R2 is 0.955 for X-OPM versus 0.916 for Ridge, 0.908 for MLP, and 0.886 for GBDT on x_aq_core.The figure compares four baselines trained on raw single-bit features with X-OPM’s processed features.Source: B. Modeling Result of C906 · p. 9
  • Replacing only raw features with processed features raises GBDT+Ridge test R2 from 0.908 to 0.955; X-OPM’s validation-to-test drop is 0.021 versus 0.025–0.058 for baselines.The remaining X-OPM error concentrates at high power, where predictions saturate near 100 mW.Source: B. Modeling Result of C906 · p. 9

C. Hardware Overhead Evaluation

Pruning reduces the implemented model’s proxy count, while the discussion links peak-power error to rare training examples and least-squares behavior. The conclusion reports strong unseen-benchmark results against raw-signal baselines.

C. Hardware Overhead Evaluation

  • With RFE, accuracy stays near pooled test R2 0.89 down to about 30 proxies, then falls to 0.83 at N = 10 and 0.79 at N = 5.At N = 1, pooled R2 is 0.28 and CoreMark is −0.47; the deployed model uses 30 proxies.Source: C. Hardware Overhead Evaluation · p. 9
  • After layout, the pruned predictor occupies 5307 µm2, or 0.61% of the 0.87 mm2 C906 core.Source: C. Hardware Overhead Evaluation · p. 9

D. Discussion about the Modeling Results

  • Peak-power cycles are rare because dense instruction mixes, wide datapath toggling, and ungated deep paths must coincide; such stress vectors are also costly to simulate.The resulting training set is dominated by average-power cycles.Source: D. Discussion about the Modeling Results · p. 10
  • Least-squares fitting favors average cases; data-gating coefficients depend on few peak samples, while clock-gating coefficients are better estimated across workloads.The paper identifies saturation near 100 mW as the visible result.Source: D. Discussion about the Modeling Results · p. 10
  • High-capacity models can fit training benchmarks without learning circuit structure that transfers, while RTL-derived gating features with regularized linear fitting generalize better.The paper also recommends reserving fine-grained configuration and data signals for large, variable-power submodules.Source: D. Discussion about the Modeling Results · p. 10

VII. CONCLUSION

  • Test R2 reaches 0.955 on unseen benchmarks, versus 0.886–0.916 for raw-signal baselines; the conclusion reports layout area below 0.1% of core area.The conclusion describes X-OPM as an explainable automated methodology using tree models for feature interactions and regularized linear regression.Source: §VII · pp. 10–11
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