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Physical Design Automation for Planar Superconducting Quantum Chips

Michael Feldmeier, Marcel Walter, Gerhard B. P. Huber, Anirban Bhattacharjee, Stefan Filipp, Robert Wille

arXiv:2610.08580v1quant-phcs.ET

TL;DR

Manual SCQC layout takes days or weeks, and existing automated approaches simplify the problem and relax physical constraints. The paper formalizes device physics geometrically and introduces an automated design flow. It reports complete, design-rule-compliant layouts and up to 25× faster solving on a comparable instance.

  • Problem

    Manual chip layout takes days or weeks of expert effort, while existing automation relaxes physical constraints and falls short of fabrication-ready results.

    Source: §I · p. 1, §V · p. 13

  • Method

    The paper translates device physics into a geometric abstraction and builds an automated design flow on that formulation.

    Source: §I · p. 1, §V · p. 13

  • Results

    25× faster than Yang et al. on the comparable 33Q instance; the flow also generates fully routed layouts for up to 69 qubits while adhering to physical design rules.

    Source: C. Discussion · p. 13

  • Takeaways & Limitations

    The flow automates chip designs at scales where manual layout drafting becomes impractical, producing design-rule-compliant layouts in seconds to minutes.

    Source: C. Discussion · p. 13, §V · p. 13

    The flow does not provide universal theoretical guarantees of completeness for every conceivable edge case, though it resolves all evaluated instances.

    Source: C. Discussion · p. 13

Abstract

from arXiv · show

Superconducting circuits have emerged as one of the most promising and scalable platforms for quantum com- puting, with substantial industrial adoption driving qubit counts steadily upward. Yet the layout of the corresponding chips is still primarily performed manually, consuming multiple days or weeks of expert effort, even for moderately sized designs. Existing automation approaches sidestep this bottleneck by simplifying the underlying problem and relaxing physical constraints. Therefore, they fall short of fabrication-ready results. To overcome this scalability wall without such compromises, we first introduce a formal abstraction that translates physical device characteristics into a rigorous geometric problem formulation. This abstraction bridges physical realization and design automation. Building upon this abstraction, we then propose a three-stage design automation flow comprising geometry-aware global partitioning, ILP-based port assignment, and a hierarchical routing pipeline. Evaluations conducted by our interdisciplinary team of design au- tomation researchers and superconducting hardware experts con- firm that the resulting flow produces complete, manufacturing- ready layouts that comply with the physical design rules at the push of a button. That is, it operates fully automatically within seconds to a few minutes, and solves complex instances up to 25x faster than the state of the art. All methods are released as the fully open-source tool mqt-scpd as part of the Munich Quantum Toolkit, providing the first readily usable, end- to-end design flow for planar superconducting quantum chips that explicitly addresses the underlying physical characteristics and requirements.

I. INTRODUCTION

The paper addresses the lack of automation for physically faithful layouts of irregular superconducting quantum chips, which leaves teams reliant on time-consuming manual design. It formalizes chip physics geometrically and builds an automated flow on that abstraction.

I. INTRODUCTION

  • Manual layout, validation, and simulation take multiple people days to weeks even for 20–30-qubit designs, and architectural changes require repeating the layout effort.The authors identify manual drafting as a scalability wall for larger processors.Source: §I · p. 1

II. FROM PHYSICS TO ABSTRACTION

  • The paper formalizes physical device characteristics as a rigorous geometric problem, addressing the gap in automation for irregular topologies and required physical features.Its abstraction covers physical background, layout, routing, and port assignment.Source: §I · p. 1

I. INTRODUCTION

  • The flow combines geometry-aware global partitioning, ILP-based port assignment that minimizes bridges and expected wire length, and hierarchical routing that incrementally enforces design rules.The abstraction is intended as a reusable foundation for design-automation methods.Source: §I · pp. 1–2, §II · p. 2
  • Complete, design-rule-compliant layouts are produced automatically in seconds to minutes, and complex layouts are solved up to 25× faster than the state of the art,.The flow is presented as fully automatic and manufacturing-ready.Source: §I · p. 2
  • The methods are released as the open-source tool mqt-scpd, providing an open foundation for future work.The tool is part of the Munich Quantum Toolkit.Source: §I · p. 2

A. Physical Background

The paper models superconducting-chip components and their physical interfaces as geometry subject to layout constraints. Qubits, couplers, and launchers form the principal layout components.

A. Physical Background

  • Superconducting chips route microwave and flux signals through CPWs, requiring rounded bends and conductor spacing to limit reflections and crosstalk.Qubit counts increase the number of control lines and tighten these constraints.Source: A. Physical Background · p. 2

B. SCQC Layouts

  • Qubits are modeled as obstacle polygons with readout and control terminals, while a regular-grid constraint governs their placement.The two illustrated floating, fixed-frequency geometries support two-way or four-way connectivity.Source: B. SCQC Layouts · p. 3, Figure 1 · p. 3
  • Couplers are modeled as routing obstacles with a flux terminal and an adjacency constraint placing each between a pair of qubits.Tunable couplers adjust coupling through applied magnetic flux.Source: B. SCQC Layouts · p. 3
  • Launchers are modeled as routing obstacles with fixed source terminals constrained to the chip boundary.They serve as external interfaces and are integrated with the qubit and coupler layout components.Source: B. SCQC Layouts · pp. 2–4
  • The layout abstraction treats qubits, couplers, and launchers as structured geometric components, with obstacle avoidance enforced during routing.The 4-qubit and 9-qubit examples are translated from physical designs into abstract representations.Source: B. SCQC Layouts · p. 4, Figure 2 · p. 4

C. Routing

Routing is formulated around physically motivated geometric constraints and distinct wire types. The framework also accounts for bridge-assisted access to otherwise unreachable interior regions.

C. Routing

  • Routing enforces minimum bend radius, straight segments at interfaces, exact resonator length, and minimum clearance between conductors.The constraints map physical concerns including signal reflections, resonator frequency, and crosstalk into geometric rules.Source: C. Routing · p. 4
  • Launcher-to-port wires, resonators, and feedlines have distinct physical roles and constraints, including fixed resonator lengths and a maximum resonator capacity per feedline.The three wire classes are Wp, Wr, and Wf.Source: C. Routing · p. 5
  • Airbridges lift wires over planar obstacles to open routing channels into interior regions, but limited bridge availability can leave some inner ports unreachable.The framework models airbridges and CPW couplers as routing components and minimizes the number of bridges.Source: C. Routing · p. 5
  • The routing problem combines layout and routing components, wire constructs, constraints, and objectives to determine assignments and routes.The objectives include wire length, clearance, bends, and bridge count.Source: C. Routing · pp. 5–6

D. Port Assignment

Port assignment maps wire constructs to component terminals under one-to-one and sequencing constraints. Assignment choices affect bridge crossings and route quality.

D. Port Assignment

  • Launcher-to-port wires and resonators each connect two terminals, while feedlines form ordered sequences from one launcher to another through intermediate coupler terminals.A feedline can traverse at most rutil intermediate CPW-coupler terminals.Source: D. Port Assignment · p. 6
  • Each control and flux terminal is assigned exactly one launcher-to-port wire, each qubit receives one resonator, and launcher terminals are used by at most one wire.The number of launcher-to-port wires is q + c, and the number of resonators is q.Source: D. Port Assignment · p. 6
  • The alternative valid assignment has more bridge crossings and greater launcher-to-port wire length than the primary assignment, making it less favorable under the objectives.The example illustrates that terminal mapping affects routing quality.Source: D. Port Assignment · p. 6
  • The complete design problem seeks assignments and routes that satisfy layout, routing, and assignment constraints while optimizing the objectives.The formulation represents components, wires, constraints, and objectives as sets C, W, R, and O.Source: D. Port Assignment · p. 6

III. DESIGN AUTOMATION

Existing automation tools omit physical features or rely on regular layouts, leaving them unable to address complex planar-chip designs. The proposed flow partitions geometry, assigns ports, and routes nets through a hierarchical pipeline.

A. Shortcomings of Related Work

  • Existing approaches either simplify the design problem or omit required features, limiting them to regular architectures rather than complex layouts with tunable couplers and tight clearances.The reviewed methods lack support for requirements including resonators, feedlines, flux-control ports, or fixed-length resonator routing.Source: A. Shortcomings of Related Work · pp. 6–7

B. General Idea

  • Geometry-aware partitioning assigns routing regions realistic edge capacities so later assignments respect bottlenecks and cavities.Port assignment then allocates inner bridges before outer ports and connections, optimizing bridge usage and then wire length.Source: B. General Idea · p. 7
  • The flow partitions geometry, assigns ports, and routes nets through a four-stage hierarchical routing pipeline that enforces physical, clearance, curvature, and resonator-length constraints.The routing stages are global routing, detailed routing, Dubins A* refinement, and feedline routing.Source: B. General Idea · p. 7

C. Global Partitioning

Narrow passages and cavities can make apparently valid port assignments physically unroutable. The method rasterizes the layout, detects bottlenecks using its Voronoi graph, and uses their geometry to form capacity-aware regions.

C. Global Partitioning

  • Cavities and narrow passages can make assignments unroutable when clearance or neighboring-port geometry leaves insufficient space for the assigned bridges and wires.The example includes a cavity unable to fit three parallel wires and a bridge assignment that conflicts with neighboring ports.Source: C. Global Partitioning · pp. 7–8, Figure 6 · p. 8

1) Grid Construction and Bottleneck Detection

  • The layout is rasterized into a partitioning grid that represents component obstacles, separates inner from outer regions, and initializes outer cells.The obstacles include qubits, couplers, and launchers; minimum straight path and clearance are marked as obstacles for each target node.Source: 1) Grid Construction and Bottleneck… · p. 8
  • Voronoi paths through free space and a distance transform identify narrow passages, whose bottleneck lines are reconstructed from nearby obstacles.Bottleneck centers are detected at local minima and saddle points along nonbranching Voronoi nodes.Source: 1) Grid Construction and Bottleneck… · p. 8, Figure 7 · p. 8

2) Cavity Trees and Geometry-Aware Partitions

The cavity tree records how target ports connect to the chip boundary through capacity-limited bottlenecks. Pruning it retains the restrictive passages used to define geometry-aware partitions.

2) Cavity Trees and Geometry-Aware Partitions

  • A cavity tree is a directed acyclic graph rooted at the chip boundary or launcher, with bottleneck nodes carrying capacities and target ports as leaves.A leaf-to-root breadth-first search traces connections from targets through bottlenecks to launcher roots.Source: 2) Cavity Trees and Geometry-Aware… · p. 8
  • The tree captures which bottlenecks restrict each target; sequential bottlenecks are reduced to the smallest capacity, and branches without targets are removed.In the example, one target path crosses two capacity-2 bottlenecks, while other passages are either unnecessary or too narrow for a wire.Source: 2) Cavity Trees and Geometry-Aware… · p. 9
  • Pruned cavities are integrated with the initial global cells, and remaining grid nodes are assigned to the closest partition to cover the layout.The resulting partitions constrain bridge usage during port assignment and form the foundational global-routing graph.Source: 2) Cavity Trees and Geometry-Aware… · p. 9

D. Port Assignment Computation

Port assignment allocates point-to-point and resonator connections plus feedlines while optimizing bridge count and expected wire length. Inner targets are assigned to bridges before outer ports and connections are solved.

D. Port Assignment Computation

  • Port assignment handles point-to-point and resonator assignments and feedline allocation, optimizing bridge count and expected wire length.The assignment is split into inner and outer steps and formulated as ILPs; the sequential decomposition is optimal only for the fixed inner assignment.Source: D. Port Assignment Computation · p. 9

1) Inner Assignment

  • Inner targets are sinks and dedicated bridges are capacity-constrained sources; minimum-cost flow assigns targets to bridges with minimum total wire length.The inner assignment is formulated on a Hanan grid for each inner partition.Source: 1) Inner Assignment · p. 9, D. Port Assignment Computation · p. 9
  • Cavity-tree constraints limit bridge use to physically routable assignments, including capacity reserved for mandatory readout nets.In the example, a zero-capacity bottleneck bars one target, while another bottleneck allows only one of two bridges because it must also carry readout.Source: 1) Inner Assignment · pp. 9–10

2) Outer Assignment

Outer port assignment is encoded as an ILP over an assignment graph, enforcing valid net and feedline assignments while minimizing bridge use and expected wire length.

2) Outer Assignment

  • An assignment graph represents resonators, launchers, and control/flux targets, with edge weights encoding bridge costs for feedline connections.Resonator edges connect adjacent resonators in cyclic order or a resonator to its launcher.Source: 2) Outer Assignment · p. 10
  • Cyclic assignment variables enforce ordered terminal sequences, feedline launcher endpoints and capacity, unique launcher use, and assignments for flux and control targets.Regular-port ordering prevents crossing assignments; resonator nodes need a separate launcher only when their launcher edge is selected.Source: 2) Outer Assignment · p. 10
  • The ILP minimizes bridge usage first and expected wire length second; its O(q)-variable formulation uses symmetry breaking to keep solving time negligible against geometric routing.The bridge objective uses feedline-edge weights, while the wire-length objective penalizes target distance to the nearest launcher.Source: 2) Outer Assignment · p. 10
  • After the outer assignment is solved, every net is mapped to dedicated ports and the flow proceeds to physical routing.The assignment satisfies Rassign while minimizing bridge usage and expected wire length.Source: 2) Outer Assignment · p. 10

E. Routing

The routing flow turns assigned nets into physical routes through two A* algorithms, cyclic conflict resolution, and a four-stage hierarchy that progressively enforces design rules.

1) Routing Algorithms

  • Grid A* uses obstacle-free cells and a proximity penalty, while Dubins A* expands straight and arc moves to enforce minimum straight length and bending radius by construction.Dubins routing also supports fixed-length resonators through meander insertion, but its larger state space makes it the runtime-critical stage.Source: 1) Routing Algorithms · p. 11

2) Conflict Resolution

  • Cyclic rip-up-and-reroute alternates forward and backward passes, targeting adjacent nets because assigned point-to-point and resonator nets are cyclically ordered and mutually crossing-free.A failed route triggers iterative removal of subsequent nets in a forward pass or preceding nets in a backward pass.Source: 2) Conflict Resolution · p. 11

3) Hierarchical Routing Pipeline

  • Point-to-point and resonator nets route before feedlines; global routing sets coarse paths, detailed routing enforces clearance, and Dubins refinement adds radius and length constraints.Global partition-border ports form the routing grid; the detailed router treats direct cyclic neighbors as clearance-inflated obstacles.Source: 3) Hierarchical Routing Pipeline · p. 11
  • Feedlines are routed along ordered terminal sequences through assigned coupler positions; conflicting point-to-point or resonator nets are selectively rerouted around feedline segments and bridge crossings.If a resonator route exceeds its fixed length, its CPW coupler shifts toward the resonator until the effective length matches.Source: 3) Hierarchical Routing Pipeline · p. 11, Figure 10 · p. 12
  • The heuristic pipeline cannot guarantee valid routing for every instance: layouts may be infeasible from congestion, or rip-up-and-reroute may miss a solution.Geometry-aware partitioning and assignment are designed to avoid infeasible configurations upfront.Source: 3) Hierarchical Routing Pipeline · p. 12

IV. EXPERIMENTAL EVALUATION

The evaluation implements the flow in mqt-scpd and tests automated planar layouts across a range of benchmark architectures and sizes, using runtime and physical-quality measures.

IV. EXPERIMENTAL EVALUATION

  • The proposed methods are implemented in the open-source mqt-scpd tool, and an interdisciplinary team of design-automation researchers and superconducting-hardware experts conducted the evaluation.The tool implements the three-stage flow and generates complete planar-chip layouts intended to be ready for fabrication.Source: §IV · p. 12

A. Experimental Setup

  • The benchmark architectures include grid layouts and X-shaped topologies, with added three-qubit blocks at each corner in the larger X-shaped variants.The illustrated set includes 2×2 and 3×3 grids, a 3×3 core with eight boundary qubits, and two X-shaped variants.Source: Figure 11 · p. 12
  • Benchmarks span 4 to 69 qubits and automatically run partitioning, port assignment, and routing; instances above 48 launcher ports chiefly probe scalability because planar boundary bottlenecks make that count impractical.The 45Q–69Q layouts extend the 33Q X-shaped scheme, while larger instances would require multilayer architectures in practice.Source: A. Experimental Setup · p. 12
  • Experiments use 185 µm minimum clearance, 100 µm minimum straight length, and 50 µm minimum bending radius, recording runtime, wire length, clearance, angle transitions, and bridge count.Target resonator length and feedline capacity vary with layout size and launcher availability; inner-region resonators use an adjusted target length.Source: A. Experimental Setup · p. 12

B. Experimental Results

Every evaluated layout satisfies the stated physical constraints; the reported metrics also show practical runtimes and structural trends as instance size increases, without a direct automated baseline comparison.

B. Experimental Results

  • Every evaluated instance strictly satisfies the physical constraints, and Table I reports benchmark results while Fig. 12 shows a fully routed 33-qubit layout.Detailed designs for all instances are available in the supplementary data repository.Source: B. Experimental Results · pp. 12–13, Table I · p. 13, Figure 12 · p. 13
  • The angle ratio rises monotonically from 4.71 to 9.47, while the bridge ratio stays between 0.42 and 0.55 and the clearance scaling factor between 0.62 and 1.08.The authors interpret these trends as increasing angle transitions per connection, proportional bridge demand, and consistent wire spacing quality as layouts scale.Source: B. Experimental Results · p. 13
  • Direct quantitative benchmarking is not feasible because the current literature lacks other automated approaches for this problem formulation.Runtime remains seconds to a few minutes across instances, with a maximum of 385 s for the 69-qubit layout.Source: B. Experimental Results · p. 13

C. Discussion

The proposed flow handles substantially heavier routing and tighter clearance constraints than the compared layouts, while remaining faster. The conclusion presents it as a practical planar design flow and a foundation for future multilayer automation.

C. Discussion

  • The 33Q and 69Q variants manage 150 versus 40 and 313 versus 80 point-to-point connections, respectively, while enforcing 185 µm rather than 50 µm minimum wire clearance.Both layouts also accommodate fixed-length routing Rl and non-uniform chip architectures.Source: C. Discussion · p. 13
  • 25× faster for the comparable 33Q instance than Yang et al.; the proposed 69Q layout is over 5× faster than Yang et al.’s 64Q layout.Against Yu et al., the proposed flow is over 12.5× faster for the 32Q variant and 2.5× faster for the 69Q layout.Source: C. Discussion · p. 13
  • The flow fully routes layouts up to 69 qubits and resolves every evaluated instance, but provides no universal completeness guarantee for every conceivable edge case.Its quality-of-results metrics Oc, Oa, and Ob remain aligned with net counts and layout area.Source: C. Discussion · p. 13
  • The flow delivers manufacturing-ready, design-rule-compliant layouts in seconds to a few minutes, automating scales where manual drafting becomes impractical.Layout recurs with architectural changes within design cycles that span days to weeks when validation and simulation are included.Source: C. Discussion · p. 13

V. CONCLUSION AND FUTURE WORK

  • The conclusion frames the contribution as a formal geometric abstraction of device physics and a three-stage automated planar design flow.The flow generates complete, design-rule-compliant results and is reported as up to 25× faster than the state of the art.Source: §V · p. 13
  • The abstraction carries over to multilayer designs, where stacked planes expand routing footprint and enable functional layer separation beyond planar routing and congestion limits.The paper identifies extending the flow to other superconducting circuit architectures as a next step.Source: §V · p. 14
  • The methods are released as the open-source tool mqt-scpd, and the work provides a reproducible dataset for future benchmarking.The tool is presented as a foundation for community development of design automation for ultra-scalable quantum processors.Source: §V · p. 14

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