PaperlayerView exact revision on arXiv

Source-linked AI summary

CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs

Qifan Zhang, Ruijie Li, Fangzhou Zhang, Qian Ma, Hui Li, Furui Zhan, Yongpeng Wang, Liying Hao, Shikai Guo

arXiv:2610.09549v1cs.LG

TL;DR

Learning-based AIG representations must capture circuit-level functional dependencies beyond local structure and remain consistent under functionality-preserving transformations. CircuitGate encodes global PI support and support-overlap-aware reconvergence, with Boolean constraints to encourage consistency. It achieves the lowest MAE across the reported ForgeEDA, EPFL, and ITC’99 evaluations for both tasks, with reductions reaching 21.7% and 14.2%.

  • Problem

    GNN-based AIG methods rely mainly on local message passing, leaving circuit-level functional dependencies and consistency across functionality-preserving topology changes insufficiently modeled.

    Source: §1 · pp. 1, 3, §2.1 · p. 4

  • Method

    CircuitGate combines circuit-level context, global PI-support encoding, support-overlap-aware reconvergent-fanin modeling, and logic-inspired Boolean constraints.

    Source: §1 · pp. 2–3

  • Results

    CircuitGate achieves the lowest MAE on both tasks across ForgeEDA, EPFL, and ITC’99; reductions reach 21.7% for equivalent-gate identification and 14.2% for signal-probability prediction.

    Source: §1 · p. 3, §5 · p. 10

  • Takeaways & Limitations

    The reported results support circuit-level functional priors for accurate and efficient AIG representation learning, with competitive inference latency.

    Source: §5 · p. 10

    The parity-indexed PI-support sets provide a path-based structural approximation of exact Boolean functional support.

    Source: §3.3 · p. 5

Abstract

from arXiv · show

And-Inverter Graphs (AIGs) are fundamental representations for logic synthesis and verification in Electronic Design Automation (EDA). As structured representations of complex digital systems, AIGs require models to capture functional dependencies beyond local structure and remain robust to functionality-preserving transformations. In learning-based AIG representation, existing approaches are predominantly based on GNNs and rely on local gate-level message passing, limiting their ability to capture circuit-level functional context and making the learned representations sensitive to topology-specific patterns. Therefore, we propose CircuitGate, a function-aware AIG representation learning framework that advances from gate-level semantics to circuit-level functional modeling. CircuitGate explicitly encodes global primary-input (PI) support and models support-overlap-aware reconvergence between fanins, while incorporating logic-inspired Boolean constraints to encourage functionally consistent representations. We evaluate CircuitGate on the large-scale ForgeEDA benchmark and further validate it on the EPFL and ITC'99 benchmarks. Across equivalent-gate identification and signal-probability prediction tasks, CircuitGate consistently outperforms existing methods, achieving up to 21.7% and 14.2% reductions in MAE, respectively. Under direct ForgeEDA-to-OpenABC transfer without fine-tuning, CircuitGate also achieves the best equivalent-gate identification performance, demonstrating strong cross-dataset generalization. These results demonstrate the effectiveness of modeling circuit-level functional dependencies beyond local topology.

1 INTRODUCTION

AIG representations need to capture circuit-wide functional dependencies and remain consistent when synthesis changes topology without changing Boolean function. CircuitGate adds global PI-support and reconvergent-fanin context with Boolean constraints, and is evaluated across multiple benchmarks and tasks.

1 INTRODUCTION

  • Existing methods rely mainly on local message passing, which can miss complete PI support and shared-support relationships between reconvergent fanins.Functionality-preserving synthesis can also change topology and leave equivalent circuits with inconsistent representations.Source: §1 · p. 2
  • CircuitGate combines global PI-support information and support-overlap-aware reconvergent-fanin relationships with Boolean constraints to encourage functionally consistent representations.Its stated goal is to capture functional context beyond the local structural neighborhood despite synthesis-induced structural variations.Source: §1 · pp. 2–3
  • Zero-shot ForgeEDA-to-OpenABC transfer further demonstrates cross-dataset generalization across AIG representation learning tasks.The introduction describes the transfer as occurring without fine-tuning.Source: §1 · p. 3
  • On ForgeEDA, CircuitGate reduces MAE over the second-best methods by 21.7% for equivalent-gate identification and 13.8% for signal-probability prediction.The benchmark comprises 83,155 circuit instances derived from 4,450 AIGs across 1,189 open-source designs.Source: §1 · p. 3
  • On EPFL, MAE reductions are 19.5% for equivalent-gate identification and 14.2% for signal-probability prediction; on ITC’99, they are 13.4% and 8.4%, respectively.Both reductions are over the second-best methods.Source: §1 · p. 3

2 RELATED WORK

Prior AIG methods increasingly use scalable GNN propagation, but global PI dependencies and reconvergent-fanin correlations remain difficult to model explicitly. Separately, consistency under topology-changing transformations remains a challenge that CircuitGate targets with functional context and logic-inspired regularization.

2.1 FUNCTIONAL DEPENDENCY MODELING

  • Traditional support-based analysis tracks PI dependencies explicitly, while GNN approaches scale through implicit propagation; CircuitGate addresses the resulting global-dependency and reconvergence gaps.The related-work discussion traces GNN-based AIG representation from DeepGate through later methods and complementary approaches.Source: §2.1 · pp. 3–4
  • Standard k-layer message-passing GNNs aggregate at most k-hop neighborhoods, making global PI dependencies difficult to preserve across deep logic hierarchies.Shared PI support between fanins is also typically reflected only indirectly rather than explicitly modeled.Source: §2.1 · p. 4

2.2 SYNTHESIS ROBUSTNESS

  • Consistency under functionality-preserving topology transformations remains a distinct challenge despite progress in learning-based synthesis and cross-domain circuit representations.CircuitGate targets this setting with circuit-level context, global PI-support encoding, reconvergence-aware modeling, and logic-inspired regularization.Source: §2.2 · p. 4

3 METHOD

CircuitGate augments topology-driven AIG message passing with circuit-level context, explicit PI dependencies, and support-aware reconvergence. Logic-inspired Boolean constraints regularize representations across structural realizations.

3.1 OVERVIEW

  • CircuitGate combines circuit-level context, global PI-dependency encoding, reconvergent-fanin modeling, and logic-inspired constraints to learn functional representations beyond local gate semantics.The framework augments local message passing with these complementary sources of functional context.Source: §3.1 · p. 4

3.2 CIRCUIT-LEVEL CONTEXT AUGMENTATION

  • Node representations are augmented with circuit-position, fanout, output-status, and PI-support-coverage attributes to distinguish nodes with the same gate type.These EDA-native features help separate structurally different candidates before message passing begins.Source: §3.2 · pp. 4–5

3.3 GLOBAL PI-DEPENDENCY ENCODING

  • Nodes receive fixed-width, parity-aware summaries of structural PI dependencies, which are injected after the first propagation layer and reused in subsequent updates.These path-based support sets approximate exact Boolean functional support; a PI may occur in both parity sets.Source: §3.3 · p. 5

3.4 RECONVERGENT-FANIN DEPENDENCY MODELING

  • For two-input AND nodes, shared PI support between fanins gates global dependency context during local updates.The six-dimensional descriptor encodes reconvergence presence, support overlap and size, fanin-depth imbalance, and parity contrast.Source: §3.4 · p. 6

3.5 TRAINING OBJECTIVE

  • Logic-inspired penalties target NOT complementarity and AND probability bounds without assuming independent fanins.The bounds remain applicable to reconvergent structures.Source: §3.5 · pp. 6–7

4 EXPERIMENTS

Experiments compare CircuitGate with existing methods, examine its component contributions and efficiency, and test robustness and hyperparameter sensitivity. CircuitGate leads on equivalent-gate identification across three benchmarks, while further results characterize its ablations, latency, and representation consistency.

4.1 EXPERIMENTAL SETTINGS

  • The evaluation uses ForgeEDA, EPFL, and ITC’99, with source-disjoint ForgeEDA splits and parent-circuit-isolated splits for EPFL and ITC’99.The compared methods include general-purpose GNNs, the DeepGate series, and circuit-specific approaches.Source: §4.1 · p. 7
  • MAE is the primary equivalent-gate identification metric; signal-probability prediction reports MAE, and topology robustness uses CKA between matched nodes.The setup also reports parameter count, inference latency, and accuracy–efficiency cost.Source: §4.1 · p. 7

4.2 RQ1: HOW DOES CIRCUITGATE COMPARE WITH EXISTING METHODS?

  • CircuitGate achieves the best equivalent-gate identification performance across ForgeEDA, EPFL, and ITC’99.Table 1 reports the equivalent-gate identification comparison.Source: Table 1 · p. 8, §4.2 · p. 8

4.3 RQ2: HOW DOES EACH COMPONENT CONTRIBUTE TO CIRCUITGATE?

  • Removing PI-support encoding causes the largest ForgeEDA MAE degradation at 34.4%, followed by reconvergence modeling at 29.6%.Component impacts vary by benchmark: circuit-level context matters most on EPFL, while logic constraints provide the largest gain on ITC’99.Source: §4.3 · p. 8, Table 3 · p. 8
  • Per-circuit PI-token permutation maintains comparable performance, but removing polarity or retaining only cardinality/coverage statistics degrades performance.These results support the importance of fine-grained polarity-aware PI support.Source: §4.3 · p. 8

4.6 RQ5: HOW SENSITIVE IS CIRCUITGATE TO HYPERPARAMETERS?

  • The selected settings are α = 0.05, λlogic = 0.05, λAND = 0.25, λNOT = 1.0, ds = 64, L = 9, and merge-gate reconvergence.Overly strong logic regularization or insufficient propagation depth degrades performance; further increases in support-sketch dimension or depth add limited benefit.Source: Figure 3 · p. 9, §4.6 · p. 9

4.4 RQ3: HOW EFFICIENT AND SCALABLE IS CIRCUITGATE?

  • On 200 ForgeEDA test circuits, CircuitGate obtains 0.0433 MAE at 12.4393 ms latency, reducing MAE by 23.1% over MGVGA with a 1.3% latency increase.Its accuracy–efficiency cost (AEC) is 1.0275, the best reported.Source: Table 4 · p. 9, §4.4 · p. 9

4.5 RQ4: HOW ROBUST IS CIRCUITGATE TO TOPOLOGY CHANGES?

  • CircuitGate has the highest CKA under all four synthesis transformations, with average CKA of 0.8341.The evaluation uses matched-node representations under topology transformations.Source: Table 5 · p. 9, §4.5 · p. 9

5 CONCLUSION

CircuitGate learns AIG representations using circuit-level context, global PI dependencies, reconvergent-fanin modeling, and a logic-inspired objective. Across ForgeEDA, EPFL, and ITC’99, it achieves the lowest MAE on both evaluated tasks while maintaining competitive inference latency.

5 CONCLUSION

  • CircuitGate combines circuit-level context, global PI dependencies, reconvergent-fanin modeling, and a logic-inspired objective to learn AIG functional representations.The conclusion presents these mechanisms as capturing relationships beyond local connectivity while reducing reliance on topology-specific patterns.Source: §5 · pp. 9–10
  • Across ForgeEDA, EPFL, and ITC’99, CircuitGate achieves the lowest MAE on equivalent-gate identification and signal-probability prediction, with competitive inference latency.The conclusion also highlights PI-support encoding and reconvergence modeling in the ablation results.Source: §5 · p. 10

REPRODUCIBILITY STATEMENT

  • The authors provide an anonymous implementation to facilitate reproducibility.Dataset statistics and splits, evaluation protocols, implementation settings, robustness evaluation, and hyperparameter analyses are described in the paper and appendix.Source: REPRODUCIBILITY STATEMENT · p. 10

AI USE STATEMENT

  • Generative AI was used only for language polishing, with edits reviewed and approved by the authors.The authors state that AI was not used for study design, methodology, analysis, result generation, or scientific interpretation.Source: AI USE STATEMENT · p. 10

A.1 TASK SUPERVISION DETAILS

The supervision details use final node representations for two tasks, with pairwise functional similarity and signal probability as targets. ForgeEDA provides 2,048 intra-instance node pairs per circuit instance.

A.1 TASK SUPERVISION DETAILS

  • The final node representation h(L) is used for the two downstream tasks.The supplied passage identifies the representation but does not specify further task-specific transformations.Source: §A.1 · p. 13
  • The supervised node-pair set is Q, the signal-probability target is y_v, and s_ij is the cosine similarity between z_i and z_j.These quantities are defined in the description of the supervised losses.Source: §A.1 · p. 13
  • Each ForgeEDA circuit instance uses 2,048 intra-instance node pairs from the benchmark’s tt pair index; d^tt_ij = 0 indicates functional equivalence.The pairwise target is derived from normalized truth-table distance.Source: §A.1 · p. 13
  • Signal-probability prediction uses L_task = L_prob, while equivalent-gate identification uses a task loss with auxiliary probability supervision weighted by α.Empty-set averages are defined as zero.Source: §A.1 · p. 13

A.2 DATASET STATISTICS

This section identifies tables reporting dataset statistics for ForgeEDA and the processed EPFL benchmark.

A.2 DATASET STATISTICS

  • Table 6 reports statistics of the ForgeEDA dataset.The table caption attributes the dataset to Shi et al. (2025a).Source: Table 6 · p. 13
  • Table 7 reports statistics of the processed EPFL benchmark dataset.The supplied caption does not give individual statistics.Source: Table 7 · p. 13

A.3 EVALUATION PROTOCOL AND EFFICIENCY METRIC

The protocol uses disjoint circuit or parent-circuit splits across the benchmarks and evaluates equivalent-gate prediction, signal probability, and representation consistency. It also reports inference efficiency and cautions that equivalent-gate AP should be read alongside each benchmark’s positive-pair rate.

Dataset splits

  • ForgeEDA uses a source-disjoint 5%/5%/90% train/validation/test split; EPFL and ITC’99 also keep subcircuits from each parent circuit within a single split.For EPFL, 16 parent circuits yield 51/27/23 training/validation/test subcircuits; ITC’99 uses 38/7/12 subcircuits from mutually disjoint parent circuits.Source: §A.3 · pp. 13–14

Evaluation metrics

  • Equivalent-gate evaluation uses cosine similarity against a continuous truth-table-distance target, with MAE and MSE per-circuit averages and AP and validation-thresholded F1 on pooled pairs.Positive pairs have dtt_ij = 0; checkpoints are selected by validation MAE, and test splits are reserved for final evaluation.Source: §A.3 · p. 14

Pair distribution

  • ForgeEDA’s positive-pair rate is 0.464648%, versus 10.4561% on EPFL; ITC’99 uses balanced pairs, so AP values should be interpreted with prevalence in view.AP is computed from pooled test pairs, and its absolute value depends on class prevalence.Source: §A.3 · p. 14

Latency measurement

  • Inference latency is neural inference on preprocessed graphs, measured at batch size one on the same 200 test circuits; one-time preprocessing and PI-support construction are excluded.Measurements use an NVIDIA RTX A6000 GPU.Source: §A.3 · p. 14

Accuracy–efficiency metric

  • The accuracy–efficiency cost combines MAE, latency, and model complexity; lower AEC indicates a better joint trade-off.The model-size penalty is logarithmically normalized to [0, 1], scaling MAE × latency by a factor between one and two.Source: §A.3 · pp. 14–15

A.4 CROSS-DATASET GENERALIZATION TO OPENABC

CircuitGate’s ForgeEDA-trained checkpoints are evaluated on OpenABC without fine-tuning or parameter adaptation, testing transfer to an unseen circuit distribution. CircuitGate achieves the lowest MAE in this setting.

Evaluation setting

  • The transfer test applies ForgeEDA-trained checkpoints to OpenABC without fine-tuning or parameter adaptation, measuring generalization to an unseen circuit distribution.All methods use their corresponding ForgeEDA checkpoints and the same OpenABC test protocol.Source: §A.4 · p. 15

Cross-dataset evaluation

  • 0.10125 MAE: CircuitGate has the lowest error under direct ForgeEDA-to-OpenABC transfer, ahead of DeepGate3 at 0.10223.CircuitGate also outperforms MGVGA at 0.11177, DeepGate4 at 0.11476, and the remaining baselines.Source: §A.4 · p. 15

A.5 ADDITIONAL PI-SUPPORT CONTROLS

The additional studies probe PI-support encoding, preprocessing scale, topology robustness, hyperparameter sensitivity, and propagation architecture. They report polarity-sensitive support benefits, feasible preprocessing at the tested scale, and robustness across synthesis transformations.

A.5 ADDITIONAL PI-SUPPORT CONTROLS

  • Per-circuit PI-token permutation closely matches the full model, but removing support polarity or retaining only cardinality and coverage degrades performance.The controls indicate that fine-grained, polarity-aware support structure—not cross-circuit PI-index alignment—accounts for the observed benefit.Source: §A.5 · p. 15

A.6 COMPLETE-GRAPH PREPROCESSING SCALABILITY

  • 525,762 nodes: the largest profiled graph completes feature construction in 14.03 s and input-to-cache preprocessing in 14.89 s, at 2.73 GiB peak RSS.All 21 profiling runs complete; hyp takes 15.03 s despite fewer nodes than dft, alongside 88.96 million parity-specific support memberships.Source: §A.6 · pp. 15–16

A.7 SYNTHESIS-INDUCED TOPOLOGY ROBUSTNESS DETAILS

  • CircuitGate achieves the lowest equivalent-gate MAE under all four synthesis transformations in the topology-robustness evaluation.The study verifies original/transformed circuit equivalence and uses matched nodes or pairs with fixed ForgeEDA checkpoints.Source: §A.7 · p. 16

A.8 ADDITIONAL MATERIALS OF RQ5: HYPERPARAMETER SENSITIVITY

  • 0.0695 MAE: increasing λlogic from 0.05 to 0.5 degrades error; the default 0.05 setting achieves 0.0433 MAE.Across the evaluated settings, the default α = 0.05 and λAND = 0.25 also achieve 0.0433 MAE, while λAND = 4.0 yields 0.0451.Source: §A.8 · p. 16
  • 0.0433 MAE: nine propagation layers and merge-gate reconvergence perform best among the evaluated settings; increasing depth to 11 or 13 layers adds no gain.Merge-gate reconvergence reduces MAE by 4.6% versus the binary-flag formulation and by 22.8% versus omitting reconvergence modeling.Source: §A.8 · pp. 16–17, Table 13 · p. 17

A.9 PROPAGATION AND ARCHITECTURE DETAILS

  • The PI-dependency representation is introduced after the first propagation layer and retained thereafter; the reconvergence descriptor controls its contribution during node updates.The first layer initializes two latent states using an initialization aggregation operator; PI, AND, and explicit NOT nodes share propagation and update rules, while only AND nodes receive reconvergence descriptors.Source: §A.9 · p. 18

Related papers

Loading 2610.09549v1…