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Communication-Aware Qubit Placement and Automatic Node-Count Allocation for Distributed State-Vector Simulation

Íñigo Aréjula-Aísa, Sergio Iserte, Petter Sandås, Ricard S. Raigada-García, Antonio J. Peña

arXiv:2610.09659v1cs.DCcs.ET

TL;DR

Distributed simulation faces communication costs shaped by qubit placement and node count. This paper combines graph-based placement optimization with predictive node-count selection; placement outcomes vary by circuit, with some cuts reduced or eliminated and QFT cases unchanged.

  • Problem

    For a fixed node count, qubit placement affects communication, while the appropriate node count depends on circuit structure and is not determined by qubit count alone.

    Source: §I · p. 1

  • Method

    The paper uses simulated annealing to minimize communication cuts and a predictive efficiency model to select node count under a user-defined degradation constraint.

    Source: §I · p. 2, A. Qubit Placement Layout · p. 4

  • Results

    Placement effects were circuit-dependent: some cuts fell or reached zero, while qft n29 variants showed no improvement and qft n29 transp. remained at 1.00×.

    Source: 1) Analytical Results · p. 8, 2) Performance Analysis · p. 9

  • Takeaways & Limitations

    Node count can be treated as an efficiency decision based on the circuit and a user-defined performance threshold, rather than fixed arbitrarily or chosen through an expensive sweep.

    Source: §VIII · p. 12

    The authors acknowledge limitations of the current approach but do not specify them in this passage.

    Source: §VII · p. 12

Abstract

from arXiv · show

Distributed quantum circuit simulation enables the execution of large-scale quantum algorithms by partitioning qubits across multiple computational nodes. However, inefficient qubit placement frequently leads to excessive inter-node communication, severely limiting performance and scalability. This work introduces a communication-aware qubit layout optimization framework that systematically minimizes data exchange among nodes while dynamically selecting the optimal number of computational resources. Integrated into the QuCSLO library, our approach supports dynamic node scaling, OpenQASM parsing, and seamless integration with the QuEST simulator. Extensive evaluations on both synthetic benchmarks and real-world QASMBench circuits demonstrate that optimized layouts significantly reduce communication cuts and yield runtime speedups of over 2x compared to identity layouts, particularly in highly entangled circuits. Our results underscore the critical impact of strategic qubit placement on distributed simulation efficiency and provide a practical, resource-scalable solution for quantum workloads.

I. INTRODUCTION

Distributed state-vector simulation extends exact quantum-circuit simulation beyond a single node’s memory, but introduces communication costs that depend on qubit placement and node count. The paper proposes circuit-aware placement and node-count selection, against the background of distributed execution and simulated annealing.

I. INTRODUCTION

  • State-vector memory grows exponentially with qubit count, making distributed execution necessary for circuits beyond one node’s capacity.Distributed simulators partition the state vector across processes, allowing each process to update its local portion.Source: §I · p. 1, A. Distributed State-Vector Simulation · p. 2
  • For a fixed node count, placement determines which logical qubits are global; the optimal node count also depends on circuit structure.More nodes increase memory and parallelism but can add communication, so the largest allocation is not necessarily fastest.Source: §I · p. 1
  • The paper proposes a simulator-agnostic placement optimizer using weighted graphs and simulated annealing, plus a predictive model that recommends node count under a degradation constraint.It evaluates the approaches on synthetic circuits and QASMBench circuits.Source: §I · p. 2

A. Distributed State-Vector Simulation

  • Non-diagonal gates on global qubits require interprocess communication, while gates on local qubits can generally run without it.QuEST is the concrete simulator used to implement this distributed state-vector model in the experiments.Source: A. Distributed State-Vector Simulation · p. 2

B. Simulated Annealing

The section introduces simulated annealing and process malleability, then positions offline placement and automatic node-count selection against prior communication-reduction approaches. The paper’s method uses a single offline placement and selects node count in advance using a user-defined performance-degradation threshold.

B. Simulated Annealing

  • Simulated annealing explores neighboring candidates, accepting improvements and sometimes worsening moves to help escape local minima.The probability of accepting worsening moves decreases over time.Source: B. Simulated Annealing · p. 2

C. Process Malleability

  • Process malleability lets a parallel application change its process count at runtime without restarting the job.The experiments use DMR as the middleware realizing this capability.Source: C. Process Malleability · p. 2

III. RELATED WORK

  • Prior work includes circuit-specific placement, runtime reordering, and circuit partitioning; this method instead computes one placement offline without runtime reconfiguration.The placement is formulated as weighted graph partitioning and optimized with simulated annealing.Source: §III · pp. 2–3

IV. METHODOLOGY

  • Prior placement studies generally assume a fixed node count, whereas this paper selects node count in advance using a user-defined performance-degradation threshold.The proposed efficiency model addresses node-count selection alongside offline qubit placement.Source: §III · p. 3, §IV · p. 3

A. Qubit Placement Layout

The placement method models gate-target communication with a weighted graph and minimizes the resulting communication cut for a fixed number of global qubits. It uses simulated annealing for two-target gates and applies the selected layout through a semantics-preserving qubit relabeling.

A. Qubit Placement Layout

  • The graph assigns node weights to single-target non-diagonal gates and edge weights to two-target non-diagonal gates; a global endpoint makes the corresponding weight communicate.Diagonal gates and control qubits are omitted because they do not determine communication in this model.Source: A. Qubit Placement Layout · p. 3
  • For a layout, the communication cut counts non-diagonal gates with at least one target in the global set.The figure marks communicating global-qubit gates in red nodes and boundary-straddling two-target gates in red edges.Source: A. Qubit Placement Layout · p. 3, Figure 1 · p. 4
  • The worked example reduces the communication cut from three to one by changing the placement, without modifying the circuit or simulator.The optimized layout places q3 in the local region and a lighter qubit in the global region.Source: A. Qubit Placement Layout · p. 3
  • With only single-target non-diagonal gates, assigning the k lowest-weight qubits globally gives the optimal layout; two-target gates require a broader search.The search swaps one global and one local qubit, updating the objective using affected gates.Source: A. Qubit Placement Layout · pp. 3–4
  • The simulated-annealing search runs in O(N · M) time and retains its best layout, but does not guarantee global optimality.The selected layout is applied by relabeling qubit indices, preserving circuit semantics without moving amplitudes.Source: A. Qubit Placement Layout · p. 4

B. Node-Count Efficiency Model

The model predicts communication-related scaling degradation from circuit statistics and cluster calibration, then selects the largest feasible node count within a user-set degradation threshold. Memory limits set the feasible range, while additional nodes trade smaller local state-vector blocks for potentially greater communication.

B. Node-Count Efficiency Model

  • Per-node memory imposes a lower bound on k, while k < N caps the feasible range because each register must retain a local qubit.Each node stores 2^(N-k) amplitudes, with 16 bytes per amplitude.Source: B. Node-Count Efficiency Model · p. 4
  • Doubling nodes halves each local amplitude block but can increase communication when the added global qubit is touched by non-diagonal gates.More nodes may speed execution despite higher communication overhead.Source: B. Node-Count Efficiency Model · p. 4
  • The model expresses deviation from ideal linear scaling through O(k), with zero degradation corresponding to execution time halving when node count doubles.The model anchors degradation at kmin rather than the invalid k = 0 configuration for large N.Source: B. Node-Count Efficiency Model · pp. 4–5
  • The model estimates communication time from latency per communicating gate and bandwidth for exchanged data, using cutmin(k) and Wcomm(k).Wcomm(k) accounts for how controls reduce exchanged blocks.Source: B. Node-Count Efficiency Model · pp. 4–5
  • Cluster-calibrated ratios a(k) and b(k), combined with circuit statistics, predict efficiency without running the circuit.The circuit inputs include gate count, optimized cut, and communication weight; a(k) and b(k) are measured once per cluster.Source: B. Node-Count Efficiency Model · p. 5
  • The selector chooses the largest node count whose degradation from the smallest feasible count stays within threshold τ.The smallest feasible count is kmin = kmem.Source: B. Node-Count Efficiency Model · p. 5

V. IMPLEMENTATION

QuCSLO implements placement and node-count selection as reusable middleware for state-vector simulators. Its modules represent and import circuits, optimize layouts, select resources, and connect to the simulator and system software.

V. IMPLEMENTATION

  • QuCSLO implements the placement and resource-selection models as middleware reusable across state-vector simulators without modifying or reimplementing the simulator.The library is organized into five modules.Source: §V · p. 5
  • The Circuit Representation stores an ordered gate sequence, while Circuit Import parses OpenQASM 2.0 into that representation.Source: §V · p. 5
  • The Placement Optimizer implements qubit-layout search, and the Node-count Selector implements computational-resource selection.Source: §V · p. 5
  • The Simulator Connector links the modules to the target simulator; only this module communicates with QuEST and DMR, so porting requires replacing it.A standalone calibrator writes calib.csv for the Node-count Selector, and the dashed DMR resize path is available with malleability support.Source: §V · p. 5

A. Circuit Representation

QuCSLO keeps a circuit as an ordered, execution-independent gate description, allowing circuits to be built through either its C++ API or OpenQASM import. Its placement optimizer then searches for a qubit permutation that minimizes communication cuts without changing simulator internals.

A. Circuit Representation

  • The Circuit type stores an ordered gate sequence without applying gates or encoding node count and layout, leaving the full circuit available for analysis before state-vector creation.Qubits are indexed for use by the placement optimizer and communication model.Source: A. Circuit Representation · p. 5

B. Circuit Import

  • Circuits can be constructed programmatically with the C++ Circuit API or imported from OpenQASM 2.0 into the same Circuit type.The API example builds a Bell-state preparation, and imported circuits use the same Executor interface.Source: B. Circuit Import · pp. 5–6
  • The parser resolves register and gate declarations, translates supported operations into the internal gate representation, and rejects unsupported or non-unitary constructs.The common representation lets downstream placement, node-count selection, and execution behave identically for API-built and imported circuits.Source: B. Circuit Import · pp. 5–6

C. Placement Optimizer

  • For a circuit and selected global-qubit count k, the Placement Optimizer returns a logical-qubit permutation minimizing the communication cut.It builds a weighted qubit graph from non-diagonal gates and uses simulated annealing from the identity layout; dispatch-time relabeling avoids modifying the simulator.Source: C. Placement Optimizer · p. 6

D. Node-Count Selector

The Node-count Selector combines circuit and cluster measurements to choose resources for a communication-efficiency target, while the Simulator Connector applies the chosen layout and runs the circuit. Evaluation uses synthetic circuits and a restricted QASMBench subset on a 64-node system.

D. Node-Count Selector

  • The selector evaluates circuit statistics and calibrated cluster parameters across feasible k values, then recommends the efficient count for a user-defined communication-efficiency degradation threshold.The calculation includes gate count, cutmin(k), Wcomm(k), and calibrated latency and bandwidth ratios; each evaluated k triggers placement optimization.Source: D. Node-Count Selector · p. 6
  • Calibration measures the same gate locally and distributed, using their execution-time difference as communication overhead to derive cluster-specific parameters.The calibrator evaluates a Hadamard gate and calculates Tcomm(k), a(k), and b(k) for different qubit counts.Source: D. Node-Count Selector · p. 6

E. Simulator Connector

  • The Executor applies the layout by relabeling qubits, configures the requested process count, and invokes the simulator through a uniform connector interface.QuCSLO uses QuEST here; with malleability support, it can also reconfigure process and node counts at runtime.Source: E. Simulator Connector · pp. 6–7
  • For resizing, the Executor checks the current allocation against the model’s target and asks DMR to reconfigure when they differ.The running process is replaced, and the new process reconstructs its Executor and distributed Qureg.Source: E. Simulator Connector · p. 7

VI. EVALUATION

  • Experiments use up to 64 MN5 General-Purpose Partition nodes, and the QASMBench Large-scale subset is restricted to 28–34 qubits by cluster memory limits.Circuits requiring unsupported QASM constructs are excluded.Source: §VI · p. 7
  • Eight synthetic circuits probe varied communication patterns, including local chain and carry interactions, sparse random coupling, and communication-heavy QFT blocks.Source: §VI · p. 7
  • The synthetic set also includes SWAP routing, a layout-invariant QFT-epcc control, and Comm cliff, whose communication becomes global beyond a fixed node count.Together, the circuits span reducible to structurally irreducible communication patterns.Source: §VI · p. 7

A. Qubit Layout Optimization Study

Analytical evaluations compare identity and optimized layouts on synthetic and QASMBench circuits at 2 and 16 nodes. Optimized layouts reduce communication cuts in many circuits, but gains depend on circuit structure and may be absent when qubits are involved nearly uniformly.

1) Analytical Results:

  • At 16 nodes, identity QAOA-sparse cut rises from 76 to 94 between N = 30 and N = 32, while its optimized cut stays 16 and reduction rises from 78.9% to 83.0%.Seven other synthetic circuits have identical reduction patterns at both qubit counts because their hand-designed interaction topologies are invariant to total qubit count.Source: 1) Analytical Results · p. 7, Table I · p. 8
  • Optimized layouts reduce communication cuts in many synthetic and QASMBench circuits, but control and uniformly coupled circuits can show no gain.The comparisons cover synthetic 30- and 32-qubit circuits and large-scale QASMBench circuits at 2 and 16 nodes.Source: Table I · p. 8, Table II · p. 8, 1) Analytical Results · p. 8
  • The adder achieves cutmin(k)=0 at both node counts; the 1D chain also reaches zero for k=1, but at k=4 only partially reduces its cut from 16 to 12.Source: 1) Analytical Results · p. 8
  • Ising Trotter reduces exactly 8 communication events at both node counts: 13 to 5 at k = 1 and 52 to 44 at k = 4.Its relative impact grows because the identity baseline cut increases with k.Source: 1) Analytical Results · p. 8
  • QFT circuits show no layout gain because every qubit has identical communication weight; adder n28 benefits at k = 4, but its transpiled counterpart does not.The remaining QASMBench circuits show consistent communication reductions at both node configurations.Source: 1) Analytical Results · p. 8, Table II · p. 8

2) Performance Analysis:

Across synthetic and QASMBench circuits, layout speedups vary with circuit structure and node count: some circuits benefit substantially, while circuits with unchanged communication cuts remain at 1.00×.

2) Performance Analysis:

  • 1.87× at N = 30 and 2.09× at N = 32 were the largest synthetic speedups, for QAOA-sparse; the compute-heavy Ising Trotter gained 1.13–1.14×.The QFT-epcc and Comm cliff controls stayed at 1.00× at both sizes.Source: Table III · p. 8, 2) Performance Analysis · p. 8
  • At N = 30, QAOA-sparse and Draper adder peaked at 1.87× and 1.53× at 16 nodes, then approached 1.00× at 32 and 64 nodes.At N = 32, their speedups continued growing through the 64-node test range, reaching 2.27× and 1.65×, respectively.Source: 2) Performance Analysis · p. 8, Table IV · p. 9
  • 2.28× was the measured speedup for bv n30 at two nodes, but cut reduction did not predict speedup uniformly at 16 nodes.At k = 4, adder n28 reduced its cut by 30% but gained 1.05×; dnn n33 transpiled and ising n34 transp. reduced cuts by 21.9% and 16.7% and each gained 1.07×. The qft n29 pair remained at 1.00× because placement left their cuts unchanged.Source: 2) Performance Analysis · p. 9
  • QASMBench speedups varied by circuit and node count: bv n30 variants stayed comparatively strong through 8 nodes, while knn n31 transp. kept growing through 32 nodes before declining at 64.The QFT-like circuits qft n29 and qft n29 transp. remained at 1.00× throughout.Source: Table VI · p. 9, 2) Performance Analysis · p. 9

B. Node-count Efficiency Study

The study evaluates a node-count efficiency model alongside layout scaling, because more nodes can increase memory and parallelism while also adding communication and synchronization overhead. Model accuracy and resource choices depend on operating within QuEST’s distributed range.

B. Node-count Efficiency Study

  • More nodes can increase memory and parallelism but also communication and synchronization overhead, so the largest allocation need not be fastest or most resource-efficient.For bv n30, the optimized configuration stayed closer to linear scaling than the identity-layout baseline.Source: B. Node-count Efficiency Study · p. 9
  • The model predicts degradation using only the circuit and its optimized layout, without preliminary execution or runtime measurements.It predicts deviation from linear scaling relative to each circuit’s smallest feasible node count, usually one node unless memory prevents it.Source: B. Node-count Efficiency Study · pp. 9–10
  • When predicted and measured curves fall in the same threshold band, the selected node count is the largest feasible k that satisfies the degradation constraint.Table VII summarizes agreement for the synthetic and QASMBench circuit sets.Source: B. Node-count Efficiency Study · p. 10, Table VII · p. 10
  • At τ = 15%, QFT-epcc was predicted at 11.1% degradation versus 17.5% measured at 16 nodes; at τ = 30%, Cuccaro was predicted at 18.2% versus 38.5% measured at 4 nodes.Neither circuit was misclassified at both thresholds: Cuccaro measured 10% at 2 nodes under τ = 15%, while QFT-epcc stayed below τ = 30% throughout the measured range.Source: B. Node-count Efficiency Study · p. 10
  • 13–25 percentage points was the model’s underestimation of bv n30 degradation at 8 and 16 nodes, but measured degradation was already 107–176%, excluding those choices under both studied thresholds.At 2 and 4 nodes, prediction error was approximately 1–5 percentage points.Source: B. Node-count Efficiency Study · p. 10
  • −5.4% measured degradation versus 6.1% predicted at qft n29’s 8-node distribution floor; at 16 nodes, measured degradation jumped to 1,508%, beyond the model’s applicable regime.For adder n28, predicted and measured degradation at its 4-node floor were 22.2% and 21.3%; beyond it, measured degradation reached 693.5% at 8 nodes.Source: B. Node-count Efficiency Study · p. 10

C. Automatic Resource Adjustment

Automatic resource adjustment selects node counts against a user-defined performance-degradation threshold, balancing execution time and node-hour cost. On two representative circuits, it avoids excessive allocation, with outcomes that depend on the circuit and the comparison strategy.

C. Automatic Resource Adjustment

  • The automatic strategy avoids both minimum-node allocation, which can prolong execution, and maximum-node allocation, which can raise QuEST runtime after the distribution floor.A performance-driven alternative sweeps available node counts for the fastest execution, but incurs the cost of the preliminary sweep.Source: C. Automatic Resource Adjustment · pp. 10–11
  • The approach automates configuration selection by choosing, before execution, the largest node count whose predicted degradation stays below a user-defined threshold τ, allowing users to control the trade-off between performance and resource efficiency.For the automatic configuration, the model selects keff = 1, corresponding to two nodes, and applies the optimized qubit layout.Source: C. Automatic Resource Adjustment · p. 11
  • For bv n30, the automatically selected configuration was 3.19× slower than performance-driven execution but reduced node-hour cost by a factor of 2.74; versus greedy, it ran approximately 3% faster at 36× lower computational cost.Source: Table VIII · p. 12, C. Automatic Resource Adjustment · p. 12
  • For vqe uccsd n28, performance-driven and automatic configurations use four nodes and achieve about 74% lower wall time and 98% lower node-hour cost than greedy allocation.The greedy 64-node allocation exceeds the circuit's distribution floor; its memory limit is reached at kmem = 2, or four nodes.Source: Table IX · p. 12, C. Automatic Resource Adjustment · p. 12
  • For bv n30, layout optimization and reconfiguration add 1.375 s—about 20% of the 6.901 s total wall time.The evaluation compares automatic adjustment with static allocations chosen using user-based strategies on bv n30 and vqe uccsd n28.Source: C. Automatic Resource Adjustment · pp. 11–12
  • For vqe uccsd n28, the optimized layout changes little at four nodes, so placement adds limited benefit; automatic selection instead avoids the preliminary sweep and excessive allocation.The automatic configuration has lower execution time and wall time than the performance-driven configuration even after its 9.06 s optimization and reconfiguration overhead.Source: C. Automatic Resource Adjustment · p. 12

VII. DISCUSSION

The discussion identifies platform-specific communication modeling and hardware calibration as limitations, while pointing to possible integration with persistent services and resource managers. The conclusion reports communication-cut optimization and predictive node selection, with experimental speedups and degradation-prediction accuracy.

VII. DISCUSSION

  • Combining dynamic resource resizing with persistent simulation services could allow virtual QPUs to scale with workload or real-time utilization.Source: §VII · p. 12
  • For resource managers that route circuits across simulators and QPUs, the placement and node-count models could automate configuration after a classical simulator is selected.The discussion says this could eliminate manual provisioning and circuit-specific preliminary sweeps.Source: §VII · p. 12
  • QuEST-derived communication costs limit the model's direct portability: simulators with different data-exchange patterns need a revised communication framework.The discussion identifies Wcomm(k) as derived from QuEST's state-vector communication strategy.Source: §VII · p. 12
  • The model's a(k) and b(k) parameters were calibrated on MN5, so another cluster requires recalibration using the provided target-machine script.Source: §VII · p. 12

VIII. CONCLUSION

  • Experiments on synthetic and real-world circuits show over 2× runtime speedup, while the prediction model reaches 83–92% accuracy against measured degradation.The conclusion presents placement optimization and threshold-based node-count selection as the paper's two main approaches.Source: §VIII · p. 12
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