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ReSAFT: An Efficient Stuck-at Fault-Tolerant Scheme for ReRAM-based Process-in-Memory Accelerators

Aniseh Dorostkar, Hamed Farbeh, Hamid R. Zarandi

arXiv:2610.09999v1cs.AR

TL;DR

Conventional redundancy schemes are poorly suited to analog ReRAM crossbars, where a faulty cell can compromise a VMM column. ReSAFT combines redundant rows and columns with fault-aware mapping and multi-objective optimization; NSGA-II identifies semi-optimal trade-off solutions rather than one best design.

  • Problem

    Conventional redundancy schemes designed for digital memory-centric applications are not directly applicable to analog ReRAM PIM, where a faulty cell can compromise an entire VMM column.

    Source: §1 · p. 2

  • Method

    ReSAFT combines redundant rows and columns with fault-aware mapping and remapping, and uses NSGA-II to select row and column counts across multiple objectives.

    Source: §1 · p. 2, §4.4 · p. 15, §5 · p. 17

  • Results

    NSGA-II yields a set of semi-optimal row and column solutions covering the objective space, rather than one best solution.

    Source: §4.4 · p. 15

  • Takeaways & Limitations

    The proposed architecture is described as mitigating both SaH and SaL faults with minimal design-overhead impact and without sacrificing inference accuracy.

    Source: §5 · p. 16

    FADM does not provide high fault coverage, although it significantly improves reliability with negligible hardware overhead.

    Source: §3.2 · p. 12

Abstract

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Analog ReRAM-based process-in-memory (PIM) accelerators provide high parallelism and energy efficiency for deep convolutional neural networks (CNNs) inference. However, their susceptibility to permanent faults, such as stuck-at high (SaH) and stuck-at low (SaL) resistance states, poses a major challenge by permanently corrupting the CNN weights mapped to conductance values of ReRAM cells and degrading inference accuracy, which leads to system unreliability in safety-critical applications. In this paper, we propose a fault-tolerant scheme for analog ReRAM-based PIM accelerators to tackle stuck-at faults (SAFs) with minimal redundancy overhead to recover classification accuracy degradation. The proposed scheme contains a redundancy-based hardware solution alongside fault-aware mapping method for ensuring reliable analog computation in ReRAM crossbar. We analyze the impact of varying number of redundant rows and columns on accuracy and design metrics. Subsequently, a multi-objective optimization (MOO) problem is formulated and solved to efficiently determine the number of redundant rows and columns, considering trade-offs among various design metrics. Furthermore, a fault-aware weight mapping is proposed for dual-crossbar structures to further compensate for the accuracy degradation caused by SAFs. Simulation results show that, for the SimpleNet model using the MNIST dataset, the inference accuracy is recovered by approximately 22.39%, on average, across four configurations of optimal solutions, each offering a trade-off between reliability and area, energy consumption, and latency overheads. The mean-time-tofailure (MTTF) improves by about 61x on average compared to the baseline. These selected configurations also reduce energy and area overheads by 32%, on average, in comparison to row-only and column-only configurations.

1. Introduction

Analog ReRAM-based PIM accelerators offer efficient parallel CNN computation, but permanent stuck-at faults can corrupt mapped weights and impair inference. ReSAFT combines mixed row-and-column redundancy, multi-objective sizing, and fault-aware mapping to balance accuracy, reliability, and overhead.

1. Introduction

  • Conventional redundancy schemes are too coarse for analog PIM: disabling entire rows or columns can waste area, power, and latency, while a faulty cell can compromise a whole VMM column.Existing hardware redundancy solutions designed for digital memory-centric applications are not directly applicable to analog ReRAM-based PIM.Source: §1 · p. 2
  • ReSAFT combines redundant rows and columns with mapping and remapping methods to address stuck-at faults while trading off reliability, cost, and CNN classification accuracy.The design also evaluates the effects of redundancy choices on energy, area, and latency.Source: §1 · p. 2
  • Redundant columns tolerate both SaL and SaH faults, while redundant rows tolerate SaH faults through current adjustment, reducing area overhead relative to column-only methods.The combined architecture uses both redundancy types rather than relying exclusively on rows or columns.Source: §1 · p. 2
  • A multi-objective optimization problem selects redundant row and column counts by trading off MTTF, energy, latency, and area subject to a classification-accuracy constraint.The optimization determines an adequate hardware configuration for the crossbar.Source: §1 · p. 2
  • Fault-aware mapping assigns faulty cells to suitable redundant cells based on fault type and location, while runtime dual-crossbar weight remapping addresses remaining faults.The dual-crossbar method remaps conductance values across positive and negative crossbars to compensate for SAF-related accuracy degradation.Source: §1 · p. 2

2. Preliminaries and Related Work

The preliminaries describe CNN computations and how ReRAM crossbars store and execute them as analog VMMs. The related-work review identifies limitations of existing software and hardware fault-tolerance approaches and motivates their integration.

2.1. Convolutional Neural Networks

  • CNN fully connected layers compute weighted input sums with bias and an activation function, while convolutional layers apply kernels to input feature maps.Trainable weights, kernels, and biases occur mainly in convolutional, fully connected, and BatchNorm layers.Source: §2.1 · p. 3

2.2. ReRAM-based PIM Accelerators

  • ReRAM crossbars encode matrix elements as conductances and apply input vectors as word-line voltages, producing VMM outputs as bit-line currents.Learning parameters are formatted, mapped to conductance values, and placed across crossbars, tiles, and memory banks.Source: §2.2 · p. 3
  • Because ReRAM conductance is nonnegative, signed weights use separate positive and negative crossbars with differential encoding.The corresponding cell conductances depend on the weight sign, with the paired cell set to gmin.Source: §2.2 · pp. 3–4

2.3. Related Work

  • Software fault-tolerance approaches include remapping, retraining, online training, and matrix transformations, but can add computation or memory overhead and lose effectiveness under high fault rates or device variation.Retraining can require many write operations, potentially accelerating ReRAM wear-out.Source: §2.3 · p. 4
  • Hardware approaches use redundancy or peripheral-circuit changes, but ECC, replication, and coarse row-or-column redundancy can incur substantial overhead or inefficiency in analog PIM.The review motivates combining hardware redundancy with software methods to balance reliability, overhead, and accuracy.Source: §2.3 · pp. 4–5

3. ReSAFT: Fault-Tolerant Scheme for Analog ReRAM-Based PIM Accelerator

ReSAFT combines a redundancy-based ReRAM crossbar with runtime fault-aware mapping and remapping. Its design-time optimization selects row and column redundancy, while runtime methods use the identified fault map and handle faults left by the architecture.

3. ReSAFT: Fault-Tolerant Scheme for Analog ReRAM-Based PIM Accelerator

  • ReFTC combines redundant rows and columns, with design-time multi-objective optimization selecting their counts across reliability, MTTF, energy, latency, area, and CNN accuracy.At runtime, RMap uses each crossbar’s identified fault map to map faulty cells to redundant resources and schedule their input voltages.Source: §3 · p. 5
  • FADM complements ReFTC by remapping faulty-cell conductance values to corresponding dual cells for faults ReFTC does not tolerate, including faults in redundant rows and columns.FADM operates across the positive and negative ReRAM crossbars at runtime.Source: §3 · p. 5
  • Figure 4 presents the overall workflow of the ReSAFT scheme.The described workflow includes design-time optimization and runtime mapping and remapping.Source: Figure 4 · p. 5, §3 · p. 5

3.1. ReFTC: Redundancy-Based Fault-Tolerant ReRAM Crossbar Architecture

ReFTC adds redundant rows, columns, and auxiliary cells to tolerate faults in a ReRAM crossbar. Combining row and column redundancy can use fewer resources for different fault patterns, with additional cycles trading latency for fewer rows.

3.1. ReFTC: Redundancy-Based Fault-Tolerant ReRAM Crossbar Architecture

  • Combining rows and columns can use fewer redundant resources than either alone when faults cluster differently across rows and columns.A single redundant row can handle multiple faults in one row, while a single redundant column can handle multiple faults in one column.Source: §3.1 · p. 5
  • One redundant row can tolerate faults across different rows through additional cycles, but all faulty columns require corresponding redundant columns for tolerance.More redundant rows reduce the time overhead; too few redundant columns can leave faults untolerated even with additional cycles.Source: §3.1 · pp. 5–6
  • ReFTC adds r redundant rows, c redundant columns, and r × c auxiliary cells to a 1T1R crossbar to tolerate faults in the main array and redundant columns.Auxiliary cells replace faults in redundant columns.Source: §3.1 · p. 5, Figure 5 · p. 6

3.1.1. Mapping and Scheduling of Faulty Cells to Redundant Rows and Columns

RMap detects faults and maps them to redundant columns, rows, or auxiliary cells, prioritizing columns for SaL faults and scheduling row mappings across cycles. Redundant resources are limited, so remaining faults are addressed with FADM.

3.1.1. Mapping and Scheduling of Faulty Cells to Redundant Rows and Columns

  • Faults in redundant columns can be replaced with auxiliary cells, while unused auxiliary cells are programmed to gmin.Faults in redundant rows can often be tolerated by mapping and scheduling across the remaining redundant rows.Source: §3.1.1 · p. 6
  • For SaH faults, redundant-row conductances are configured so their current combines with main-crossbar current to match the golden current.The method calculates fault-tolerated column current and the redundant-row conductance for SaH faults.Source: §3.1.1 · p. 6
  • Redundant columns handle SaL faults, while redundant rows primarily handle distributed SaH faults; FADM further mitigates faults that exceed the available redundancy.The framework provides bounded fault tolerance depending on the design-time redundancy budget and FADM remapping capability.Source: §3.1.1 · p. 6
  • RMap remaps an entire row or column when its fault count exceeds a threshold, prioritizing redundant columns for SaL faults and mapping SaH faults to rows when the count permits.SaH mappings preserve column alignment; unused redundant-row columns are deactivated and programmed to gmin.Source: §3.1.1 · pp. 6–7
  • When faults from different rows share a redundant row, RMap schedules different input voltages across cycles and prioritizes columns to reduce serialization.The algorithm sorts rows by SaH fault count and repeatedly assigns the row with the most unmapped faults to a cycle.Source: §3.1.1 · p. 7
  • In the 10 × 10 example with three redundant rows and one redundant column, column remapping is followed by row mapping across two scheduled cycles.The example includes ten SaH faults and three SaL faults; the first cycle applies V5, V8, and V2, and the second applies V4 and V3.Source: Figure 6 · p. 7, §3.1.1 · p. 7
  • Area and latency overheads range from O(N) in the worst case to O(1) in the best case, depending on the redundant row and column counts.Source: §3.1.1 · p. 7

3.1.2. Determining Number of Redundant Rows and Columns

The section analyzes how redundant rows and columns affect ReRAM-crossbar reliability, energy, latency, area, and CNN accuracy to guide redundancy allocation. Its models and results expose trade-offs among these metrics and the accuracy constraint.

3.1.2. Determining Number of Redundant Rows and Columns

  • The optimization selects row and column redundancy to maximize MTTF while minimizing energy, latency, and area, subject to an accuracy threshold.The section analyzes the effects of redundancy allocation on these design metrics and CNN classification accuracy.Source: §3.1.2 · pp. 7–8

3.1.2.1 Reliability of ReRAM Crossbar

  • MTTF rises as redundant rows and columns increase, with larger gains from columns because they tolerate both SaH and SaL faults while rows tolerate SaH faults.The analytical model and Monte Carlo simulation show consistent trends; their comparison has 19.58% mean relative error and a 0.9569 Pearson correlation coefficient.Source: §3.1.2.1 · pp. 8–9, Figure 7 · p. 9

3.1.2.2 Energy Consumption

  • The energy model sums read and write operation energy with idle leakage, while its read-power approximation assumes identical cell resistance and row voltage.During inference, write operations are typically much fewer than reads, so most system power and energy comes from reads.Source: §3.1.2.2 · p. 9

3.1.2.3 Latency

  • In a 256 × 256 crossbar, fewer than 16 redundant rows require more than 16 additional VMM cycles, whereas more than 64 rows add fewer than four.This is a worst-case latency bound; actual overhead depends on redundancy, fault distribution, and mapping efficiency.Source: §3.1.2.3 · pp. 9–10, Figure 9 · p. 10

3.1.2.4 Area

  • Redundant rows, columns, and their intersections add cell area, and remapping logic contributes additional overhead beyond the memory cells.The redundant cells occupy the same per-cell area as main-crossbar cells.Source: §3.1.2.4 · p. 10, Figure 10 · p. 10

3.1.2.5 Accuracy

  • To avoid exhaustive evaluation of over 65,000 row-column combinations, the accuracy approximation averages separate row and column models evaluated at total redundancy r + c.The approach requires 514 simulations rather than over 65,000 and is described as maintaining acceptable estimation error.Source: §3.1.2.5 · p. 10

3.1.3. Optimization Problem

The optimization selects redundant-row and redundant-column counts through multi-objective optimization, balancing reliability against energy, area, and latency while constraining classification-accuracy deviation.

3.1.3. Optimization Problem

  • The optimization minimizes energy, latency, and area while maximizing the minimum MTTF across crossbars.The design therefore balances conflicting objectives rather than optimizing a single metric.Source: §3.1.3 · p. 11
  • Accuracy deviation between the fault-tolerant accelerator and baseline must remain below a model- and application-dependent threshold ε.The row and column redundancy ranges are [0, n] and [0, m], respectively.Source: §3.1.3 · p. 11
  • System area is expressed as the number of crossbars multiplied by the area per crossbar.The optimization formulates system area as Ncrossbar × Areacrossbar.Source: §3.1.3 · p. 11

3.2. FADM: Fault-Aware Weight Mapping in Dual ReRAM Crossbar

FADM uses the complementary positive and negative crossbars to remap conductances around some stuck-at faults. Its coverage is limited: some single-fault cases are tolerated, but double faults and other states are not.

3.2. FADM: Fault-Aware Weight Mapping in Dual ReRAM Crossbar

  • Four of the nine dual-crossbar fault cases are tolerable single faults, while four simultaneous double-fault cases are intolerable.FADM exploits the complementary structure of positive and negative crossbars to handle the tolerable cases.Source: §3.2 · p. 11
  • The fault-aware conductance values must remain within [gmin, gmax], and the mapping equations calculate values for cells affected by faults.The original values are for fault-free operation; the fault-aware values are programmed when faults occur.Source: §3.2 · p. 11
  • Whether a fault is tolerable depends on the weight sign and the fault type and location; simultaneous faults in corresponding cells cannot be tolerated.The passage also identifies specific single-fault states that are intolerable, including SaH in the positive crossbar for a positive weight.Source: §3.2 · p. 11
  • FADM remaps faulty cells to conductance values in corresponding opposite-crossbar cells to tolerate selected SaL and SaH faults.The example illustrates SaL tolerance in the positive crossbar and SaH tolerance in the negative crossbar.Source: §3.2 · p. 11, Figure 11 · p. 12
  • FADM does not provide high fault coverage, but it improves reliability with negligible hardware overhead and is intended to complement ReFTC or other methods.The stated aim of combining methods is to improve accuracy while reducing hardware and software overhead.Source: §3.2 · p. 12

4. Evaluation and Analysis

Evaluation across CNN models examines redundant crossbar rows and columns, dual-crossbar fault-aware mapping, and Pareto-optimized configurations. Results show accuracy recovery alongside reliability and overhead trade-offs.

4.1. Experiment Setup

  • The evaluation uses SimpleNet, LeNet5, VGG8, VGG11, and ResNet18, modeling ReRAM devices with VTEAM and estimating architecture metrics with MNSIM2.0.SimpleNet and LeNet5 use MNIST; VGG8 and ResNet18 use CIFAR-10. The crossbar configuration is a 256 × 256 dual-crossbar tile.Source: §4.1 · p. 12

4.2. Classification Accuracy of CNN Models on ReFTC Architecture

  • Redundant columns provide larger maximum accuracy increments than rows—17.49% versus 13.36% for SimpleNet and 45.77% versus 38.01% for LeNet5.Rows reduce worst-case VMM latency overhead as row count increases; columns tolerate both SaH and SaL faults and add no latency overhead. Accuracy estimates use quadratic row fits and logarithmic column fits, with average estimation errors of 5.23% for SimpleNet and 4.78% for LeNet5.Source: §4.2 · p. 13, Figure 12 · p. 13, Figure 13 · p. 14

4.3. Evaluation of Fault-Aware Weight Mapping in Dual ReRAM Crossbar (FADM)

  • FADM reduces summed weight variation by 82% on average versus conventional mapping, while tolerating approximately 50%–60% of fault cases.The tolerable ratio reaches 60.96% at a 20% fault rate; symmetric double faults can compensate in the differential crossbar.Source: §4.3 · p. 14, Table 3 · p. 14, Figure 15 · p. 15
  • FADM increases classification accuracy by averages of 17.04% for SimpleNet, 19.9% for LeNet5, 17.48% for VGG8, 14.91% for VGG11, and 21.16% for ResNet18.The evaluation injects varying numbers of SaH and SaL faults.Source: §4.3 · p. 14, Figure 16 · p. 15
  • FADM combined with redundancy yields average accuracy of 89.17% and 89.02% for LeNet5, and 95.02% and 95.55% for SimpleNet, across row- and column-varying configurations.The passage reports increases even where small row or column counts alone did not improve accuracy.Source: §4.3 · p. 15, Table 4 · p. 15

4.4. MOO Problem Analysis

  • NSGA-II identifies a Pareto set rather than one best row/column count, and increasing ε yields more semi-optimal solutions.The example design space has 66,049 possible solutions; designers select among the Pareto choices according to application requirements.Source: §4.4 · p. 15, Table 5 · p. 15
  • A configuration with 87 redundant rows and 19 columns improves MTTF 56×, raises energy consumption 43%, and reduces area and energy overheads about 28% versus row-only or column-only configurations.Its latency overhead increases about 3×; column-only redundancy achieves higher MTTF but has more area and energy overhead.Source: §4.4 · pp. 15–16
  • 21.7% total accuracy enhancement is achieved for SimpleNet by optimized ReFTC configurations combined with FADM.Faults lower baseline accuracy from 99.33% to 75.66%; ReFTC contributes an average 18.71% improvement and FADM adds 2.98%.Source: §4.4 · p. 16

5. Conclusion

The conclusion presents ReSAFT as a fault-tolerant scheme combining crossbar redundancy with mapping and input scheduling. Across four optimized SimpleNet configurations, it reports accuracy improvement while balancing reliability and design overhead.

5. Conclusion

  • ReSAFT combines redundant rows and columns with adaptive mapping, input-voltage scheduling, and fault-aware weight mapping in positive and negative crossbars.The architecture targets both SaH and SaL faults while aiming to limit design overhead and preserve inference accuracy.Source: §5 · pp. 16–17
  • 22.39% inference accuracy improvement is reported on average for SimpleNet across four Pareto-derived configurations.The conclusion describes these configurations as fulfilling the optimization problem’s objectives.Source: §5 · p. 17
  • The conclusion positions ReSAFT for safety-critical and high-precision deep-learning applications.It also reports evaluation of MTTF, energy, latency, area, and classification accuracy.Source: Figure 20 · p. 16, §5 · p. 17
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