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Low-Complexity SVD-Based Precoding over Zero-Padded ISI Channels

Shuiyin Liu, Amin Sakzad

arXiv:2610.12784v1cs.ITmath.IT

TL;DR

Conventional equalization can sacrifice detection performance, while trellis-based methods motivate a lower-complexity alternative. The paper uses zero padding to enable FFT-based SVD processing and adaptive signaling with soft decoding. The proposed scheme has comparable high-SNR FER to SOVA, while both soft-decoding schemes outperform the RS-based hard-decoding architecture.

  • Problem

    Conventional TX-FFE/RX-DFE can sacrifice detection performance, and trellis-based detection motivates a fast receiver architecture.

    Source: §I · p. 1

  • Method

    A single zero-padding symbol exposes a closed-form SVD structure for FFT-based precoding and equalization, with parallel subchannels for adaptive PAM, power allocation, and exact soft-information computation.

    Source: §I · p. 2, §III · p. 3, B. Exact Finite-Alphabet LLR Computation · p. 5

  • Results

    At high SNR, the proposed SVD-based transceiver achieves comparable FER to SOVA, and both soft-decoding schemes substantially outperform the RS-based hard-decoding architecture.

    Source: §V · p. 5

  • Takeaways & Limitations

    The framework provides a low-complexity foundation for large-PAM ISI transceivers, using O(n log n) complexity and O(n) memory.

    Source: §VI · p. 5

    TX-FFE trades ISI suppression for SNR loss, and DFE decision errors can propagate to subsequent decisions.

    Source: 2) RX-DFE · p. 3

Abstract

from arXiv · show

We propose a low-complexity SVD-based transceiver for zero-padded memory-$1$ ISI channels. Appending a single zero-padding symbol to an $n$-symbol block yields an $n\times(n-1)$ channel matrix with an \emph{exact symmetric tridiagonal Toeplitz Gram matrix}. This structure provides closed-form singular values and vectors, enabling exact SVD precoding and equalization via FFTs without explicitly forming dense SVD matrices. The resulting implementation has $O(n\log n)$ complexity and incurs only a $1/n$ rate penalty. The resulting parallel scalar subchannels enable joint adaptive PAM and power allocation for SER minimization, followed by exact soft-information computation for LDPC decoding. At comparable code rates near $0.945$, simulations show that our proposed scheme outperforms a conventional TX-FFE/RX-DFE system with hard-decision Reed-Solomon (RS) decoding by approximately $5$ dB at FER $10^{-5}$. At high SNR, it achieves nearly the same FER performance as a SOVA-based receiver with LDPC decoding, while replacing trellis-based detection with fast SVD precoding and exact scalar soft-output computation.

I. INTRODUCTION

Higher-order PAM and conventional equalization motivate an ISI transceiver that combines low complexity with adaptive signaling and soft decoding. The proposed zero-padded memory-1 channel structure enables exact FFT-based SVD processing and parallel subchannels.

I. INTRODUCTION

  • TX-FFE can divert transmit power from information, while DFE decision errors can propagate and produce burst errors that distort soft-decoder reliability.These effects can limit decoding performance for high-order PAM.Source: §I · p. 1
  • Trellis-based MLSD and SOVA have higher computational overhead, motivating a receiver architecture with O(n log n) complexity.For memory-1 ISI, MLSD complexity scales as O(nM^2); SOVA adds traceback and soft-output update overhead.Source: §I · p. 1
  • Jointly adapting PAM order and power allocation addresses unequal channel gains, whereas conventional schemes typically use fixed PAM order and equal power.The proposed architecture targets improved decoding performance with O(n log n) complexity and O(n) memory.Source: §I · pp. 1–2
  • A single zero-padding symbol yields a structured channel with a closed-form SVD, enabling exact FFT-based precoding and equalization at O(n log n) complexity and O(n) memory.The approach avoids explicitly forming or storing dense singular-vector matrices.Source: §I · p. 2

A. Memory-1 ISI Channel

  • The memory-1 ISI channel is modeled over n uses as a structured linear transformation, providing the basis for low-complexity precoding and equalization.Its input-output relation is y_i = x_i + αx_{i−1} + z_i, with x_0 = 0.Source: A. Memory-1 ISI Channel · p. 2

1) TX-FFE:

The TX-FFE baseline uses a lower-triangular Toeplitz filter whose coefficients cancel initial ISI terms, leaving a higher-order residual.

1) TX-FFE:

  • The fixed-PAM baseline uses a common PAM order and equal power allocation across channel uses.Its FFE output is normalized to satisfy the total transmission-power constraint.Source: 1) TX-FFE · p. 2
  • A t-tap FFE uses t ISI-canceling taps plus the main tap, with coefficients f_k = (−α)^k.The filter is represented by a lower-triangular Toeplitz matrix.Source: 1) TX-FFE · p. 2
  • The t-tap FFE cancels the first t ISI terms, leaving only the (t + 1)-th-order residual ISI.The resulting effective channel is denoted ˆH_t = HF_t.Source: 1) TX-FFE · pp. 2–3

2) RX-DFE:

The section contrasts successive DFE cancellation and trellis-based sequence detection with a structured SVD transceiver designed to retain soft information at lower complexity.

2) RX-DFE:

  • The RX-DFE cancels residual post-cursor ISI using previous hard decisions, reducing the current channel to AWGN when all prior decisions are correct.An erroneous decision can propagate through successive interference cancellation and degrade detection performance.Source: 2) RX-DFE · p. 3

C. ML-Type Detectors: MLSD and SOVA

  • MLSD jointly detects the PAM sequence by exploiting residual ISI, and finite-memory optimization can be represented by a trellis solved with the Viterbi algorithm.Trellis states are determined by previous transmitted symbols.Source: C. ML-Type Detectors: MLSD and SOVA · p. 3
  • For memory-1 ISI, MLSD and SOVA require O(nM^2) branch-metric computations, with trellis storage growing as O(M^L).The general memory-L case requires O(nM^(L+1)) branch-metric computations and O(M^L) state-metric storage.Source: C. ML-Type Detectors: MLSD and SOVA · p. 3

D. Problem Statement

  • The design target is a finite-length ISI transceiver with O(n log n) complexity and O(n) memory that preserves soft information for channel decoding.It is motivated by the complexity of trellis detection.Source: D. Problem Statement · p. 3

III. FAST SVD-BASED EQUALIZATION FOR FINITE-LENGTH ISI

  • Single zero padding yields a closed-form singular system that supports exact SVD precoding and equalization in O(n log n) complexity and O(n) memory.The Gram matrix structure enables an FFT implementation without explicitly forming singular vectors.Source: §III · p. 3

A. Single-Zero Padding Transformation

A single zero-padding constraint produces a structured channel whose Gram matrix is symmetric tridiagonal Toeplitz, enabling a closed-form singular system with a rate loss of 1/n.

A. Single-Zero Padding Transformation

  • The physical transmitted vector appends one zero to the n−1 transmitted symbols, creating one redundant channel use per block.The resulting rate loss is 1/n and vanishes as n grows.Source: A. Single-Zero Padding Transformation · p. 3
  • The Gram matrix of the zero-padded channel is symmetric tridiagonal Toeplitz.This is the structural property used for the closed-form singular system.Source: A. Single-Zero Padding Transformation · p. 3
  • The resulting channel structure permits a closed-form characterization of the singular system and fast SVD-based precoding and equalization.The channel matrix is introduced after imposing a single zero-padding constraint.Source: A. Single-Zero Padding Transformation · p. 3

1) Closed-Form

The singular-system construction uses a DST-I basis for the right singular vectors and avoids explicitly forming either singular-vector matrix.

1) Closed-Form

  • The eigenvectors of the Gram matrix form the orthonormal DST-I basis.These are the right singular vectors of the channel.Source: 1) Closed-Form · p. 4
  • Because the DST-I matrix is symmetric, it supports the singular-value characterization stated in the section.The supplied passage introduces the singular values after noting this symmetry.Source: 1) Closed-Form · p. 4
  • Both singular-vector transformations can be implemented without explicitly forming U or V.Source: 1) Closed-Form · p. 4

C. FFT-Based Implementation of the DST-I Transform

The right singular-vector transform is an orthonormal DST-I, and its symmetry allows both forward and transpose transforms to use the same FFT construction. The following transceiver description applies this transform to scaled PAM symbols.

C. FFT-Based Implementation of the DST-I Transform

D. Fast SVD-Based Transceiver via FFT

1) Transmitter:

The transmitter applies a DST-I precoder and appends one zero to realize the structured channel's exact SVD without explicitly forming V. At the receiver, FFT-based projection separates the signal into parallel AWGN modes, with O(n log n) complexity and O(n) working memory.

1) Transmitter:

  • The DST-I precoder followed by a single appended zero realizes the exact SVD of the structured channel without explicitly forming V.The transmitted block is x = [ex^T, 0]^T, yielding y = UΛeu + z.Source: 1) Transmitter · p. 4

2) Receiver:

  • The receiver computes qj = yj + αyj+1 in O(n) operations, then projects the signal into n−1 exactly decoupled parallel AWGN modes.The projected noise remains white Gaussian with the same variance.Source: 2) Receiver · p. 4

E. Computation Complexity and Storage

IV. ADAPTIVE PAM, POWER ALLOCATION, AND LLR COMPUTATION

The parallel AWGN modes support adaptive PAM and power allocation alongside exact soft-information computation. The allocation procedure minimizes worst-case SER by assigning bits according to marginal power cost and selecting the target SER by bisection.

IV. ADAPTIVE PAM, POWER ALLOCATION, AND LLR COMPUTATION

  • The parallel AWGN subchannels support adaptive PAM and power allocation, followed by exact soft-information computation.The per-block transceiver has O(n log n) complexity and O(n) memory, dominated by the FFT-based SVD.Source: §IV · p. 4

A. Adaptive PAM and Power Allocation (APPA)

  • The APPA variant directly minimizes worst-case SER rather than maximizing mutual information as in Mercury/waterfilling (MWF).At high SNR, it imposes at least one bit on every SVD mode.Source: A. Adaptive PAM and Power Allocation… · pp. 4–5
  • Discrete convexity makes marginal bit costs non-decreasing, enabling greedy bit assignment by smallest marginal cost and bisection on the target SER.A min-heap yields the optimal allocation for a given target SER.Source: A. Adaptive PAM and Power Allocation… · p. 5

B. Exact Finite-Alphabet LLR Computation

The parallel-channel representation supports exact finite-alphabet soft-output demodulation, with LLRs computed for each bit of each mode. In simulations, the proposed scheme has comparable high-SNR FER to SOVA, while both soft-decoding schemes outperform the RS-based hard-decoding architecture.

B. Exact Finite-Alphabet LLR Computation

  • Exact LLR computation for each mode's Gray-labeled bit uses the finite-alphabet AWGN subchannels and can be implemented stably via log-sum-exp.Positive LLR values favor bit 0; negative values favor bit 1.Source: B. Exact Finite-Alphabet LLR Computation · p. 5

V. SIMULATION RESULTS

  • At high SNR, the proposed SVD-based transceiver achieves comparable FER to SOVA, and both soft-decoding schemes substantially outperform the RS-based hard-decoding architecture.Source: Figure 1 · p. 5, §V · p. 5

VI. CONCLUSION

  • The framework combines FFT-based SVD with adaptive PAM, power allocation, and exact LLR computation for finite-length ISI channels.Source: §VI · p. 5
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