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CktHGVAE: A Symmetric Design/State Heterogeneous Graph Variational Autoencoder for Transistor-level Analog/Mixed-signal Circuit Design and Analysis
Shigeyasu Uno
TL;DR
AMS circuit-design optimization is often limited to several tens of design parameters and requires many circuit-simulation trials. CktHGVAE treats design and state variables symmetrically in a graph variational autoencoder; the authors demonstrate reconstruction, latent-space optimization, and zero-shot transfer, suggesting it may serve as a basis for AMS circuit-design automation.
Problem
AMS circuit-design optimization is often limited to several tens of design parameters and requires many circuit-simulation trials.
Source: §1 · p. 1Method
CktHGVAE uses a graph variational autoencoder that treats circuit design variables and state variables symmetrically as inputs and outputs.
Source: §1 · p. 2Results
Zero-shot reconstruction of differential-pair voltage amplifiers reached median R2 values of 0.720–0.901, with poor fidelity in one of four scenarios.
Source: §5 · pp. 12–13Takeaways & Limitations
The demonstrations suggest that a simple GVAE treating design and state variables symmetrically can serve as a basis for AMS CMOS circuit design automation.
Source: §5 · p. 13The model does not produce state variables from design inputs in a single forward pass; conditioning on design variables instead requires latent-space search.
Source: §4 · p. 12
Abstract
from arXiv · showhide
We propose CktHGVAE, a heterogeneous graph variational autoencoder for transistor-level analog/mixedsignal CMOS circuits that takes not only design variables but also state variables as its inputs and outputs. With a single hyperparameter configuration without topology-specific tuning, comparison between model-generated and SPICE-simulated circuit operational states gives median R2 values above 0.9 for typical single-ended voltage amplifiers and the CMOS inverter, and 0.81-0.96 for differential amplifiers with larger datasets. Latent-space optimization in the PCA-reduced latent space with Bayesian optimization, evolutionary search, random search, and quasi-exhaustive search is demonstrated for a common-source voltage amplifier with NMOS input and resistive load, where the objective function is defined as a penalty for deviation from required circuit specifications. For each search strategy, 93.3 - 100% of all design candidates suggested by the model satisfy the required circuit specifications at the decoder output, and SPICE simulations verify that 90 - 100% of them indeed satisfy the requirements. The model pretrained on a batch of topologies can be transferred to unseen topologies without retraining at all, with zero-shot reconstruction median R2 values of 0.72-0.90 in three of four scenarios, including transfer from single-ended to differential topologies, although the transfer fidelity depends on the choice of pretraining topologies. Our demonstrations suggest that the proposed model can potentially serve as a basis for AMS CMOS circuit design automation.
1 INTRODUCTION
CktHGVAE treats circuit design and operating-state variables symmetrically in a graph variational autoencoder. The introduction presents demonstrations of operating-point learning, specification-directed latent-space search, and zero-shot transfer to unseen topologies.
1 INTRODUCTION
- Conventional sizing optimization can be limited by high-dimensional search to several tens of design parameters and still requires many circuit-simulation trials.Source: §1 · p. 1
- Prior VAE latent spaces represent design variables rather than circuit operation, leaving KPIs or state variables to separate neural networks or circuit simulation.Source: §1 · p. 2
- CktHGVAE uses graph neural networks on circuit topology and takes mixtures of design variables and state variables as both inputs and outputs.Source: §1 · p. 2
- 12 fundamental circuit topologies: the model learns DC operating-point circuit operation tested against circuit simulation results.Source: §1 · p. 2
- Specification-directed optimization search is demonstrated in a PCA-reduced latent space using Bayesian, evolutionary, random, and quasi-exhaustive search.Source: §1 · p. 2
- Pretraining on topology groups supports zero-shot transfer to unseen topologies without retraining.Source: §1 · p. 3
2 METHOD
CktHGVAE represents circuit topology and both design and simulator-derived state variables in a graph VAE. The method fits and searches a reduced latent space, checks generated states against SPICE, and evaluates transfer to held-out topologies using topology-specific latent-space fitting.
2.1 Neural Network Model Architecture
- The encoder and decoder process heterogeneous circuit graphs, with design and state variables assigned to device, pin, and net nodes; topology-agnostic parameters support transfer across topologies.The encoder maps node variables through type-specific MLP heads and GraphSAGE message passing to latent distributions; the decoder reverses this process to reconstruct physical variables.Source: §2.1 · p. 3
2.2 Latent Space Fitting and Search
- PCA reduces the concatenated latent space before GMM fitting and specification-directed search; the objective penalizes decoded specification deviations and latent points in low-density regions.The study considers Bayesian optimization, CMA-ES, random search, and quasi-exhaustive search in the PCA-reduced space.Source: §2.2 · p. 5
2.3 Closed-loop Fidelity Verification
- Closed-loop fidelity verification decodes sampled reduced-space points, simulates their design variables in SPICE, and compares simulated with generated state variables using R2.The procedure first fits the model, PCA, and GMM on a dataset, then checks new samples against SPICE simulations.Source: §2.3 · pp. 5–6
2.4 Zero-shot Cross-topology Transfer Capability Test
- For zero-shot transfer, pretrained encoder/decoder weights remain frozen on held-out topologies; their training data are used to fit PCA and GMM before reduced-space reconstruction is evaluated.The reconstruction R2 values are not directly comparable with Section 3.1 because this test does not generate new samples verified by SPICE.Source: §2.4 · p. 6
2.5 Circuit Topologies, Simulation and Dataset Preparation
- The datasets use Ngspice operating-point simulations with SkyWater 130nm models at 1.8 V, then split surviving samples into 70/15/15% training, validation, and test sets.Approximately 1,000 samples per topology were retained, or 2,000 for the larger datasets.Source: §2.5 · p. 6
2.6 Software versions
- The implementation uses Python, PyTorch and PyTorch Geometric, scikit-learn for PCA/GMM, Optuna for BO/CMA-ES, and Ngspice for circuit simulation.Source: §2.6 · p. 8
3 RESULTS
CktHGVAE reconstructs circuit states with high fidelity across several topologies, and latent-space optimization (LSO) produces candidates that often satisfy specifications in SPICE. Its pretrained model also reconstructs many unseen topologies, though transfer depends on the pretraining set.
3.1 Closed-loop Fidelity Verification
- With one fixed hyperparameter setting, median R^2 exceeded 0.9 for T1–T9; differential pairs reached 0.8141–0.9561 at around 2,000 samples, versus 0.6908–0.9207 around 1,000.Evaluations used in-domain samples; the reported dataset sizes are approximate.Source: §3.1 · p. 9, Table 3 · p. 10
3.2 Latent Space Optimization
- SPICE confirmed that 28/30 BO and ES candidates, 30/30 RND candidates, and 27/28 QES candidates satisfied the required specifications.The table compares candidates passing the decoder's constraints with those still passing after SPICE re-simulation.Source: §3.2 · p. 10, Table 5 · p. 11
- The four search strategies' small observed differences do not establish a capability ranking, and these requirements could often be met without extensive search.BO and ES often returned warm-start trials, while RND and QES generated candidates in a single batch for exploration.Source: §3.2 · p. 10
3.3 Zero-shot Cross-topology Transfer
- For zero-shot reconstruction, scenarios B–D achieved median R^2 values of 0.72–0.90, while scenario A's median was close to zero for held-out topology T6.The model had not seen the held-out topologies during pretraining; the authors suggest that scenario A's pretraining may have encouraged transferring an NMOS series pattern to its PMOS counterpart.Source: §3.3 · p. 11
- In scenario B, pretraining only on single-ended topologies yielded mean R^2 of 0.720 when reconstructing differential topology T12.The pretraining topologies shared NMOS/PMOS series connections with T12, apart from its NMOS tail current source.Source: §3.3 · p. 11
4 DISCUSSION
CktHGVAE’s architecture links design and state reconstruction to circuit-state fidelity, latent-space optimization, and zero-shot topology transfer. Its current form has limits in conditioning and topology generation, with broader applications left for future work.
4 DISCUSSION
- Symmetric design/state inputs and outputs avoid extra MLP branches for operational-state or KPI prediction, while PCA-reduced latent space supports optimization and potential physical explainability.The GNN-based encoder/decoder enables zero-shot cross-topology transfer, though reconstruction fidelity varies by scenario.Source: §4 · p. 11
- Including state variables in training means minimizing reconstruction loss encourages physically realistic operational states, which agree with SPICE simulations on average.The discussion attributes this behavior to the model naturally capturing underlying circuit-operation physics.Source: §4 · pp. 11–12
- The model does not map design variables to states in a single feed-forward pass; conditioning on specified designs instead requires equality-constrained latent-space search.The current work uses gradient-free search; gradient-based search through the differentiable decoder is left for future work.Source: §4 · p. 12
- Topology generation is outside the model’s current scope; adding topology information to the VAE is described only as a possible extension.The proposed higher-hierarchical latent-space extension is not part of the near-future scope.Source: §4 · p. 12
- Planned extensions include topology-specific tuning, larger circuits, cross-process transfer, latent-space explainability, designer copilots, tighter specifications, and AC/transient characteristics.The proposed AC and transient extension would add capacitive state variables and simulation types.Source: §4 · p. 12
5 CONCLUSION
CktHGVAE reconstructs circuit operational states, supports latent-space optimization, and transfers to unseen topologies without retraining. Its demonstrated fidelity varies across transfer scenarios, but the results suggest a basis for AMS CMOS circuit design automation.
5 CONCLUSION
- Median R2 exceeded 0.9 for typical single-ended amplifiers and the CMOS inverter, while differential-pair values were 0.8141–0.9561, using one untuned hyperparameter configuration.The reported comparisons use approximately 1,000 SPICE samples for the former circuits and approximately 2,000 for differential pairs.Source: §5 · p. 12
- For the four search strategies, 28–30 of 30 suggested designs met specifications at decoder output, and SPICE verified that 27–30 met them.The demonstration used a common-source amplifier with NMOS input and resistive load.Source: §5 · p. 12
- Pretraining on single-ended topologies yielded zero-shot differential-pair reconstruction median R2 values of 0.720–0.901, though one of four scenarios had poor fidelity.Transfer fidelity depended on which topologies were used for pretraining.Source: §5 · pp. 12–13
- The demonstrations suggest that a simple GVAE treating design and state variables symmetrically can serve as a basis for AMS CMOS circuit design automation.Source: §5 · p. 13
A HYPERPARAMETERS
The appendix table is identified as covering model hyperparameters and configuration options.
A HYPERPARAMETERS
- Table 7 presents model hyperparameters and configuration options.Source: Table 7 · p. 15