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STISA: A 0.16 GOPS/W/PE Single-Shot Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design

Kainan Wang, Chengyi Yang, Lei Liu, Chengting Yu, Yee Sin Ang, Bo Wang, Aili Wang

arXiv:2610.19973v1cs.AR

TL;DR

SNN inference must balance accuracy, latency, and energy efficiency despite the temporal dependencies that make multi-timestep computation costly. STISA combines block-wise temporal compression with a spatiotemporal hardware architecture and bandwidth-aware resource allocation. The framework reports synaptic-operation reductions across four datasets and FPGA hardware improvements.

  • Problem

    Block-level timestep compression creates branch-load imbalance and resource fragmentation that complicate efficient hardware implementation.

    Source: B. TSC Experimental Results and Analysis · p. 5

  • Method

    STISA combines block-wise TSC with TPOS dataflow, BMS architecture, and bandwidth-aware resource allocation for spatiotemporal parallel inference.

    Source: §I · p. 2

  • Results

    TSC reduces synaptic operations by 24.44%-51.71% while achieving competitive accuracies on CIFAR-10, CIFAR-100, ImageNet, and DVS-CIFAR10.

    Source: §VII · p. 13

  • Takeaways & Limitations

    The architecture combines inter- and intra-block parallelization with bandwidth-aware allocation and eliminates membrane-potential buffering.

    Source: §VII · p. 13

Abstract

from arXiv · show

Spiking neural networks (SNNs) offer great potential for low-power intelligent computing owing to their event-driven nature, yet their deployment is limited by high inference latency and inefficient hardware utilization caused by temporal dependencies. Existing accelerators struggle to balance timesteps, accuracy, and energy efficiency, while hardware-oriented timestep compression remains underexplored. To address these challenges, this work presents STISA, a unified algorithm-hardware co-design framework featuring: (i) a Temporal Splitter Compression (TSC) technique with a Temporal Split Structure (TSS) to reduce temporal redundancy while preserving network dynamics; (ii) a hardware-efficient spatiotemporal parallelism scheme, which co-optimizes dataflow and architecture through a Temporal-Prioritized Output-Stationary (TPOS) mapping and a flexible Block-Mux Streaming (BMS) architecture; and (iii) a joint TSC-TPOS-BMS co-optimization framework featuring a bandwidth-aware resource allocation strategy to achieve balanced accuracy, latency, and energy efficiency across diverse network architectures. On the algorithmic side, TSC reduces synaptic operations by 24.44%-51.71% while achieving competitive accuracies of 96.38%, 81.10%, 68.51%, and 82.40% on CIFAR-10, CIFAR-100, ImageNet, and DVS-CIFAR10, respectively. On the hardware side, FPGA prototypes deliver up to 7.99 speedup, 30.4% power reduction, and 30.1% LUT reduction. Compared with state-of-the-art SNN accelerators, STISA achieves 0.16 GOPS/W/PE, demonstrating its scalability and superior energy efficiency for real-time SNN inference under constrained hardware resources.

I. INTRODUCTION

STISA addresses the latency and utilization costs of temporal dependencies by co-designing SNN timestep compression with hardware mapping. Its TSC, spatiotemporal architecture, and bandwidth-aware allocation target a balance of accuracy, latency, and energy efficiency.

I. INTRODUCTION

  • Temporal dependencies make accurate SNN inference require multiple timesteps, increasing latency and memory footprints while limiting hardware utilization.Balancing accuracy, latency, and energy efficiency remains a central bottleneck in neuromorphic acceleration.Source: §I · p. 1
  • Existing temporal-parallel accelerators trade latency reduction for higher area, power, and membrane-potential storage costs, while algorithm-hardware co-designs can rely on complex models or offline analysis.The reported limitations constrain scalability and real-time applicability, leaving a mismatch between algorithmic efficiency and hardware realizability.Source: §I · pp. 1–2
  • TSC reduces synaptic operations by 51.71%, 46.71%, 33.6%, and 24.44% on CIFAR-10, CIFAR-100, ImageNet, and DVS-CIFAR10, respectively.Reported accuracies on those datasets are 96.38%, 81.10%, 68.51%, and 82.40%, respectively.Source: §I · p. 2
  • TSC uses a Temporal Split Structure to redistribute timesteps across parallel branches, suppressing temporal redundancy while maintaining accuracy and temporal dynamics.Source: §I · p. 2
  • STPA combines TPOS dataflow and BMS architecture to improve weight and membrane-potential locality, eliminate membrane-potential storage, and enable spatiotemporal parallel execution.Source: §I · p. 2
  • A bandwidth-aware resource-allocation strategy integrates TSC and STPA to balance accuracy, latency, and energy efficiency across diverse SNN models and FPGA platforms.Source: §I · p. 2

II. BACKGROUND

The background describes the LIF neuron dynamics and their discrete-time implementation. It identifies input accumulation and membrane-potential updates as major sources of computational and storage complexity.

A. SNN Neuron Model

  • The paper adopts the standard leaky integrate-and-fire model, in which membrane potential evolves over time and a threshold crossing emits a spike and resets the potential.Source: A. SNN Neuron Model · p. 2
  • Hardware implementation divides discrete-time LIF dynamics into input-current accumulation, membrane-potential update, and output-spike generation phases.The update uses the previous state and accumulated input current; a threshold crossing triggers a spike and reset.Source: A. SNN Neuron Model · p. 2
  • Input accumulation is computationally costly because of dense synaptic connectivity, while membrane-potential updates require frequent storage access and read-write operations across timesteps.Source: A. SNN Neuron Model · p. 2

B. SNNs Temporary Compression

SNN layers have different temporal demands, so uniform timestep reduction can sacrifice accuracy or retain redundant computation. TSC adapts timestep allocation at the block level to better match those differences.

B. SNNs Temporary Compression

  • Uniformly shrinking timesteps across layers can be overly aggressive, whereas layer-wise adaptation can maintain or improve accuracy with fewer average timesteps.Source: B. SNNs Temporary Compression · p. 2
  • Prior analyses report higher activation entropy and temporal demand in many deeper layers, while lower-entropy layers can carry redundancy under a uniform timestep setting.Naively shortening the global time window can discard useful temporal information and degrade accuracy.Source: B. SNNs Temporary Compression · p. 2
  • A uniform timestep creates a short-long mismatch: shallow layers perform redundant spike computations even as temporal accumulation is needed to form higher-level semantics.Source: Figure 1 · p. 3
  • TSC assigns timesteps at the block level, giving longer windows to deeper, higher-entropy, or timestep-sensitive blocks and shorter windows to shallow blocks with clearer redundancy.This block-level allocation targets a better accuracy-latency-energy trade-off than globally shortening timesteps.Source: B. SNNs Temporary Compression · p. 3

C. TPOS Dataflow and BMS Architecture Hardware Considerations

The section motivates hardware mapping that balances temporal parallelism against bandwidth, storage, and resource costs. It also describes TSC’s block-wise allocation and its reported compression results.

C. TPOS Dataflow and BMS Architecture Hardware Considerations

  • Serial inference has a smaller hardware footprint but higher end-to-end latency and frequent off-chip accesses; fully parallel execution enables single-shot inference but scales compute and storage with timestep count.Redundant computation can remain under fully parallel execution.Source: C. TPOS Dataflow and BMS Architecture… · p. 3
  • TPOS prioritizes temporal unrolling, reuses weights across timesteps, and keeps partial sums stationary to eliminate membrane-potential buffering.BMS combines cross-block pipelining with intra-block time-division multiplexing, while block homogeneity and output-channel parallelism support utilization and load-aware allocation.Source: C. TPOS Dataflow and BMS Architecture… · p. 3

1) Comparison Between Standard and TSC-Compressed SNNs:

  • Uniform timestep compression can sharply reduce accuracy in deeper networks, while shallow layers are more robust; inferring a four-timestep-trained model with one timestep reduces accuracy and spiking activity.Source: 1) Comparison Between Standard and… · p. 4
  • TSC assigns longer temporal windows to deeper, higher-entropy or more sensitive blocks and shorter windows to shallow blocks with significant redundancy.The approach targets a better trade-off among accuracy, latency, and energy efficiency.Source: 1) Comparison Between Standard and… · p. 4
  • TSC reduces the layer-timestep product and synaptic-operation energy while keeping accuracy degradation below 0.6%.The reported result follows a ResNet18 example trained with four timesteps and assigned timesteps across its four main blocks.Source: 1) Comparison Between Standard and… · p. 4, Figure 2 · p. 4

2) Forward Propagation and Loss Function Modeling of TSC:

TSC models forward propagation and training with a Temporal Split Structure, then uses selective inference execution to reduce computation. Its evaluations report accuracy-efficiency trade-offs across static and neuromorphic datasets and identify hardware challenges from branch imbalance and block-level timestep variation.

2) Forward Propagation and Loss Function Modeling of TSC:

  • TSC formulates forward propagation in Equation (5) and defines its loss using Temporal Efficient Training, evaluating loss and backpropagation with cumulative output-layer membrane potential H.The corresponding gradient computation is derived in Equation (7).Source: 2) Forward Propagation and Loss… · p. 4

3) Training and Inference Procedure of TSC:

  • During training, the main and TSS branches jointly optimize temporal dynamics while retaining independent parameters; inference activates only the forward path, with TSS processing fewer timesteps.The TSS branch supplies temporal context while reducing redundant computation, synaptic operations, and memory accesses.Source: 3) Training and Inference Procedure of… · p. 4

B. TSC Experimental Results and Analysis

  • TSC uses main-branch timestep configurations [1, 2, 2, 3] for CIFAR-10 and [1, 2, 3, 3] for CIFAR-100 and ImageNet, with accuracy drops of 0.29%, 1.05%, and 1.39%, respectively.For DVS-CIFAR10, configurations [4, 6, 8, 8] and [4, 6, 6, 8] yield accuracy decreases of 0.1% and 0.6%.Source: Figure 3 · p. 5
  • On CIFAR-10 and CIFAR-100, TSC achieves 0.31% and 0.87% higher classification accuracies than SEENNI and SEENNII, respectively, with slightly smaller operation reductions.On ImageNet, it improves over SEENNI by 18.1% in operation reduction and 3.85% in accuracy; it also delivers competitive recognition on dynamic datasets.Source: B. TSC Experimental Results and Analysis · p. 5
  • TSC can reduce latency without added hardware cost under temporal-serial processing, while temporal parallelism can reduce latency to one timestep; branch load imbalance and inconsistent block timesteps create utilization and scheduling challenges.When auxiliary blocks finish earlier than main-branch blocks, idle waiting and variable idle ratios can increase scheduling overhead.Source: B. TSC Experimental Results and Analysis · p. 5

IV. STISA HARDWARE OVERVIEW

STISA combines TSC with TPOS dataflow and BMS streaming to translate temporal compression into single-shot hardware execution. Its co-optimization accounts for block-level latency and bandwidth constraints while organizing compute and buffers as a block-wise pipeline.

IV. STISA HARDWARE OVERVIEW

  • TSC alone cannot provide single-shot inference, so dataflow and architecture strategies are needed to turn its computational and latency reductions into hardware benefits.The stated goal is low latency and high energy efficiency while maintaining competitive accuracy.Source: §IV · pp. 5–6
  • TPOS prioritizes temporal-loop unfolding, reuses weights across timesteps, and keeps partial sums stationary, eliminating membrane-potential buffering and reducing memory burden.It targets latency and energy efficiency while enabling full temporal parallelization for single-shot inference.Source: §IV · p. 6
  • BMS uses block-wise streaming and homogeneous per-block configurations to reduce coordination overhead and resource fragmentation, with time-multiplexed compute and buffers supporting deeper networks without additional hardware.Output-channel parallelization and prioritization of latency-critical main-branch blocks balance loads and shorten the critical path.Source: §IV · p. 6, Figure 4 · p. 7
  • STISA combines TSC, TPOS, and BMS in a bandwidth-aware optimization that models per-block latency and parallelism to maximize throughput and equalize latency within a bandwidth budget.The framework is intended to sustain performance across diverse models and platforms.Source: §IV · p. 7
  • STISA organizes main-auxiliary block pairs as a pipeline with configurable temporal-spatial parallelism and synchronized inter-block feature-map transfers.Each block has control logic and private feature and weight buffers; its compute unit accumulates input currents and its neuron unit updates neuron state and emits spikes.Source: §IV · p. 7

V. HARDWARE IMPLEMENTATION

The hardware implementation combines TPOS convolution dataflow with channel-packed spike vectors, a tailored line buffer, and configurable processing elements. These components reuse input and weight data while supporting multiple convolution modes.

1) TPOS Dataflow of the Convolutional Layer:

  • TPOS propagates spike vectors across processing elements, reuses weights across timesteps, and accumulates weighted inputs into stationary partial sums before neuron updates.The neuron unit compares accumulated membrane potential with threshold across timesteps and refreshes neuron states without retaining membrane potentials between timesteps.Source: 1) TPOS Dataflow of the Convolutional… · p. 7, Figure 5 · p. 8

2) Channel-Packed Spike Vector Representation and Tailored Line-Buffer Microarchitecture:

  • Channel-packed spike vectors aggregate channels at each spatial coordinate for one memory transaction, while FIFO rows in the line buffer feed aligned processing-element rows for continuous streaming.For standard convolution, FIFO count equals kernel height minus one, and each FIFO has minimum depth Wi and bitwidth Ci.Source: 2) Channel-Packed Spike Vector… · p. 8

3) Microarchitecture of the Processing Element:

B. Block-Mux Streaming Architecture

BMS combines block-wise streaming and sparse spike transmission with latency-aware intra-block parallelism. Its per-block parallel factors are balanced against bandwidth and throughput constraints.

1) BMS Architecture Design:

  • 15.14% spike-vector sparsity in CIFAR-10’s first convolutional layer exceeds the 14% threshold; pruning below 1% cuts off-chip traffic by 9.8% and system traffic by 4.87%.Raising the pruning threshold to 3% reduces off-chip traffic by 19.06% and system traffic by 15.46%.Source: 1) BMS Architecture Design · p. 9, Figure 7 · p. 9
  • Per-block parameterization, inter-block handshaking, and COO spike encoding form a block-wise pipeline that improves resource management and data-transfer efficiency.Request-response handshaking synchronizes inter-block feature-map transfers under rate imbalance.Source: 1) BMS Architecture Design · pp. 8–9

2) Intra-Block Parallel Processing Strategy and Optimization:

  • As the number of inputs grows, average per-frame latency approaches the maximum-latency convolution block, amortizing pipeline latency across inputs.The block latency is decomposed to tune layer latency using a block-specific output-channel parallel factor.Source: 2) Intra-Block Parallel Processing… · p. 9, Figure 8 · p. 9
  • Per-block parallel factors are selected to balance compute efficiency and bandwidth limits along the throughput-critical path across network architectures.Factors are constrained by available bandwidth and required to be divisible by the number of output channels for regular mapping.Source: 2) Intra-Block Parallel Processing… · p. 9

VI. EXPERIMENTAL SETUP AND HARDWARE EVALUATION

The evaluation uses multiple SNN models and datasets on a host-FPGA platform. The FPGA implementation uses 8-bit weight quantization and operates at 200 MHz.

A. Experimental Setup

  • SCNN9 and spiking ResNet18 are evaluated on CIFAR-10, while spiking ResNet34 is evaluated on ImageNet.The first convolutional layer performs spike encoding before the spike trains enter the accelerator.Source: A. Experimental Setup · p. 9
  • The TPOS comparison examines hardware power distribution, average inference latency, and energy with and without TSC on CIFAR-10 ResNet18.The comparison uses TPOS without intra-block parallelism.Source: Figure 10 · p. 10
  • The FPGA platform is a Xilinx ZCU102 board with an XCZU9EG FPGA; the Verilog design is synthesized with Vivado 2022.1 at 200 MHz.Vitis 2022.1 provides a TCP-based host interface for input data and control commands.Source: A. Experimental Setup · p. 10

B. Hardware Evaluation

The hardware evaluation finds that combining TSC, TPOS, and BMS improves latency balance, power, and logic-resource utilization. TSC alone reduces energy, while intra-block parallelism improves throughput by addressing block-level latency imbalance.

1) Evaluation of TPOS With and Without TSC:

  • With TSC under TPOS, auxiliary branches have shorter latency and partly offload main-branch power, reducing overall system energy.The maximum-latency block remains the system bottleneck and degrades utilization of other blocks.Source: 1) Evaluation of TPOS With and Without… · p. 10

2) Joint Evaluation of TPOS+TSC With and Without BMS:

  • 7.96× pipeline performance improvement for SCNN9 and 7.99× for ResNet34 follow the introduction of intra-block parallelism.More compute resources are allocated to latency-critical blocks, balancing latency across blocks and improving hardware utilization.Source: 2) Joint Evaluation of TPOS+TSC With… · p. 10

3) Joint Evaluation of BMS+TPOS With and Without TSC:

  • 30.4% average power reduction and 30.1% average LUT reduction are reported for ResNet34 with TSC and TPOS+BMS.The figure compares block power and resource usage with and without TSC under TPOS and intra-block parallelism.Source: 3) Joint Evaluation of BMS+TPOS With… · p. 10, Figure 11 · p. 11
  • 51.92% fewer LUTs and 22.83% lower power are reported for CIFAR-100 ResNet18 with TSC under spatial-temporal parallelism; at equal latency, system energy is lower.The system-level comparison uses normalized plots of total LUTs and power versus average latency.Source: 3) Joint Evaluation of BMS+TPOS With… · p. 11

C. Comparison and Analysis with Previous Work

STISA is compared with FPGA-based SNN accelerators across accuracy, throughput, power, efficiency, and resource metrics. Its results include hardware gains on ResNet34, while ImageNet comparisons note lower FPS and energy efficiency than Firefly2 and DeepFire2.

C. Comparison and Analysis with Previous Work

  • Tables III and IV compare accelerator accuracy, throughput, power, efficiency, and hardware resource utilization across CIFAR-10, CIFAR-100, and ImageNet.The comparison passage describes the experimental setup as consistent across accelerators.Source: C. Comparison and Analysis with… · p. 11, Table III · p. 12, Table IV · p. 12
  • STISA reports 95.29% accuracy on CIFAR-10 and 68.51% on ImageNet while reducing average main-branch timesteps; the results are described as comparable to recent SNN literature.DeepFire2 prioritizes latency with T = 1, which the passage says compromises classification accuracy.Source: C. Comparison and Analysis with… · p. 11
  • STISA has slightly lower FPS and energy efficiency than Firefly2 and DeepFire2 on ImageNet, but achieves higher per-PE energy efficiency without DSP-specific features.The cited comparison describes the other designs as relying on DSP-centric strategies tied to specific FPGA architectures.Source: C. Comparison and Analysis with… · p. 13

VII. CONCLUSION

  • For ImageNet on ResNet34, STISA achieves up to 7.99× speedup, 30.4% power reduction, 30.1% LUT reduction, and 0.16 GOPS/W/PE.The conclusion presents these results as an efficient latency-energy-accuracy trade-off under limited resources.Source: §VII · p. 13

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