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Cross-Layer Co-Design of Low-Latency Stateful Logic Adders with Printed Memristors

Fabian Seiler, Kerem Kagan Güclü, Hongrong Hu, Gabriel Cadilha Marques, Jasmin Aghassi-Hagmann, Nima TaheriNejad

arXiv:2610.20109v1cs.ET

TL;DR

Data movement between memory and processing units is a bottleneck, while stateful-logic adder efficiency depends on device-compatible primitives, operation dependencies, and datapath mapping. This paper co-designs those layers using printed ECM memristors and carry-aware adder mappings. The proposed parallel and pipelined mappings reduce cycles and improve performance across the evaluated workloads.

  • Problem

    Stateful-logic adder efficiency depends jointly on the device-supported primitive set, operation dependencies, and datapath mapping, while prior work typically optimized these layers separately.

    Source: §I · p. 1

  • Method

    The authors experimentally demonstrate mixed MAGIC and FELIX primitives on printed ECM memristors and co-design a carry-optimized full-adder sequence with serial, parallel, and pipelined mappings.

    Source: §I · p. 1, A. Carry-Optimized Full Adder Design · p. 3, B. Datapath-Aware Mapping · p. 3

  • Results

    3.7×–16.4× speedup over the state-of-the-art baseline is reported for evaluated workloads; parallel and pipelined mappings require 2n + 6 cycles.

    Source: §V · p. 4

  • Takeaways & Limitations

    The evaluated results highlight the importance of jointly considering device, logic, and datapath architecture layers when designing stateful-logic arithmetic.

    Source: §V · p. 4

    The workload comparison excludes control and external data-transfer overheads and assumes operands reside in the active tile with intermediate results remaining in memory.

    Source: B. Workload-Level Throughput · p. 4

Abstract

from arXiv · show

Data movement between memory and processing units remains a major bottleneck in data-centric systems. Memristive Stateful Logic (SL) addresses this problem by performing Boolean operations directly on stored resistive states. However, arithmetic efficiency depends jointly on the device-supported logic primitive set, the dependency structure of the resulting operation sequence, and its mapping to datapath architectures. While prior designs typically optimize device, logic, and architecture layers separately, we jointly consider them to co-design a stateful adder. We experimentally demonstrate a mixed MAGIC and FELIX logic primitive set on printed Electrochemical Metallization (ECM) memristors and derive a full adder sequence optimized for inter-bit carry propagation. Mapping this sequence to bit-serial, bit-parallel, and bit-pipelined datapaths reduces the latter two to 2n+6 cycles for an n-bit addition. For 32-bit addition, this requires 60-88% fewer cycles than prior SL adders. Across four representative workloads, we achieve 3.7x-16.4x speedup over prior. These results show how cross-layer co-design can translate into improved workload-level performance.

I. INTRODUCTION

Stateful Logic performs Boolean and arithmetic operations directly on stored resistive states, but adder efficiency depends on co-designing device-compatible primitives, operation dependencies, and datapath mapping.

I. INTRODUCTION

  • Prior work typically optimized arithmetic sequences within fixed logic families or mapped fixed primitive sets to architectures, limiting datapath-aware sequence co-design.Addition is especially sensitive because latency is often dominated by inter-bit carry propagation.Source: §I · p. 1
  • The paper jointly co-designs a device-compatible primitive set, a carry-aware full-adder sequence, and bit-serial, bit-parallel, and bit-pipelined mappings.Its contributions include experimental validation of mixed MAGIC and FELIX primitives on printed ECM memristors.Source: §I · p. 1
  • 2n + 6 cycles is the reported latency for the proposed mappings on parallel and pipelined datapaths, with 3.7×–16.4× workload-level speedup over comparable state-of-the-art adders.The reported cycle reduction is 60%–88%.Source: §I · p. 1

II. PHYSICAL VALIDATION OF MIXED STATEFUL LOGIC

The paper fabricates printed Ag/ZnO/Au ECM memristor crossbars and demonstrates MAGIC NOR, MAGIC NOT, and FELIX XOR operations on the same device stack.

A. Device Fabrication and Experimental Setup

B. Validation of Stateful Logic Primitives

The experimental validation tests MAGIC NOR and NOT and two-cycle FELIX XOR, with operation voltages selected to avoid erroneous switching in designated input cases.

B. Validation of Stateful Logic Primitives

  • 87.5 %, 100 %, and 95.0 % are the reported success rates for NOR, NOT, and XOR, respectively.Failures mainly involved output failing to RESET; input switching occurred in 1.25 % of NOR and XOR tests and none of the NOT tests.Source: B. Validation of Stateful Logic… · p. 2
  • The demonstrations report low input switching for MAGIC NOR (1.25 %) and error-free MAGIC NOT, while NOR and XOR success rates remain limited by device variability.The authors describe the results as proof of concept requiring further device optimization.Source: B. Validation of Stateful Logic… · p. 2
  • To the authors’ knowledge, this is the first multi-cycle experimental demonstration of FELIX XOR and MAGIC NOR in the same memristor stack.The figure presents the proposed adder and datapath mappings, rather than additional primitive-validation measurements.Source: B. Validation of Stateful Logic… · p. 2, Figure 2 · p. 3

A. Carry-Optimized Full Adder Design

The full-adder sequence reduces carry-dependent work by precomputing local terms before the incoming carry arrives.

A. Carry-Optimized Full Adder Design

  • The available primitive composition is {NOR, NOT, OR, NAND}, providing {⊕, ¬, ∨}; XOR uses consecutive OR and NAND µOPs over two cycles.The output state also depends on initialization, so complemented states are generated before the carry arrives.Source: A. Carry-Optimized Full Adder Design · p. 3
  • The eight stateful µOP full-adder computation has a carry critical-path depth of only two, with two additional initialization cycles.Steps 1–4 depend only on a_i and b_i; the inter-bit dependency is confined to NOR operations in steps 5–6, and final XOR operations complete the sum.Source: A. Carry-Optimized Full Adder Design · p. 3

B. Datapath-Aware Mapping

The proposed full-adder sequence is mapped onto serial, parallel, and pipelined datapaths, with parallel and pipelined execution exploiting shortened inter-bit dependencies to reach 2n + 6 cycles.

B. Datapath-Aware Mapping

  • 8n cycles are required by the bit-serial mapping because it completes each bit’s eight-step sequence before moving to the next bit.This organization reuses one computational region and cannot exploit the shortened inter-bit dependency.Source: B. Datapath-Aware Mapping · p. 3
  • 2n + 6 cycles are required by both the bit-parallel and bit-pipelined mappings for an n-bit addition.The reported latencies exclude two pre-initialization cycles.Source: B. Datapath-Aware Mapping · p. 3
  • Bit-parallel execution broadcasts steps 1–4 across partitions, then staggers steps 5–8 across successive bit positions.Successive bits are displaced by two cycles.Source: B. Datapath-Aware Mapping · p. 3
  • Bit-pipelined execution shifts a common instruction sequence across partitions and writes carry results directly to inter-partition buffers.The carry-producing operation avoids dedicated buffer-transfer operations.Source: B. Datapath-Aware Mapping · p. 3

C. Control and Hardware Trade-offs

The three datapaths trade hardware and control overhead against execution flexibility and pipeline overlap.

C. Control and Hardware Trade-offs

  • Bit-serial execution minimizes hardware and control overhead; bit-parallel adds X = r(p−1) switches for flexible independent scheduling, while bit-pipelined adds 2X switches and X buffers for regular control and overlapping additions.Bit-parallel requires the most complex control; bit-pipelined uses a temporally shifted instruction stream.Source: C. Control and Hardware Trade-offs · p. 4

A. Adder-Level Comparison

The proposed parallel and pipelined mappings reduce compute cycles relative to considered SIMD-compatible stateful-adder baselines, while retaining row-wise SIMD execution.

A. Adder-Level Comparison

  • 60–88% fewer cycles are required by the proposed parallel and pipelined mappings than by considered SIMD-compatible baselines.For n = 32, both mappings require 70 cycles while retaining row-wise SIMD execution; latency reduction costs spatial replication of bit-level computation.Source: A. Adder-Level Comparison · p. 4

B. Workload-Level Throughput

Across four evaluated workload dependency structures, the proposed bit-pipelined mapping outperforms prior stateful-adder mappings. The conclusion reports 3.7×–16.4× speedup over the SoA baseline and emphasizes joint device, logic, and datapath design.

B. Workload-Level Throughput

  • 3.7×–16.4× speedup over SoA mappings is achieved by the proposed pipelined mapping across four evaluated workload structures.It improves over the proposed parallel mapping by approximately 2×.Source: B. Workload-Level Throughput · p. 4
  • Pipelined advantage is largest for Vector Add and decreases as dependencies constrain concurrency; for Acc64, parallel and pipelined mappings converge to the same latency.The evaluated structures range from independent additions to chains where each addition depends on the previous result.Source: B. Workload-Level Throughput · p. 4

V. CONCLUSION

  • The conclusion reports 2n + 6 cycles for n-bit additions on parallel and pipelined datapaths, 60%–88% lower latency than SoA adders, and 3.7×–16.4× workload speedup.It identifies joint consideration of device, logic, and datapath architecture as important to SL arithmetic design.Source: §V · p. 4
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