Source-linked AI summary
GNN-Guided Local Refinement for Efficient Layout Decomposition with DSA-MP
Yu Feng, Liyi Zhou, Haoyu Wang, Yiming Xu, Hao Geng, Shaozhi Deng, Ningsheng Xu, Shisheng Xiong
TL;DR
DSA-MP decomposition must balance solution quality and runtime amid tightly coupled grouping and mask-assignment choices, while accounting for template-spacing constraints. The paper models those conflicts and uses a GNN to select vias for local ILP refinement; reported results show faster solving with small cost increases and generalization across layouts and nodes.
Problem
DSA-MP decomposition combines coupled via grouping and mask assignment, creating a difficult search where existing approaches struggle to balance solution quality and runtime.
Source: §1 · p. 1Method
A template edge-to-edge conflict graph is paired with a GNN that uses early ILP features to predict vias for reassignment and locally re-optimizes them.
Source: §1 · p. 2Results
About 45× speedup over EILP with only 0.1% cost increase on 7 nm synthetic benchmarks, with reported generalization across design styles, technology nodes, layout scales, and mask counts.
Source: §1 · p. 2, §5.3 · p. 7Takeaways & Limitations
The framework provides a high-quality, faster-converging approach to DSA-MP decomposition and may apply to other ILP-based physical-design optimization problems.
Source: §6 · p. 8
Abstract
from arXiv · showhide
Multiple patterning lithography (MPL) has been widely used to improve lithography resolution in advanced nodes, but it faces cost limits as feature sizes shrink. Directed self-assembly (DSA) offers a cost-effective complement, extending the resolution of optical lithography to sub-10 nm and beyond. Integrating DSA into MPL (DSA-MP) further enhances the resolution of contact/via patterning. Nevertheless, growing design complexity exposes the limits of existing decomposition methods, which struggle to balance solution quality and runtime, and neglect edge-to-edge spacing constraints of DSA templates, compromising manufacturability. To address these issues, we introduce a new conflict graph model capturing the previously overlooked constraints and develop a local refinement strategy powered by the graph neural network, enabling efficient and scalable layout decomposition. Experiments demonstrate that our method achieves higher solution quality with faster convergence than state-of-the-art methods, while maintaining robustness across layout scales, design styles, technology nodes, and varying mask counts.
1 Introduction
DSA-MP can reduce mask conflicts for via patterning, but coupled grouping and mask-assignment decisions make decomposition difficult to solve efficiently. The paper combines a template-spacing conflict model with GNN-guided local refinement to improve solution quality and convergence.
1 Introduction
- DSA-MP makes decomposition harder because grouping and mask assignment are tightly coupled, many valid groupings exist, and rising conflict density challenges prior methods.The conflict-to-via ratio has grown from around 1:2 to 2:1 or even 3:1; exact ILP methods incur prohibitive runtime, while DLXplus can sacrifice solution quality.Source: §1 · p. 1
- Early ILP solving records can identify a small subset of vias for reassignment, allowing re-optimization to match the optimal objective value with less search.The proposed flow uses solver-derived features to predict vias for reassignment while fixing the others.Source: §1 · pp. 1–2, Figure 1 · p. 1
- The conflict model explicitly represents edge-to-edge spacing between DSA templates, which center-to-center via distances do not capture.Template geometry and sufficient spacing matter for stable pattern formation and correction against proximity effects.Source: §1 · p. 2
- The method achieves about 45× speedup with only 0.1% cost increase on 7 nm synthetic benchmarks, while generalizing well to other 7 nm designs and 5 nm industrial layouts.Source: §1 · p. 2
2 Preliminaries
DSA uses lithographically defined templates to guide block copolymers in forming dense vias, subject to grouping and spacing constraints. The section defines the template-and-mask assignment problem and introduces a bipartite representation of ILPs.
2.1 Brief Introduction to DSA
- DSA guides block copolymers with lithographically defined templates through deposition, annealing, and pattern transfer to form dense, uniform vias.Feasible configurations are restricted to 1-D templates with n × 1 holes, n≤2; the BCP natural pitch limits grouping distance to 52–63 nm, and adjacent templates require sufficient edge-to-edge spacing.Source: §2.1 · p. 2
2.2 Problem Formulation
- Groupable vias are aligned horizontally or vertically and fall within the feasible center-to-center grouping range; TMA assigns vias to templates and templates to masks while minimizing spacing conflicts and template cost.The problem specifies a minimum edge-to-edge template spacing, d_min, and K available masks.Source: §2.2 · pp. 2–3
2.3 Bipartite Graph Representation
- An ILP can be represented as a bipartite graph with variable nodes, constraint nodes, and edges weighted by the corresponding variable coefficients.An edge exists when a variable appears in a constraint; the representation preserves the original problem structure and provides input for GNN models.Source: §2.3 · p. 3
3 Proposed Graph Model and ILP Formulation
The proposed hybrid grouping/conflict graph represents template choices and edge-to-edge spacing conflicts, supporting an ILP formulation for template and mask assignment. Its objective penalizes unresolved conflicts and selected two-hole templates, while constraints encode coverage and conflict conditions.
3 Proposed Graph Model and ILP Formulation
- The hybrid graph represents each via as a vertex, feasible two-hole template pairings as edges, and too-close template pairs as conflict hyperedges.It unifies lithography spacing and template-related conflicts as edge-to-edge constraints between templates.Source: §3 · p. 3, Figure 6 · p. 3
- The model distinguishes conflicts between two single-hole templates, a single-hole and a two-hole template, and two two-hole templates.These are denoted SC, STC, and TTC, respectively.Source: §3 · p. 3, Figure 6 · p. 3
- The ILP objective minimizes unresolved conflicts and selected two-hole templates, weighting conflict costs much more heavily than template costs.Each via must be covered exactly once by either a single-hole template or a two-hole template on a mask.Source: §3 · p. 3
- For each conflict candidate, the formulation incurs a conflict penalty when both involved templates are assigned to the same mask.The constraints cover single-hole/single-hole, single-hole/two-hole, and two-hole/two-hole conflict candidates.Source: §3 · p. 4
4 Algorithms
The framework builds a labeled dataset of vias needing reassignment, trains a GNN to identify them, then re-optimizes selected vias while fixing the rest.
4.1 Overview
- The framework constructs the Vias-to-Refine Dataset, trains a GNN on encoded ILP-derived features, and uses its predictions to select variables for re-optimization.Only sampled vias are re-optimized, reducing runtime compared with solving the full ILP from scratch.Source: §4.1 · p. 4
4.2 Vias-to-Refine Dataset Preparation
- The dataset labels vias whose reassignment from an initial solution is required to reach an optimal solution, using ILP-derived features and node-level labels.Synthetic layouts are generated with randomized, design-rule-compliant placements to provide diverse conflict graph topologies for training.Source: §4.2 · pp. 4–5
4.3 GNN Training for Via Selection
- The GNN learns from variable, constraint, and edge features on a bipartite graph, then predicts reassignment probabilities for via variables.Its inputs include ILP-derived variable features, constraint features, and edge features; the model is trained with binary cross-entropy.Source: §4.3 · p. 5
4.4 Inference Procedure
- Inference samples vias from GNN-predicted reassignment probabilities, fixes the remaining vias at their initial assignments, and re-optimizes the selected variables.The sampling distribution aggregates probabilities across masks and uses temperature scaling; two-thirds of the vias are sampled without replacement.Source: §4.4 · p. 5
5 Experimental Results
Across 7 nm and 5 nm benchmarks, the method substantially reduces runtime over EILP with small cost increases, including on difficult layouts. Ablations find benefits from solver-derived features and the proposed conflict graph model.
5.1 Experimental Setting; 5.2 Benchmark Details
- Experiments use DSA-TPL with three masks at 7 nm and DSA-QPL with four masks at 5 nm, with minimum edge-to-edge template spacing set to 50 nm.The 7 nm training set comprises 20 ASAP7-based synthetic layouts with roughly 3,000 vias each; test sets also include BOOM layouts and 5 nm industrial clips.Source: §5.3 · p. 6, §5.1 · p. 6, §5.2 · p. 6
5.3 Result Analysis
- About 45× speedup over EILP with only 0.1% cost increase on 7 nm synthetic layouts; BOOM layouts show about 15× acceleration with around 1.0% cost increase.These results support runtime advantages with near-optimal solution quality across different 7 nm design styles.Source: §5.3 · p. 7
- Approximately 12× speedup over EILP with only 2% increase in cost on 5 nm industrial DSA-QPL layouts, using the same GNN weights without retraining or fine-tuning.The evaluation shifts both technology node and mask count from the 7 nm training setting.Source: §5.3 · p. 7, Table 3 · p. 7
- On challenging instances, our method remains tractable when EILP or DLXplus exceed the 20-hour limit without feasible solutions; on N5_test_11, it achieves 4.2× lower cost in less than half the runtime.The reported difficult cases arise from large scale or complex conflict structures.Source: §5.3 · p. 7, Table 4 · p. 7
- The GNN generalizes from 20 synthetic 7 nm layouts containing about 60,000 vias to layouts over 200K vias, diverse design origins, 5 nm, and K=4.The authors attribute transfer partly to ILP- and solver-derived features rather than layout-specific geometric features.Source: §5.3 · p. 7
5.4 Ablation Study
- Removing any single solver-derived feature worsens both recall and cost; excluding sol_pool_freq causes the largest drop, from 0.979 to 0.933 recall and from 127.89 to 129.05 cost.The feature ablation averages recall and cost over the Table 1 layouts; recall measures correctly identified vias requiring reassignment.Source: §5.4 · p. 8, Figure 8 · p. 8
- Training on synthetic layouts yields lower cost than training on a comparable 60,000-via BOOM set for the 5 nm industrial DSA-QPL evaluation.The authors suggest randomized synthetic geometry supplies diverse local conflict structures and can be generated without proprietary design data.Source: §5.4 · p. 8, Table 5 · p. 8
- The proposed edge-to-edge-spacing conflict graph has the lowest EPE and L2 loss among no-DSA, prior-graph, and proposed-graph settings.Post-OPC simulation contours are reported as more accurate for DSA templates with the proposed model; EPE counts sampled edges exceeding a 5 nm deviation threshold.Source: §5.4 · p. 8, Figure 9 · p. 8, Figure 10 · p. 8
6 Conclusion
The paper presents a new DSA-MP conflict graph that accounts for edge-to-edge template spacing and a GNN-guided local refinement framework that achieves speedup with high-quality solutions.
6 Conclusion
- The framework combines an edge-to-edge-spacing conflict graph with GNN-guided local refinement, achieving significant speedup over state-of-the-art methods while maintaining high-quality solutions.The authors state that the framework may also apply to other ILP-based physical-design optimization problems.Source: §6 · p. 8