PaperlayerView exact revision on arXiv

Source-linked AI summary

Sketch2Sim: an end-to-end modular framework for hand-drawn circuit analysis

Mohammad Kawsar, Al Amin Islam Ridoy, Md Rakib Hossain, Farzana Akter, AKM Bahalul Haque, Rejwan Bin Sulaiman, Mohammed Amin Almaiah

arXiv:2610.28836v1cs.AIcs.CVcs.LG

TL;DR

Hand-drawn circuit interpretation is challenging because component styles, handwritten values, and noisy wiring complicate recognition and topology recovery, while existing systems often cover only part of the task. Sketch2Sim combines a curated circuit dataset with detection, OCR, and node-mapping stages to generate and solve circuit netlists. It reports component-detection and text-recognition metrics and a 94% end-to-end success rate, within a stated first-order RLC scope.

  • Problem

    Hand-drawn components, mixed engineering labels, and noisy wires make component detection, value recognition, and topology extraction challenging, and prior systems rarely automate the full process.

    Source: INTRODUCTION · p. 2

  • Method

    The framework uses a 1,000-diagram handwritten RLC dataset and combines YOLOv8 detectors, CRNN-CTC OCR, and skeletonization with DBSCAN to generate netlists and nodal solutions.

    Source: INTRODUCTION · pp. 2–3

  • Results

    The system reports 98.9% accuracy in component detection, 6.47% character error rate for text recognition, and 94% evaluation success rate (95% CI [83.5–98.1%]).

    Source: CONCLUSION AND FUTURE WORK · p. 37

  • Takeaways & Limitations

    The web interface returns an annotated image and netlist for user review and can perform nodal analysis to present calculated voltages and currents.

    Source: Error and edge-case analysis · p. 35

    The current system supports first-order RLC circuits with independent sources and focuses mainly on passive elements and independent sources.

    Source: LIMITATIONS · p. 36, CONCLUSION AND FUTURE WORK · p. 37

Abstract

from arXiv · show

This study proposes a sketch-to-simulation system to solve handwritten circuit diagrams. The system converts raw images into a Simulation Program with Integrated Circuit Emphasis (SPICE)-compatible netlist and automatically calculates the circuit's nodal voltages and currents. Another objective is to propose a holistic framework that benefits students and educators by enhancing the teaching and learning experience of electric circuits and expediting engineering design reviews. This article presents a multistage pipeline that converts raw photographs of handwritten electric circuits into executable SPICE-like netlists, providing a solution. A dataset of 1,000 hand-drawn Resistor-Inductor-Capacitor (RLC) circuits was curated and annotated for components, text regions, and character recognition. The proposed system decomposes a circuit diagram into three stages: (i) dual You Only Look Once (YOLO)-based detectors for components and text regions, (ii) a Convolutional Recurrent Neural Network (CRNN) with Connectionist Temporal Classification (CTC) and Optical Character Recognition (OCR)-based domain-aware symbol value extraction, and (iii) image processing with thresholding, skeletonization, and Density-Based Spatial Clustering of Applications with Noise (DBSCAN) to automatically identify nodes and map them with corresponding components. The proposed system produces the netlist and solves the circuit. The qualitative and quantitative ablation studies on modular stages, as well as end-to-end tests, demonstrate robust performance across various handwriting styles, lighting conditions, and clutter.This study serves as an interactive learning aid and practical tool for professionals, providing a comprehensive user interface (UI), enabling rapid digitization of circuit sketches for study, design, prototyping, or troubleshooting.

INTRODUCTION

Manual conversion of hand-drawn circuits into simulation-ready formats is slow and error-prone, while existing systems rarely automate the full interpretation process. The paper introduces a dataset and end-to-end framework to detect components, read values, reconstruct topology, generate netlists, and solve circuits.

INTRODUCTION

  • Prior systems often address only component detection or text recognition, leaving fully automated circuit interpretation without manual cleanup uncommon.Hand-drawn components vary in style, size, angle, and line width; labels mix digits, letters, and domain symbols, while noisy wires complicate topology extraction.Source: INTRODUCTION · p. 2
  • The authors curate 1,000 handwritten circuit diagrams and focus on first-order RLC circuits with independent sources as a controlled benchmark.The modular framework is intended to extend to more complex topologies in future work.Source: INTRODUCTION · p. 2
  • The pipeline combines YOLOv8 detection, CRNN-CTC text recognition, and skeletonization with DBSCAN topology reconstruction to produce netlists and nodal solutions.The proposed system is intended for educational and industrial settings, including teaching and engineering design reviews.Source: INTRODUCTION · p. 3
  • The work also reports experimental validation and ablation studies, and provides a web interface for interactive circuit verification and simulation.The interface is presented as deployable.Source: INTRODUCTION · p. 3

BACKGROUND AND RELATED WORKS

Prior circuit-interpretation research has often handled component detection, text recognition, or connectivity separately, with earlier approaches constrained by sketch variation and noisy wiring. The paper positions its contribution as an end-to-end system that couples specialized detection and OCR with topology reconstruction and a web implementation.

BACKGROUND AND RELATED WORKS

  • Early symbol-segmentation and recognition methods struggled with noise, complex connectivity, and variation in hand-drawn symbol styles.Okazaki et al. (1988) used closed-loop shapes; Feng, Viard-Gaudin & Sun (2009) later applied two-dimensional dynamic programming.Source: BACKGROUND AND RELATED WORKS · p. 3
  • Prior handwritten-text approaches included HMM and hybrid models, while encoder-decoder recognition handled text holistically without explicit character- or word-level segmentation.The cited encoder-decoder circuit recognition work could misread notation such as 10 Ω as 100.Source: BACKGROUND AND RELATED WORKS · p. 4
  • Wire-recovery methods faced challenges with curved or jagged lines, spurious node candidates, and merging distinct junctions or branches.The reviewed approaches included Hough transforms, skeletonization with connectivity analysis, and treating wire blobs as a single node.Source: BACKGROUND AND RELATED WORKS · pp. 4–5
  • The proposed system separates component and text detection, pairs text-region detection with OCR for engineering symbols and units, and combines these stages with node extraction and a real-time web implementation.The authors describe the web interface as allowing users to correct interpretation errors; they also report using thinning and DBSCAN to handle imperfect sketches.Source: BACKGROUND AND RELATED WORKS · p. 5

METHODOLOGY

The methodology builds task-specific datasets and models, then combines component and value recognition with wire-based node extraction. It links detected components to nodes and values, assembles a SPICE-compatible netlist, and applies nodal analysis.

METHODOLOGY

  • The dataset contains 1,000 handwritten circuit diagrams from different people, preprocessed with grayscale conversion, noise filtering, cropping, contrast enhancement, and resizing.The component-detection set uses six classes and manually drawn bounding boxes; resistors represent 45.3% of components, while the other classes together represent 54.7%.Source: METHODOLOGY · p. 6, Figure 1 · p. 6, Figure 3 · p. 7
  • The annotation workflow creates component-detection, text-region, and cropped OCR datasets; approximately 3,000 handwritten value regions are annotated for OCR training.The OCR corpus uses a 68-symbol character set including electrical symbols and units such as Ω, µ, V, A, H, and F.Source: Figure 2 · p. 7, METHODOLOGY · p. 8, Figure 4 · p. 8
  • The training process uses separate YOLOv8 models for component and text-region detection and a CRNN-CTC model for text extraction, with multiple model variants and hyperparameters explored.The data split is 70% training, 20% testing, and 10% validation.Source: METHODOLOGY · p. 9, Figure 5 · p. 9
  • The pipeline detects components, crops detected text regions for OCR, and maps the extracted values to their corresponding components.The component and text branches use YOLOv8, while the CRNN-CTC recognizer transcribes sequences without character-level segmentation.Source: METHODOLOGY · pp. 9, 11, 12, Figure 6 · p. 10
  • For topology extraction, detected components and text regions are removed before edge detection and skeletonization identify wire endpoints and junctions for DBSCAN clustering.The lowest node is treated as ground, nearby nodes are merged, and the resulting nodes are assigned to component terminals by nearest-neighbor search.Source: METHODOLOGY · pp. 9, 12
  • The generated netlist is solved using DC nodal analysis to report node voltages and source currents.The described DC model treats inductors as shorts and capacitors as open circuits.Source: METHODOLOGY · pp. 10, 14
  • The system parses component values and units, maps component classes to SPICE prefixes, and assembles labeled component lines into a SPICE-compatible netlist.A terminal marked 999 is omitted from simulation but retained in the overlay.Source: METHODOLOGY · pp. 10, 13, Figure 10 · p. 15

RESULT ANALYSIS

This section evaluates the models and end-to-end system for digitizing hand-drawn circuits, covering detection and text-recognition performance as well as overall accuracy, error sources, stress-test limits, runtime, and the browser-based interface.

Component detection hyperparameter analysis

  • For component detection, RMSprop sharply reduced performance, learning rates of 0.005–0.01 performed best, and more frozen layers reduced performance; epochs and image size mainly affected training time.Freezing layers affected both training time and performance, while weight decay, batch size, and dropout had no notable performance impact.Source: RESULT ANALYSIS · p. 15

Component detection

  • YOLOv8-small achieved the highest observed component-detection mAP@0.5:0.95 (0.697) in 580 s, versus nano’s 0.683 in 389 s, and was selected as the resource-performance sweet spot.YOLOv8-medium used 57% more parameters and nearly twice the training time without meaningful improvement over small; variant differences were descriptive because the evaluation dataset was limited.Source: RESULT ANALYSIS · pp. 18, 21, Figure 11 · p. 21
  • YOLOv8-small’s component-detection curves showed stable convergence, and its test confusion matrix indicated successful detection across classes with few mislabelings of visually similar components.The reported precision and recall improved rapidly in early epochs and remained consistently high thereafter.Source: RESULT ANALYSIS · p. 22, Figure 12 · p. 22, Figure 13 · p. 23

Text region detection hyperparameter analysis

  • For text-region detection, higher epochs and image size improved accuracy at greater computational cost, while freezing layers reduced both time and performance; larger batch size and dropout reduced time without significant accuracy effects.RMSprop had a devastating effect on accuracy, whereas SGD showed stable performance.Source: RESULT ANALYSIS · pp. 22, 24

Text region detection

  • YOLOv8-small was selected for text localization: it improved mAP by 3.2% over nano, while medium’s marginal accuracy gain came with 56% more parameters and nearly 2× training time.The reported variant differences were descriptive rather than statistically significant because of the limited evaluation dataset.Source: RESULT ANALYSIS · p. 28, Figure 14 · p. 28

Text detection by the CRNN

  • The CRNN reached a final character error rate (CER) of 6.47% after 50 epochs of training, using Adam at 1e−3 and 1.08 million parameters.It stabilized around 30 epochs; errors could occur when handwritten characters looked visually similar.Source: RESULT ANALYSIS · pp. 28–29, Figure 16 · p. 29

Edge-case analysis

  • Under isolated visual difficulty the framework remained reasonably stable, but combined structural complexity and handwriting ambiguity degraded performance, especially in node mapping and topology reconstruction.Complex multi-loop circuits and messy wire intersections chiefly affected topology, whereas overlapping values or components more often caused OCR or localization errors.Source: Error and edge-case analysis · p. 31, Figure 17 · p. 32

Categorized end-to-end error breakdown

  • Topology reconstruction affected 3 of 50 circuits (6%) and 75% of failed cases, while component detection, text-region detection, and OCR/value extraction each affected 2 of 50 (4%).Error categories were not mutually exclusive because a failed circuit could have multiple error sources.Source: Error and edge-case analysis · p. 32, Table 14 · p. 32
  • 47 of 50 circuits were interpreted correctly, yielding 94% end-to-end accuracy (95% CI [83.5–98.1%]).Three circuits contained at least one stage-level error.Source: Error and edge-case analysis · p. 33

Computational complexity and runtime analysis

  • Wire and node extraction and OCR-based value assignment dominated runtime, while netlist generation and circuit solving contributed negligibly to overall latency.Timing was measured across the major pipeline stages on 50 test images, excluding visualization and file I/O.Source: Error and edge-case analysis · pp. 33–34, Table 16 · p. 34

Web implementation

  • The web interface accepts uploaded circuit images, returns an annotated image and editable netlist, and presents calculated voltages and currents after the user selects solve.It uses a Flask backend with an HTML, CSS, and JavaScript frontend and works in a browser.Source: Figure 18 · p. 34, Error and edge-case analysis · p. 35

Comparison with prior studies

  • Compared with Alhalabi et al. (2021) and Rachala & Panicker (2022), the proposed system adds automatic value extraction, topology processing, netlist generation, circuit solving, and end-to-end deployment.The cited earlier systems respectively relied on manual component-value input or reconstructed schematics without parsing values, creating netlists, or solving circuits.Source: Error and edge-case analysis · pp. 35–36

LIMITATIONS

The framework is evaluated in a controlled first-order RLC setting with independent sources. Its dataset, topology recovery under difficult sketches, and processing speed leave scope for expansion and optimization.

LIMITATIONS

  • The framework currently supports first-order RLC circuits with independent sources; operational amplifiers and transistors are not yet supported.The study chose this controlled circuit focus to reduce ambiguity in topology reconstruction.Source: LIMITATIONS · p. 36
  • The dataset does not cover the full range of real-world drawing styles or diagram types.Source: LIMITATIONS · p. 36
  • In noisy or overlapping sketches, wire-detection or node-clustering errors can propagate to incorrect topology recovery.Source: LIMITATIONS · p. 36
  • Processing each circuit takes about 2 s, and the implementation may require optimization for real-time deployment.Source: LIMITATIONS · p. 36
  • Future work aims to expand the dataset, improve topology-extraction robustness, and support more complex circuit types.Source: LIMITATIONS · p. 36

DISCUSSION

The discussion presents the annotated dataset and modular pipeline as resources for further research, while describing potential educational and professional uses. It also identifies user-AI workflows and model-development directions for future study.

Research implications

  • The 1,000-diagram dataset includes annotations for six component classes, text regions, and 3,000 text samples with 68 engineering symbol charts.The authors propose it as a resource for training, evaluation, fine-tuning, and transfer learning in related technical-drawing tasks.Source: DISCUSSION · p. 36
  • The modular pipeline and YOLOv8 ablations offer research directions in detector optimization, topology modeling, resource-constrained fine-tuning, and meta-learning.The authors also propose using the human-in-the-loop interface to study error correction and user-AI workflows.Source: DISCUSSION · pp. 36–37

Practical implications

  • For education, the system can support circuit learning and assignment feedback; for professionals, it can reduce manual diagram recreation during prototyping, review, and troubleshooting.Source: DISCUSSION · p. 37

CONCLUSION AND FUTURE WORK

Sketch2Sim combines computer vision and classical image processing to convert hand-drawn RLC DC circuits into SPICE-compatible netlists and nodal solutions. The reported results include component-detection and text-recognition metrics, alongside a 94% accuracy outcome; the authors identify broader circuit coverage and analysis as future work.

CONCLUSION AND FUTURE WORK

  • The framework combines YOLOv8-small, CRNN with CTC, and classical topology techniques to produce a SPICE-compatible netlist and nodal voltage and current results.The study also presents a dataset of 1,000 handwritten circuit diagrams with component, text-region, and engineering-symbol annotations.Source: CONCLUSION AND FUTURE WORK · p. 37
  • 94% accuracy (95% CI [83.5–98.1%]) was the reported final success-rate result.Source: CONCLUSION AND FUTURE WORK · p. 37
  • The system achieves 98.9% accuracy in component detection and yields 6.47% character error rate for text recognition.Source: CONCLUSION AND FUTURE WORK · p. 37
  • The current system focuses on passive first-order RLC elements and independent sources; future extensions include broader element coverage and AC or transient analysis.The authors also identify topology extraction as an area for refinement.Source: CONCLUSION AND FUTURE WORK · p. 37
  • The annotated dataset and pipeline implementation are publicly available via Zenodo, supporting reproducibility and further research.Source: CONCLUSION AND FUTURE WORK · p. 38

ADDITIONAL INFORMATION AND DECLARATIONS

The authors report no funding or competing interests. They make the code and datasets available through supplemental files, Zenodo, and Kaggle.

Funding

Competing Interests

Data Availability

Loading 2610.28836v1…