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Wave Processing Unit: Closed-Form Matrix Synthesis for Wave Computing in Multiuser MIMO Communications

Xiaokun Teng, Yanqing Ren, Weicong Chen, Wankai Tang, Xiao Li, Shi Jin

arXiv:2610.29687v1eess.SPcs.ITmath.IT

TL;DR

Digital physical-layer matrix operations become more challenging in latency and power as antenna dimensions and data streams increase, while existing wave-domain processors are often task-specific and iteratively configured. This paper proposes a programmable planar MZI WPU with closed-form synthesis for unitary and general complex-valued operators, and applies it to multiuser downlink precoding. It reports machine-precision synthesis, faster configuration than iterative wave-computing baselines, and fewer RF chains than fully digital precoding at identical sum rate.

  • Problem

    Digital physical-layer matrix operations become more challenging in latency and power as antenna dimensions, bandwidth, and data streams increase, while existing wave processors are often task-specific and iteratively optimized.

    Source: §I · pp. 1–2

  • Method

    The paper develops a programmable planar MZI WPU with closed-form synthesis for unitary operators, extends it to general complex matrices through SVD and semi-unitary synthesis, and specializes it to multiuser downlink precoding.

    Source: §I · p. 2

  • Results

    Approximately 380× faster configuration than iterative wave-computing baselines for 64 × 64 matrices, and 87.5% fewer RF chains than fully digital precoding while sustaining identical sum rates.

    Source: §I · p. 2

  • Takeaways & Limitations

    The WPU provides a balanced configuration-and-computing latency tradeoff for real-time spatial processing.

    Source: C. Architectural Comparison and Analysis · p. 9

Abstract

from arXiv · show

Wave computing offers a compelling route to bypass the latency and energy bottlenecks of digital baseband processing. However, existing wave-domain processors rely on task-specific, non-convex iterative optimization, which incurs substantial configuration overhead and limits real-time applications. In this paper, we propose the wave processing unit (WPU), a programmable planar Mach--Zehnder interferometer (MZI) network that accelerates matrix--vector multiplications in MIMO communications. First, we model the tunable MZI element as a parameterized $2\times2$ unitary transformation, and establish a closed-form synthesis framework for the WPU that decomposes an arbitrary unitary matrix into a cascade of MZI elements arranged in a compact rectangular topology. To handle arbitrary complex-valued operators, we further extend the method through singular value decomposition (SVD) and a hardware-efficient semi-unitary synthesis, avoiding redundant hardware and reducing the compilation complexity. We then apply the WPU to multiuser downlink precoding by an efficient WPU synthesis method, and compare the proposed architecture with hybrid and wave-domain ones. Numerical results demonstrate machine-precision synthesis with negligible residuals for up to $64\times64$ operators, with approximately $380\times$ faster configuration than iterative wave computing baselines. For 64-antenna, 8-user downlink precoding, WPU requires 87.5% fewer RF chains than the fully digital architecture while achieving the same sum rate under ideal hardware. These results highlight the potential of the WPU for precise, hardware-efficient wave-domain processing with rapid configuration.

I. INTRODUCTION

The paper presents a programmable planar MZI network with closed-form synthesis for matrix operators, addressing the limited universality and iterative configuration of existing wave-domain processors. It applies this framework to MIMO precoding and reports machine-precision synthesis and fewer RF chains than fully digital precoding at equal sum rate.

I. INTRODUCTION

  • Digital implementations of repeated physical-layer matrix operations become more challenging in latency and power as antenna dimensions, bandwidth, and data streams increase.Source: §I · p. 1
  • Existing wave processors are often task-specific and iteratively optimized, limiting their universality and efficient reconfiguration for fast-varying channels.Source: §I · p. 2
  • The WPU is a programmable planar MZI network that provides closed-form synthesis from a target operator to hardware parameters for wave-domain matrix–vector multiplication.Source: §I · p. 2, Figure 1 · p. 3
  • For general complex-valued operators, SVD and semi-unitary synthesis avoid redundant completion of the larger-side singular factor, saving MZI elements and reducing compilation complexity to O(NM^2).Source: §I · p. 2
  • Approximately 380× faster configuration than iterative wave-computing baselines for 64 × 64 matrices, and 87.5% fewer RF chains than fully digital precoding with identical sum rates.Source: §I · p. 2

A. Tunable MZI Element

  • A tunable symmetric MZI uses two couplers and two phase shifters; its unitary transfer matrix controls interference between adjacent signal paths and can annihilate a target-matrix element.Source: A. Tunable MZI Element · p. 3

B. Unitary Matrix Synthesis via Rectangular MZI Network

The unitary synthesis procedure uses adjacent-path MZI transformations to eliminate matrix entries, then standardizes the resulting factors for implementation in a compact Clements rectangular network.

B. Unitary Matrix Synthesis via Rectangular MZI Network

III. NON-UNITARY MATRIX SYNTHESIS

The synthesis framework is extended beyond unitary transformations to non-unitary matrices, since many wireless communication algorithms use general complex-valued operators.

III. NON-UNITARY MATRIX SYNTHESIS

  • Many wireless communication algorithms use general complex-valued operators rather than only unitary transformations, motivating extension of the synthesis framework to non-unitary matrices.Source: §III · p. 5

A. Synthesis Procedure

For a normalized non-unitary matrix with M < N, the synthesis pipeline uses SVD to separate square-unitary, singular-value, and semi-unitary factors. It directly synthesizes the semi-unitary factor without completing it to a redundant N × N unitary mesh.

SVD-based synthesis

  • The normalized matrix is decomposed by SVD into square-unitary factors and a diagonal singular-value layer, with semi-unitary synthesis used for the larger-side factor when M < N.For a passive realization, the matrix is first divided by its largest singular value.Source: A. Synthesis Procedure · p. 5, Figure 2 · p. 6

Case 2 (M < N)

  • The method directly synthesizes an arbitrary N × M semi-unitary matrix Q satisfying Q^H Q = I_M, without first completing it to an N × N unitary, using one-sided adjacent-row eliminations.Source: A. Synthesis Procedure · p. 5

Hardware realization

  • The resulting factorization maps to two MZI networks, a singular-value scaling layer, and terminal input phase shifters.The left M × M network uses standard unitary synthesis, while the right network uses semi-unitary synthesis.Source: A. Synthesis Procedure · pp. 5–6

[W]1,1, . . . , [W]M,M

The hardware realization implements singular-value scaling with M tunable MZI scalers and handles the complementary M > N case using a semi-unitary factor alongside a unitary factor.

Scaling layer

  • The diagonal scaling layer Γ uses M parallel MZI scalers, each configured to realize a singular-value coefficient with magnitude no greater than one.The same single-channel scaler design also implements Σ in the square case.Source: [W]1,1, . . . , [W]M,M · pp. 6–7

Case 3 (M > N)

  • For M > N, the factorization uses a semi-unitary left factor and a square-unitary right factor, with no additional standardization required for the constituent MZI factors.The semi-unitary factor has dimensions M × N, and the unitary factor has dimensions N × N.Source: [W]1,1, . . . , [W]M,M · p. 7

B. Hardware and Algorithm Complexity

The semi-unitary architecture reduces hardware and compilation costs for rectangular operators by avoiding redundant synthesis of a full larger-side unitary factor.

Hardware complexity

  • For an M × N operator with M ≤ N, the proposed architecture requires NM MZI elements, with hardware scaling from O(N 2 + M 2) to O(NM).The conventional full-SVD realization uses both singular matrices as square unitary meshes.Source: B. Hardware and Algorithm Complexity · p. 7

Algorithm complexity

  • Semi-unitary compilation scales as O(NM 2), compared with O(N 3) for compiling the redundant full N × N unitary factor.The reduction is significant in strongly rectangular settings with M ≪ N.Source: B. Hardware and Algorithm Complexity · p. 7

IV. WAVE-DOMAIN MULTIUSER PRECODING DESIGN

The paper evaluates precoding as a representative physical-layer application of wave-domain matrix processing and examines its link-level benefits.

IV. WAVE-DOMAIN MULTIUSER PRECODING DESIGN

  • The study assesses link-level benefits of directly implementing matrix transformations in the wave domain using precoding as a representative physical-layer application.Matrix–vector multiplication also underlies beamforming, parameter estimation, and signal detection.Source: §IV · p. 7

A. Signal Model

The baseband processor acquires CSI and compiles the MMSE precoder once per coherence block; the configured WPU then transforms data streams into antenna signals during symbol transmission.

A. Signal Model

  • At each coherence block, the baseband processor acquires CSI, designs the MMSE precoder, and compiles it into WPU parameters for reuse during subsequent symbols.The WPU transforms the NUE data streams into Nant spatial signals in the wave domain.Source: A. Signal Model · p. 7, Figure 3 · p. 8
  • Hardware attenuation and perturbation-induced operator error model the realized WPU precoder, while a scalar normalization enforces the base-station transmit-power budget.The stated perturbations include phase-shifter quantization.Source: A. Signal Model · pp. 7–8
  • The received signal separates the desired term, thermal noise, and multiuser and hardware-induced interference; the paper then defines UE SINR and achievable sum rate.When ΔF = 0, the stated sum-rate expressions reduce to the ideal linear-precoder sum rate.Source: A. Signal Model · p. 8

B. WPU Precoder Design

The WPU compiles the MMSE precoder by exploiting the compact SVD of the downlink channel, avoiding construction and decomposition of the dense precoding matrix.

B. WPU Precoder Design

  • Rather than calculate and decompose the dense MMSE precoder, the synthesis procedure uses the compact SVD of the downlink channel to reduce compilation overhead.The direct procedure avoids the matrix inversion needed to calculate the MMSE precoder and a subsequent SVD of that precoder.Source: B. WPU Precoder Design · p. 8
  • The channel SVD supplies semi-unitary and unitary factors that are synthesized separately, with the diagonal scaling layer combined with the semi-unitary factor's phase matrix.The semi-unitary factor is synthesized using a mesh of KV standard MZI elements.Source: B. WPU Precoder Design · pp. 8–9
  • Algorithm 3 normalizes the MMSE transformation for passive hardware and outputs a global scaling factor and WPU phase configurations.The procedure computes the compact channel SVD, singular-mode gains, and normalization factor before synthesizing the unitary and semi-unitary factors.Source: B. WPU Precoder Design · pp. 8–9

C. Architectural Comparison and Analysis

The WPU combines full spatial degrees of freedom and low digital arithmetic with closed-form configuration; numerical evaluations report fast, accurate synthesis and lower MZI counts for rectangular operators.

C. Architectural Comparison and Analysis

  • The WPU achieves full spatial DoF with NRF = NUE and O(1) digital arithmetic per symbol vector, while its closed-form synthesis scales as O(NantNUE^2).The comparison describes analog and hybrid architectures as sacrificing spatial DoF, and SIM as relying on non-convex iterative optimization.Source: C. Architectural Comparison and Analysis · p. 9

A. Closed-Form Matrix Synthesis Performance

  • ~380× faster configuration is reported for 64 × 64 synthesis over balanced iterative baselines; the WPU's mean NMSEs across tested square dimensions range from 2.77×10−30 to 4.46×10−28.Table II compares accuracy, runtime, and hardware complexity; the 64 × 64 compilation times are 0.116 s for WPU and nearly 45 s for balanced baselines.Source: A. Closed-Form Matrix Synthesis… · pp. 9–10, Table II · p. 10
  • 52.4% fewer MZI elements are required for a 16×64 operator with semi-unitary rather than full-SVD synthesis, reducing the count from 2152 to 1024.The method avoids completing the right singular factor into a redundant 64×64 unitary matrix.Source: A. Closed-Form Matrix Synthesis… · p. 10

B. Downlink Multiuser Precoding Performance

The WPU matches digital MMSE sum rate in ideal-hardware downlink precoding while using fewer RF chains; iterative wave-domain baselines fall short and hardware error degrades high-SNR performance.

B. Downlink Multiuser Precoding Performance

4) Iterative Wave-Domain Baselines (SIM and PDNN):

  • At 50 dB, WPU reaches 154.65 bit/s/Hz; SIM and PDNN saturate at 97.26 and 109.92 bit/s/Hz, respectively.Hybrid beamforming retains a non-saturating slope but remains approximately 3.46 bit/s/Hz below WPU; iterative baselines incur compilation overhead two to three orders greater than WPU.Source: 4) Iterative Wave-Domain Baselines… · p. 11, Figure 6 · p. 11

C. Performance Under Hardware Impairments

  • At relative operator error ε = 0.01, WPU tracks the digital benchmark at low-to-moderate SNR; ε = 0.1 severely degrades high-SNR rates.Hardware nonidealities primarily degrade sum rate through interference leakage in the interference-limited regime, making tolerable error depend on operating SNR and acceptable rate loss.Source: C. Performance Under Hardware… · pp. 11–12, Figure 7 · p. 12

VI. CONCLUSION

  • 87.5% fewer RF chains than fully digital precoding while matching its sum rate under ideal hardware for 64-antenna, 8-user precoding.The conclusion also reports a 52.4% reduction in total MZI count relative to full-SVD synthesis for 16×64 operators.Source: §VI · p. 12

APPENDIX A PROOFS OF LEMMAS 1 AND 2

The appendices establish how MZI rotations eliminate selected matrix entries and how the resulting elimination factors reconstruct unitary and semi-unitary matrices.

APPENDIX A PROOFS OF LEMMAS 1 AND 2

  • Choosing the rotation phase and angle from the two entries being eliminated makes the targeted row or column term zero, including the stated zero-entry cases.For row elimination, the choices are ϕ = ψ1 − ψ2 and tan(θ/2) = a/b; for column elimination, they are ϕ = ψ2 − ψ1 + π and tan(θ/2) = b/a.Source: Appendix A · p. 12

APPENDIX B PROOF OF LEMMA 3

  • The Lemma 3 proof partitions the diagonal unitary into the two coordinates acted on by Gp and the unaffected diagonal entries.The local phase and angle choices reproduce the required two-coordinate block.Source: Appendix B · p. 12

APPENDIX C PROOF OF THEOREM 1

  • Adjacent-row elimination turns Q into a form with an upper-triangular unitary block, which must be diagonal; recorded rotations then reconstruct Q.The proof preserves QᴴQ = IM throughout and yields Q = LQEN,MDQ.Source: Appendix C · pp. 12–13

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