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First hardware demonstration of a continuous-state probabilistic computer with programmable energy-defined sampling

Chao Fang, Hsuan Yao Tu, Yihan He, Xiao Gong, Chin-Fu Nien, Gengchiau Liang

arXiv:2610.31339v1cs.NEcs.ET

TL;DR

Conventional probabilistic computers use binary units that cannot directly represent continuous variables, while existing continuous-computing approaches retain hardware or representation constraints. CPC uses bounded continuous CP-bits with programmable, energy-defined conditional sampling and demonstrates the framework across optimization, memory, and mixture tasks. In tested 7-bit exact factorisation, FPGA CPC reduced mean core solving time approximately 33,000-fold relative to the evaluated QUBO implementation.

  • Problem

    Binary p-bits cannot directly represent continuous variables, and encoding them with multiple binary units increases unit count and interaction complexity.

    Source: Introduction · · p. 2

  • Method

    CPC updates bounded continuous CP-bits by sampling from programmable conditional distributions determined by local energy, decoupling random-source generation from sampling.

    Source: Introduction · · p. 3

  • Results

    In the tested 7-bit exact-factorisation case, FPGA CPC reduced mean core solving time approximately 33,000-fold relative to the evaluated QUBO implementation.

    Source: Conclusion · p. 15

  • Takeaways & Limitations

    The same CP-bit update framework supports discrete constraints, continuous-variable optimization, and stochastic exploration of multiple feasible solutions.

    Source: Introduction · · p. 3, Conclusion · p. 15

    The current FPGA is slower than CPU CPC on the memory and mixture tasks, and the separate costs of its input recalculation and rejection sampling have not been profiled.

    Source: Continuous product constraints on the… · p. 8, emory recovery and continuous mixture… · p. 11

Abstract

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Probabilistic computing has proved useful for combinatorial optimization, but conventional implementations rely on binary stochastic units and sigmoid-based updates. Extending these systems to continuous variables requires binary encoding. Here we introduce a continuous probabilistic computer (CPC) whose continuous probabilistic bits sample bounded states from conditional distributions defined by local energies. Separating random-source generation from conditional sampling provides a route to using physical random sources with different native distributions. A field-programmable gate array (FPGA) prototype updates finite-precision states using digital randomness. The same framework supports product constraints, memory recovery and solution-space exploration. For the tested 7-bit factorization case, fixed-temperature FPGA CPC reduces mean core solving time approximately 33,000-fold relative to the evaluated quadratic unconstrained binary optimization software implementation. The FPGA recovers stored MNIST patterns without pretrained networks, achieving final success rates of 100%. Software CPC reaches 90% reference coverage of the feasible area in approximately 18% of the time required by restarted Adam.

Introduction ·

Binary probabilistic bits are poorly suited to optimization over continuous variables, while existing alternatives retain limits in hardware flexibility or representation. The paper introduces CPC, which uses energy-defined conditional sampling for bounded continuous variables, and demonstrates it across several computational tasks.

Introduction ·

  • Binary p-bits cannot directly represent continuous variables, and combining them to approximate each variable raises unit count and interaction complexity.Existing p-dit demonstrations have focused primarily on categorical and integer variables; g-bits use multiple binary units per continuous variable.Source: Introduction · · p. 2
  • Thermodynamic computing supports continuous-variable sampling, but target distributions typically depend on engineered physical dynamics and interactions.This motivates programmable, energy-dependent conditional updates decoupled from stochastic signal generation.Source: Introduction · · p. 3
  • CPC uses CP-bits to represent bounded continuous variables and sample from conditional distributions determined by local energy.Programmable energy functions and Ising-inspired couplings map different computational problems into a shared framework.Source: Introduction · · p. 3
  • Separating random-signal generation from conditional sampling lets CPC adapt signals with different native distributions to energy-defined updates.The framework is designed to accommodate sources such as approximately Gaussian CMOS voltage fluctuations and log-normal RRAM resistance statistics.Source: Introduction · · p. 3
  • CPC demonstrations span decimal product constraints, MNIST pattern recovery without pretrained networks, and continuous mixture decomposition with multiple feasible solutions.The FPGA prototype integrates local-energy evaluation, random-number generation, conditional sampling, and sequential node updates.Source: Introduction · · p. 3

Results

The CPC samples bounded continuous states from energy-defined conditional distributions and implements sequential updates on an FPGA. Its tests cover product constraints, memory recovery, and exploration of observation-constrained solution spaces.

Continuous states and energy-defined local updates

  • At fixed inverse temperature, sequentially sampling each node from its local conditional distribution constitutes Gibbs updating and preserves the target Boltzmann distribution.Constant, linear, convex quadratic, and cubic local energies correspond to uniform, truncated exponential, truncated Gaussian, and non-Gaussian conditional distributions.Source: Continuous states and energy-defined… · p. 5, Figure 1 · p. 5

FPGA implementation of continuous probabilistic computing

  • The FPGA uses pseudorandom candidate and acceptance variates with rejection sampling, while fixed-point arithmetic and LUT approximation implement the conditional updates.Finite precision, random-number correlations, and LUT errors can affect the implemented distribution.Source: FPGA implementation of continuous… · pp. 6–7

Continuous product constraints on the FPGA

  • For 10-bit FPGA annealing, mean accuracy was 91.59% and solution-line coverage was 99.49%; fixed-temperature FPGA CPC reduced TTS and TTC90 by factors of 6.29 and 4.04 versus fixed-temperature CPU CPC.The 7-bit exact factor pair was recovered in all tested fixed-temperature FPGA runs, with mean core time of 95.59 μs.Source: Continuous product constraints on the… · p. 8, Figure 3 · p. 10

FPGA implementation of continuous probabilistic computing

Continuous product constraints on the FPGA

  • Approximately 33,000-fold lower mean core solving time was reported for fixed-temperature FPGA CPC than for the evaluated QUBO implementation in the tested 7-bit factorization case.The ratio combines an approximately 3,000-fold CPU CPC advantage over QUBO with a further 11.1-fold reduction from FPGA implementation.Source: Continuous product constraints on the… · p. 9, Figure 3 · p. 10

emory recovery and continuous mixture decomposition

  • On the common CPU platform, CPC reached 100% final success in recall, correction, and mixture decomposition, with shorter T50 than FCLS and Adam.FCLS and Adam achieved lower final image RMSE than CPC; FPGA final success was also 100% in all three tasks, but recorded output times were longer than CPU CPC.Source: emory recovery and continuous mixture… · p. 11, Figure 4 · p. 12

Exploring observation-constrained solution spaces

  • Across Space and Line, CPU CPC reached 90% reference coverage 5.62-fold and 3.33-fold faster than Adam5000, while its final coverage was slightly lower.FPGA batches reached 90.69% and 94.63% coverage for Space and Line, but serial-equivalent timing estimates were reconstructed rather than measured batch wall times.Source: Exploring observation-constrained… · p. 13, Figure 5 · p. 14
  • An ideal parallel FPGA scenario estimated TTC90 reductions of 8.52-fold for Space and 7.45-fold for Line relative to CPU CPC, contingent on parallel hardware and measured batch timing.The estimates assume simultaneous chain starts, sufficient resources, and no collection overhead.Source: Exploring observation-constrained… · p. 13, Figure 5 · p. 14

Conclusion

The CPC uses bounded continuous CP-bit states with programmable energy-defined updates and supports optimization, memory, and continuous-state exploration. Its tests report fast factorization, complete success on three memory and mixture tasks, and software coverage of feasible regions faster than restarted Adam.

Conclusion

  • 100% final success rates for FPGA recall, correction, and mixture decomposition, with stored patterns and observations defining energies directly without a pretrained generative network.The same update framework also supports product constraints and exploration of solution spaces under partial observations.Source: Conclusion · p. 15
  • The architecture separates random-source generation from conditional sampling, providing a route to energy-defined updates using physical sources with different native distributions.The passage describes this use as possible in principle with source characterization and statistical adaptation.Source: Conclusion · p. 15
  • Approximately 33,000-fold overall ratio in the tested 7-bit exact-factorisation case for fixed-temperature FPGA CPC versus the evaluated QUBO implementation.The ratio combines a 3,000-fold CPU CPC reduction and an 11.1-fold further reduction on FPGA, which has a 95.59 μs mean core solving time.Source: Conclusion · p. 15
  • Software CPC reaches 90% reference coverage in approximately 18% and 30% of Adam5000 time for the tested region and line-segment cases, respectively.These comparisons hold under the tested resolution, tolerances, and readout rules.Source: Conclusion · p. 15
  • Across three memory and mixture tasks, CPU CPC has shorter T50 than FCLS and restarted Adam, while those baselines achieve lower final reconstruction errors and the current FPGA is slower than CPU CPC.The comparison is limited to the tested tasks and prescribed success criteria.Source: Conclusion · p. 15

ethods

The CPC defines energy over a bounded continuous state space as a sum of local terms. Sequential conditional updates use the terms involving the updated node, while fixed inputs remain unchanged and exact Gibbs updates preserve the target distribution at fixed β.

Methods

  • The model defines continuous states on a bounded domain Ω, and continuity of the energy there ensures a finite, positive normalization factor.The stated domain is Ω=∏[l_i,u_i], with l_i<u_i.Source: General energy model and local… · pp. 15–16
  • The system energy is a sum of M terms, each depending on a subvector of nodes and parameters, with terms representing node biases or interactions.Terms may share variables and parameters, and the representation does not restrict interacting-node count or polynomial degree.Source: General energy model and local… · p. 16
  • Fixed input nodes remain unchanged, define the target distribution over the remaining nodes, and exact Gibbs updates preserve that distribution at fixed β.Source: General energy model and local… · p. 16
  • For a node update, other states stay fixed and the local energy collects all terms involving that node; terms independent of its candidate value cancel from the conditional density.A multi-node interaction contributes to the local energy of each participating node.Source: General energy model and local… · p. 16
  • The conditional model retains any residual dependence beyond the cubic part, and reduces to the cubic-or-lower form only when the local energy is at most cubic in the updated variable.The degree limit applies to the updated variable, not the total degree across variables.Source: General energy model and local… · p. 16

Conditional sampling and implementations

The software implementations use different numerical routines for conditional sampling, while all use the quadratic conditional model.

Conditional sampling and implementations

State representation and connections

The CPC represents each node with a bounded continuous state and builds interactions from powers of node states. Its FPGA model retains first- and second-power couplings, yielding quadratic conditional densities.

State representation and connections

FPGA configuration and measurement

The FPGA implementation uses one CPC core per top-level design and runs at 100 MHz. Timing counters capture task execution through on-chip readout, excluding configuration and host-side operations.

FPGA configuration and measurement

  • Each top-level design instantiates one CPC core and executes one chain at a time on a KCU105 board at 100 MHz.The device is an XCKU040-FFVA1156-2-E, and the designs were implemented using Vivado 2025.2.Source: FPGA configuration and measurement · p. 18
  • State and coefficient precision varies by figure, from 10-bit fractional storage to signed 26-bit registers with 10 fractional bits.The Fig. 4 sampling path is 40 bits for recall and correction, and signed 63 bits for mixture decomposition.Source: FPGA configuration and measurement · p. 18
  • FPGA counter intervals include initial-state loading, node updates and on-chip readout, but exclude configuration, board power-up and host control or data transfer.Counters are clocked at 100 MHz, so each count corresponds to 10 ns.Source: FPGA configuration and measurement · p. 18

Product constraints and exact decoding

Product-constraint outputs are assessed using explicit validity and exact-readout rules, with first-solution costs including failed attempts. Figure 3 evaluations use task-specific cohorts and operation-count conventions.

Product constraints and exact decoding

  • First-solution costs include failed attempts, while core timings exclude setup, offline scoring and online verification or answer return.Operation counts use active-node updates for CPC and QUBO, two variable updates per two-dimensional PGD step, and candidate evaluations for Grid and Solution-line.Source: Product constraints and exact decoding · p. 18
  • All runs in the separate Fig. 3d exact-readout cohort recover the exact factor pair.The cohort includes 100 runs per CPU method and 800 per FPGA configuration.Source: Product constraints and exact decoding · p. 19
  • Fig. 3a pools 10,000 outputs from each of 800 FPGA annealing runs, while Fig. 3b,c use different run counts by method and configuration.For Fig. 3a–c, outputs are scored using the main-text validity criterion; Fig. 3d requires both the rounded factor pair and product to match the target, allowing either factor order.Source: Product constraints and exact decoding · pp. 18–19

Energy mapping for memory recovery

Memory-recovery energy combines a reconstruction residual with a coefficient-sum penalty. The coefficients remain bounded without simplex projection or normalization during node updates.

Energy mapping for memory recovery

  • The energy uses the reconstruction residual over observed positions together with a coefficient-sum penalty.The dictionary and observations are fixed, while coefficients vary within [0,1].Source: Energy mapping for memory recovery · p. 19
  • Node updates apply neither simplex projection nor normalization by the coefficient sum.For memory tasks, the residual is scaled by observation count; letter tasks use a fixed scale.Source: Energy mapping for memory recovery · p. 19
  • α and λ weight the residual and sum penalty, respectively, and β denotes inverse temperature.The coupling expansions and parameters are given in Supplementary Notes 2, 5 and 6.Source: Energy mapping for memory recovery · p. 19

emory recovery, mixture decomposition and exploration

The evaluation covers memory recall and correction, mixture decomposition, and solution-space tasks. The protocols specify fixed inputs, scoring conditions, chain schedules and output-release procedures.

emory recovery, mixture decomposition and exploration

  • Figure 4 evaluates ten recall tasks, ten correction tasks and twenty mixture tasks using fixed dictionaries, observations and initial states.CPC uses 20, 20 and 10 repeats per task, respectively; FPGA records do not establish independent random-seed replication.Source: emory recovery, mixture decomposition… · p. 19
  • Figure 5 uses identical CPU and FPGA dictionaries, queries and observation masks, with matching ideal CPC energy weights across all three tasks.Offline scoring requires finite, non-negative coefficients with a positive sum; scoring does not feed back into the chains.Source: emory recovery, mixture decomposition… · p. 20
  • For Fig. 5, CPC and Adam5000 each use ten seeds and release 2,048 outputs per run, but use different sampling and restart schedules.CPC samples 1,024 chains with two reads per chain; Adam5000 uses eight batches of 256 restarts and releases each after 5,000 steps.Source: emory recovery, mixture decomposition… · p. 20

Baselines, timing and statistics

The CPU comparisons use common inputs and scoring thresholds, while preserving method-specific objectives and readout rules. Timing boundaries and statistical units vary across figures and are specified alongside their reporting conventions.

Baselines, timing and statistics

  • CPU comparisons use common inputs and scoring thresholds but retain method-specific objectives and readout rules.Figure 4 CPC and mixture FCLS use compiled kernels; FCLS uses simplex-constrained least squares, and Adam uses different parameterisations in Figures 4 and 5.Source: Baselines, timing and statistics · p. 20
  • Figure 5 software timing includes construction, initialisation, updates and output copying, while Figures 3 and 4 measure core runtime.FPGA timing uses recorded timestamps; Figure 5 also reconstructs serial-equivalent and ideal parallel scenarios at 10 ns per cycle.Source: Baselines, timing and statistics · p. 20
  • Independent runs or task repeats—not readouts from one chain—are the statistical units; Figure 3 reports means and 95% Student t confidence intervals.Groups with runs that miss the coverage threshold retain all runs and report truncated mean times as lower bounds; no hypothesis tests were performed.Source: Baselines, timing and statistics · p. 20
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