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TACS-RF: Tool-driven Agentic Circuit Synthesis of RF and mmWave Modules

Tristan Liang, Aravind Nagulu

arXiv:2610.31882v1cs.AI

TL;DR

Existing algorithmic RF design approaches require substantial redesign for new targets, and prior LLM circuit work does not address EM- and parasitic-aware RF closure. TACS-RF connects an LLM agent to industry-standard EDA tools and applies the workflow to a sub-THz transmitter. The complete chain delivers +6.3 dBm at 246 GHz with an 11 GHz tuning range while consuming 361 mW.

  • Problem

    Earlier algorithmic RF/mmWave methods did not carry forward design reasoning and topology knowledge to new targets, while prior LLM circuit work did not address EM- and parasitic-aware RF design closure.

    Source: §I · p. 1

  • Method

    TACS-RF uses an LLM agent with prior circuit literature and direct EDA-tool access to optimize the transmitter from schematic design through layout- and EM-aware evaluation.

    Source: §I · p. 1, §II · p. 2, B. Schematic-level Circuit and… · p. 3

  • Results

    The complete chain delivers +6.3 dBm at 246 GHz while consuming 361 mW, with an 11 GHz tuning range.

    Source: B. Final Transmitter Chain Performance · p. 4

  • Takeaways & Limitations

    The complete pre-layout transmitter chain was designed from scratch in under a week; comparable future modules are estimated to take within a day when guidelines, prior designs, and reference layouts are available.

    Source: §V · p. 4

Abstract

from arXiv · show

We present the framework of TACS-RF - a Tool-driven Agentic Circuit Synthesis of RF and mmWave modules. In this framework, a large-language-model (LLM) coding agent (Claude Opus 4.8) directly drives industry-standard electronic-design-automation (EDA) tools such as Cadence Virtuoso/Spectre, Calibre, Cadence EMX, and Ansys HFSS to design RF and mmWave modules. We validate the framework through the agentic design of a 240-251 GHz sub-THz transmitter in a 90 nm SiGe BiCMOS process. The agent semi-autonomously designed the sub-blocks including a 60 GHz push-push Colpitts VCO with second-harmonic extraction, multistage differential cascode power drivers, a push-push frequency doubler, a differential bowtie antenna, and all the interstage matching networks. The transmitter chain with parasitic-extracted devices and EM-verified passives delivers +5.1 to +6.3 dBm across an 11 GHz varactor-only tuning range, phase noise of -80 to -88 dBc/Hz at 1 MHz offset while consuming a DC power of 361 mW. We describe the agent-driven design flow and the resulting division of labor between human and agent, taking a step toward a "text-to-ASIC" future for designing RF/mmWave hardware.

I. INTRODUCTION

Earlier algorithmic RF/mmWave design automation can shorten iteration but is contextless, while prior LLM circuit work does not address EM- and parasitic-aware RF design closure. TACS-RF uses an LLM agent with contextual knowledge and EDA-tool access, demonstrated on a sub-THz transmitter.

I. INTRODUCTION

  • Prior algorithmic RF/mmWave methods shortened schematic and layout iteration from weeks to days, but required optimization to be rerun largely from scratch for new targets.They did not carry forward circuit-design reasoning, topology knowledge, or engineering heuristics.Source: §I · p. 1
  • Earlier LLM methods addressed analog and mixed-signal circuits, but not the EM- and parasitic-aware co-design central to RF, mmWave, and sub-THz design closure.LLMs can reason over contextualized knowledge, including topologies, design equations, and prior solutions.Source: §I · p. 1
  • TACS-RF combines contextual knowledge from prior publications with direct control of industry-standard EDA tools for schematic design, layout, simulation, extraction, and final checks.The paper validates the framework on a sub-THz transmitter and reports reduced design time and human labor from months to a few days.Source: §I · p. 1, Figure 1 · p. 1

II. LLM–EDA TOOL INTEGRATION

The agent directly controlled the design stack through scripts, command-line interfaces, and machine-readable outputs, with human work limited to validation and integration.

II. LLM–EDA TOOL INTEGRATION

  • The agent was tasked with autonomously driving Cadence Virtuoso/Spectre, Calibre, Cadence EMX, and Ansys HFSS using supplied specifications, technology documentation, and prior circuit literature.The agent was Claude Opus 4.8 and interacted through scripts, command-line interfaces, and machine-readable simulation outputs.Source: §II · p. 2
  • Human involvement was limited to result validation, final verification, and top-chip integration.Source: §II · p. 2
  • Figure 2 summarizes the resulting agent-driven design flow.Source: §II · p. 2

A. LLM–Virtuoso Interface

The agent used Virtuoso for circuit design and simulation, and EM tools to design and evaluate passives and an antenna.

A. LLM–Virtuoso Interface

  • The Virtuoso bridge let the agent generate schematics, run Spectre simulations, inspect machine-readable results, and choose parameter updates; scripted sweeps supported rapid optimization, while cellview/Maestro supported human verification.Source: A. LLM–Virtuoso Interface · p. 2

B. LLM Control of Electromagnetic Simulators

  • EMX and HFSS/PyAEDT supported passive and antenna design: the agent iterated transformer and inductor geometries using circuit results, and generated a bowtie antenna layout and simulation setup.EMX S-parameter models were returned to Virtuoso for circuit evaluation; HFSS exported antenna matching, gain, and directivity data. Figure 3 shows a representative design guideline provided to the agent.Source: B. LLM Control of Electromagnetic… · p. 2, Figure 3 · p. 2

C. Calibre-Based Physical Verification and Extraction

The agent automated Calibre physical verification and parasitic extraction, then used extracted results to refine the transmitter’s matching networks.

C. Calibre-Based Physical Verification and Extraction

III. LLM-DESIGNED SUB-THZ TRANSMITTER

The design is a swept-frequency sub-THz transmitter with a 60 GHz push-push Colpitts VCO, 120 GHz gain stages, a push-push doubler, and an on-chip bowtie antenna. Its performance depends on device, passive, parasitic, and matching choices near the technology fmax.

III. LLM-DESIGNED SUB-THZ TRANSMITTER

  • The 240–251 GHz transmitter combines a 60 GHz push-push Colpitts VCO, differential 120 GHz gain stages, a push-push doubler, and an on-chip bowtie antenna.The design targets wide tuning, low phase noise, and nearly constant output power across the band.Source: §III · p. 2, Figure 4 · p. 3
  • Fig. 4 spans the transmitter schematic, matching and VCO results, driver-stage optimization, and two-driver-stage output power and phase noise across the varactor sweep.Panel (e) uses EM-extracted passives and RCC-extracted devices; the operating frequency is limited by the varactor tuning range.Source: Figure 4 · p. 3
  • Near technology fmax, performance depends strongly on transistor sizing and biasing, passive losses, extracted interconnect parasitics, and interstage matching.The agent followed iterative schematic-only and layout-extracted-parasitic optimization loops.Source: §III · p. 3

A. Technology and Reference-Design Setup (Step 1):

The agent used process documentation and prior designs to identify devices, limits, and circuit topologies, then characterized and co-optimized transistor sizes, bias points, and matching for the transmitter.

A. Technology and Reference-Design Setup (Step 1):

  • The agent used 90 nm SiGe BiCMOS documentation and prior sub-THz publications to identify device and passive models, bias and SOA limits, expected transistor performance, and representative topologies.Source: A. Technology and Reference-Design… · p. 3

B. Schematic-level Circuit and Matching Design (Steps 2–4):

  • Characterization sweeps of SiGe NPN BJTs informed device sizing and bias optimization for the VCO, buffer, PA stages, and frequency doubler.Interstage networks began as parameterized circuit models with Q=10 at 120 GHz and coupling coefficient k.Source: B. Schematic-level Circuit and… · p. 3
  • Schematic-level optimization found two driver stages sufficient, while a third provides additional power-gain margin against post-layout and interstage-detuning losses.The co-optimization varied driver count, device dimensions, bias conditions, and matching parameters.Source: B. Schematic-level Circuit and… · p. 3
  • Fig. 5 illustrates EM simulation using EMX for a transformer balun and HFSS for a 240 GHz antenna.The antenna results include input matching, gain, and directivity.Source: Figure 5 · p. 3

C. Layout- and EM-aware Optimization (Steps 5–7):

Layout- and EM-aware optimization replaces schematic devices and ideal matching networks with extracted transistor models and simulated passive structures, then refines the complete chain.

C. Layout- and EM-aware Optimization (Steps 5–7):

  • The agent selected human-prepared transistor layouts, ran Calibre LVS and RCC extraction, and replaced schematic transistors with extracted models.Interstage transformers were parameterized in the top two metal layers and simulated in EMX; their multiport S-parameters replaced ideal matching networks.Source: C. Layout- and EM-aware Optimization… · p. 3
  • Table I compares the design with prior sub-THz SiGe sources.Source: Table I · p. 4
  • The chain was re-centered over the target 240 GHz band and optimized for output power.Source: C. Layout- and EM-aware Optimization… · p. 4
  • The iterative layout and EM loop runs RCC extraction, passive geometry generation, EM simulation, circuit evaluation, and circuit refinement.This optimizes passive structures by their impact on the complete transmitter rather than isolated passive metrics.Source: C. Layout- and EM-aware Optimization… · p. 4

D. Top-Level Integration and Verification (Steps 8–9):

Top-level verification simulates the extracted transmitter across the VCO tuning voltage, checks transistor terminal voltages against SOA limits, and includes an HFSS-designed bowtie antenna.

D. Top-Level Integration and Verification (Steps 8–9):

  • The complete extracted transmitter was simulated across VCO tuning voltage, operating from 240–251 GHz.Matching and device parameters were optimized for large-signal matching and power delivery.Source: D. Top-Level Integration and… · p. 4
  • Every transistor’s instantaneous terminal voltages were checked against PDK safe-operating-area limits across the full tuning range.Source: D. Top-Level Integration and… · p. 4
  • The agent designed an on-chip bowtie antenna in HFSS using the foundry back-end stackup and extracted its matching, gain, directivity, and radiation patterns.The human designer would assemble the extracted active blocks, EM-extracted matching structures, and antenna into the top-level layout for final verification.Source: D. Top-Level Integration and… · p. 4

IV. POST-EXTRACTION SIMULATION RESULTS

Post-extraction results report performance at both the individual-block and complete-transmitter levels. The complete chain reaches +6.3 dBm at 246 GHz with an 11 GHz tuning range, while Table I compares its results with prior sub-THz sources.

A. Per-Block Performance

  • At block level, the VCO delivers −1.5 dBm at 123.7 GHz; the two-stage PA reaches 14.1–16.6 dB gain, +2.2 dBm OP1dB, and +8.5 dBm Psat; the doubler provides +3.4 dB conversion gain.The doubler’s reported operating point is +2.9 dBm input at 123 GHz and +6.3 dBm output at 246 GHz.Source: A. Per-Block Performance · p. 4

B. Final Transmitter Chain Performance

  • The complete chain delivers +6.3 dBm at 246 GHz while consuming 361 mW, with an 11 GHz tuning range.The tuning range is reported across the VCO tuning-voltage sweep.Source: B. Final Transmitter Chain Performance · p. 4
  • Table I compares post-extraction results with prior state-of-the-art sub-THz sources, and the authors characterize the design’s performance as highly competitive.The prior sources were provided to the Claude agent as reference designs.Source: B. Final Transmitter Chain Performance · p. 4

V. CONCLUSION

TACS-RF produced a pre-layout sub-THz transmitter chain from scratch in under a week without pre-existing files, guidelines, or documented workflows. The conclusion estimates that comparable modules could be synthesized within a day under specified conditions, while identifying EM simulation runtime as the main design-time bottleneck.

V. CONCLUSION

  • The complete pre-layout sub-THz transmitter chain was designed from scratch in under a week, without pre-existing files, guidelines, or documented workflows.The authors describe this as a highly efficient result.Source: §V · p. 4
  • With established design guidelines, prior schematics, and reference layouts as the agent knowledge base, comparable-complexity RF/mmWave modules are estimated to take within a day.This is an estimate for future designs, not the reported duration of the demonstrated design.Source: §V · p. 4
  • EM simulation runtime is the primary design-time bottleneck, and a library of pre-characterized passives is expected to reduce design time further.Source: §V · p. 4
  • The authors see promise in reducing design cycles, cost, and human effort at scale, and expect unsupervised text-to-ASIC design to become achievable in the foreseeable future.Source: §V · p. 4
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