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A Resource-Efficient and Precision-Scalable FPGA Accelerator for Spiking Neural Networks Using Minifloat Arithmetic

Ali Mehrabi, Philip C. Jose

arXiv:2610.32052v1cs.NEcs.AR

TL;DR

Conventional floating-point arithmetic can burden resource-constrained SNN hardware, motivating a precision-scalable FPGA accelerator based on parameterized minifloat. Its reusable, time-multiplexed datapath supports multiple formats; post-route E5M6 results reduce hardware cost while matching E8M23 accuracy on the validation workload.

  • Problem

    Conventional floating-point arithmetic can impose logic, register, routing, and power overhead in FPGA SNNs, while fixed-point scaling is difficult when weights and neuron states span different numerical ranges.

    Source: §I · p. 1

  • Method

    A parameterized minifloat accelerator shares pipelined arithmetic across synaptic processing and LIF/LI updates, with synthesis-time formats and unchanged system-level control.

    Source: B. Pipelined Minifloat Adder and… · p. 3, §VII · p. 5

  • Results

    E5M6 reduces CLBs by 69.2%, LUTs by 54.4%, flip-flops by 59.1%, and estimated dynamic power by 46.0% versus E8M23, while estimated Fmax rises 18.5%; both achieve 96.30% RTL accuracy.

    Source: §VII · p. 5

  • Takeaways & Limitations

    Parameterized minifloat can serve as a design-space dimension for FPGA SNN accelerators, trading hardware cost against precision without changing the system-level control architecture.

    Source: §VII · p. 5

    E4M3's reduced state resolution changes final classifications on the validation workload, despite its greater hardware efficiency.

    Source: C. Architectural Implications and… · p. 5

Abstract

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Spiking neural networks (SNNs) are well suited to event-driven edge intelligence, but the arithmetic complexity, memory footprint, and power consumption associated with conventional floating-point implementations can limit their deployment on resource-constrained hardware. This paper presents a precision-scalable and resource-efficient SNN hardware accelerator architecture based on parameterized minifloat arithmetic. The proposed architecture implements recurrent leaky integrate-and-fire (LIF) neurons and leaky-integrator (LI) readout neurons using a unified minifloat datapath whose word length and mantissa width can be configured at synthesis time. A valid-driven arithmetic subsystem employs pipelined minifloat multiplication and addition, while time-multiplexed processing enables arithmetic resources to be shared across synaptic accumulation, neuron-state updates, recurrent connections, and output processing. This organization reduces replicated arithmetic hardware and provides a scalable design approach for different SNN sizes and precision requirements. The architecture supports E8M23, E5M10, E5M6, and E4M3 formats within the same RTL framework, allowing precision, memory capacity, timing, and power to be traded without modifying the underlying neuron architecture. FPGA implementation results demonstrate that reducing minifloat precision substantially decreases arithmetic-resource utilization and estimated dynamic power, while also reducing the theoretical storage requirement of synaptic parameters. A recurrent event-based classification network is used as a hardware validation case, demonstrating that substantial precision reduction can be achieved while retaining competitive inference accuracy. The results establish parameterized minifloat computation as an effective basis for scalable, low-resource, and energy-efficient FPGA SNN accelerators.

I. INTRODUCTION

SNN hardware must represent multi-bit weights and neuron states, but conventional floating-point arithmetic can impose substantial implementation costs. The paper proposes a reusable FPGA accelerator whose minifloat precision can be scaled across formats and application constraints.

I. INTRODUCTION

  • Full IEEE 754 single precision carries logic, register, routing, and power overhead, while fixed-point scaling is difficult when weights and neuron states span different ranges.SNNs also retain dynamical state, with information represented by spike timing and sparsity,.Source: §I · p. 1
  • Minifloat treats precision as a hardware design parameter, reducing word length and mantissa while retaining exponent-based dynamic range to trade implementation cost against accuracy needs.The objective is one architecture that scales across operating points without redesigning neuron models or event and recurrent-control flows.Source: §I · p. 1
  • Reusable subsystems and a shared, time-multiplexed minifloat datapath support event handling, synaptic accumulation, recurrent processing, LIF/LI updates, readout, memory, and control.Synthesis-time parameters PBITS and PMANTISSA support E8M23, E5M10, E5M6, and E4M3 in the same RTL framework.Source: §I · pp. 1–2
  • On an XCU250 post-route design-space evaluation, E5M6 versus E8M23 reduces CLBs 69.2%, LUTs 54.4%, flip-flops 59.1%, and estimated dynamic power 46.0%, while estimated maximum operating frequency increases 18.5%.The event-driven recurrent SNN workload retained the same classification accuracy as the higher-precision RTL baseline over tested E5M10 and E5M6 configurations.Source: §I · p. 2

II. BACKGROUND AND RELATED WORK

Prior FPGA SNN work explores scalable hardware and reduced-precision computation, while this paper focuses on a unified parameterized architecture and its post-route precision scaling rather than a new quantization or training algorithm.

A. FPGA-Based SNN Hardware

  • Time-multiplexed processing, shared arithmetic, and centralized or distributed state memories are established ways to reduce hardware replication as FPGA SNNs scale.Fully connected online-trainable designs integrate learning and inference, but their hardware and memory requirements rise with network size,.Source: A. FPGA-Based SNN Hardware · p. 2

B. Reduced-Precision Floating Point for Neural Hardware

  • Prior work studies reduced-precision floating point and SNN quantization, with tolerable precision depending on network dynamics and training strategy.Examples include FP8 and mixed-precision studies –[14], reduced-precision SNN computation, quantized SNNs,, and adaptive FPGA LIF hardware.Source: B. Reduced-Precision Floating Point… · p. 2
  • This work varies floating-point datapath width while retaining the same control flow and neuron equations, emphasizing unified hardware and post-route precision scaling rather than a new quantization or training algorithm.Dedicated neuromorphic processors demonstrate state-local event-driven computation,, while FPGAs offer workload-customizable hardware.Source: B. Reduced-Precision Floating Point… · p. 2, A. FPGA-Based SNN Hardware · p. 2

III. PRECISION-SCALABLE ACCELERATOR ARCHITECTURE

The accelerator separates event scheduling, synaptic computation, neuron-state handling, readout, memory, and control into coordinated subsystems. Valid-driven scheduling advances operations only after pipelined arithmetic returns a valid result.

A. System-Level Organization

  • Events enter an event buffer and scheduler, then the synaptic engine accumulates input and recurrent contributions for the time-multiplexed LIF/LI neuron engine.Generated spikes and updated states feed state storage and recurrent processing, while output activity goes to readout.Source: A. System-Level Organization · pp. 2–3
  • The controller waits for each arithmetic output-valid indication before advancing a neuron or synapse state machine, accommodating different adder and multiplier pipeline depths.Operations launch with an input-valid pulse.Source: A. System-Level Organization · p. 3
  • Parameter memory holds weights, thresholds, and coefficients, while state memory holds membrane potential, synaptic current, and spike state; the measured design does not infer BRAM or URAM for benchmark weights.Parameters may map to on-chip memory for smaller networks or external memory for larger ones, while frequently updated state can remain near compute.Source: A. System-Level Organization · p. 3

B. Time-Multiplexed Processing

Time-multiplexing shares arithmetic across synaptic events and sequential neuron updates. Precision configuration sets minifloat width, while the custom arithmetic omits full general-purpose IEEE 754 special-value handling.

B. Time-Multiplexed Processing

  • A shared synaptic accumulator processes active input events and recurrent spikes, then common LIF and LI engines update hidden and output neurons sequentially.The design favors a clear precision-scaling baseline over maximum spatial parallelism; more processing elements can be replicated later.Source: B. Time-Multiplexed Processing · p. 3

C. Precision Configuration

  • The minifloat format assigns one sign bit, E exponent bits, and M stored-fraction bits, with exponent width derived as E = N − M − 1.The evaluated formats are listed in Table I, though the supplied caption does not provide their individual values.Source: C. Precision Configuration · p. 3, Table I · p. 3
  • The custom arithmetic is IEEE-like rather than fully IEEE 754 compliant because it is optimized for SNN inference and omits the need for complete NaN, infinity, and subnormal machinery.This is a specialized inference datapath, not a general-purpose floating-point unit.Source: C. Precision Configuration · p. 3

IV. LIF NEURON AND MINIFLOAT ARITHMETIC

The hidden LIF neuron forms a current jump and updates its membrane candidate, then spikes and resets when the candidate exceeds threshold. The output LI cell shares the membrane integration coefficient but has no threshold or reset.

A. Exact Neuron State Update

  • The hidden neuron's membrane candidate is updated from its prior membrane state and the current jump, using km = 0.1 in the evaluated model.The current jump is formed before the membrane update.Source: A. Exact Neuron State Update · p. 3
  • The synaptic-current state decays between updates.Source: A. Exact Neuron State Update · p. 3
  • A spike occurs when the membrane candidate exceeds θ; the next membrane state is zero after a spike and otherwise retains the candidate.Source: A. Exact Neuron State Update · p. 3
  • The output LI cell uses km = 0.1 and current decay coefficient 0.8, but has no threshold or reset.Hidden LIF and output LI dynamics share the minifloat domain, allowing arithmetic reuse without repeated format conversion.Source: A. Exact Neuron State Update · p. 3

B. Pipelined Minifloat Adder and Multiplier

The minifloat adder and multiplier use pipelined stages for their arithmetic operations, with explicit zero handling. Pipeline depth remains fixed across tested precisions, so changing precision alters datapath width and cost without changing the scheduler or transaction count.

B. Pipelined Minifloat Adder and Multiplier

  • The multiplier uses four stages, while the adder uses six stages for unpacking, arithmetic, normalization, and result packing.The adder also aligns exponents and truncates the fraction; the multiplier multiplies mantissas with exponent arithmetic.Source: B. Pipelined Minifloat Adder and… · p. 3
  • Explicit zero handling prevents an all-zero operand from acquiring an implicit leading one.Source: B. Pipelined Minifloat Adder and… · p. 3
  • Pipeline depths stay fixed across tested precisions, so reducing precision changes datapath width and cost without changing the scheduler or arithmetic transaction count.This keeps precision as the principal architectural variable in post-route comparisons.Source: B. Pipelined Minifloat Adder and… · p. 3

V. IMPLEMENTATION AND VALIDATION METHODOLOGY

The RTL and FPGA flow parameterize the architecture and minifloat constants, then synthesize and route each precision on the same target device. The project repository provides the materials for reproducing software-to-RTL validation and FPGA implementation.

A. RTL and FPGA Flow

  • Synthesizable Verilog is parameterized by word length and mantissa width, with format-dependent constants selected internally.The constants include 0.1, 0.9, 0.8, and the threshold.Source: A. RTL and FPGA Flow · p. 3
  • The generic accelerator architecture configures network topology, parameters, and numerical precision.Source: Figure 1 · p. 4
  • Each precision is synthesized, optimized, placed, routed, and physically optimized.Source: A. RTL and FPGA Flow · p. 4
  • All four implementations target the AMD Xilinx XCU250; estimated maximum frequency is calculated from final setup slack and the applied clock constraint.Source: A. RTL and FPGA Flow · p. 4
  • The public repository at provides the Python reference model, parameterized RTL, testbench, FPGA constraints, and Vivado Tcl scripts for reproducing the validation and implementation flow.Source: A. RTL and FPGA Flow · p. 4

B. Controlled Event-Based Validation

A recurrent event-based classifier provides a controlled validation of numerical precision effects on spike trajectories and final decisions. Its topology, data processing, trained weights, and inference schedule are held consistent across RTL precision configurations.

B. Controlled Event-Based Validation

  • The validation network has 2,450 input channels, 100 recurrent hidden LIF neurons, and four LI readout neurons, evaluated on Poker-DVS recordings accumulated into 1-ms bins.The dataset has 131 recordings, split deterministically into 104 training and 27 test recordings.Source: B. Controlled Event-Based Validation · p. 4
  • The trained network topology, temporal event bins, weights, and inference schedule are retained across all RTL precision configurations.A Python model is trained once and Norse implements the software SNN reference model.Source: B. Controlled Event-Based Validation · p. 4
  • The benchmark tests whether numerical precision changes recurrent spike trajectories and final decisions; it is not a state-of-the-art event-recognition study.Source: B. Controlled Event-Based Validation · p. 4

VI. RESULTS AND DISCUSSION

E5M6 preserves the E8M23 RTL accuracy while delivering the strongest measured hardware trade-off; E4M3 reduces hardware further but lowers accuracy. The routed comparison reports no BRAM or URAM.

B. Accuracy and Weight-Storage Trade-Off

A. Hardware Scaling

  • The routed reports list zero BRAM and URAM for all four variants, so the measured comparison characterizes the compute core rather than an integrated BRAM-resident synaptic-memory subsystem.The logical architecture includes parameter memory, but benchmark weights are not inferred as on-chip RAM in the measured implementation.Source: A. Hardware Scaling · p. 5

B. Accuracy and Weight-Storage Trade-Off

C. Architectural Implications and Limitations

E5M6 delivers the strongest measured hardware–accuracy trade-off, while E4M3's reduced state resolution changes recurrent behavior and final classifications. The conclusion presents parameterized minifloat arithmetic as a design-space dimension for FPGA SNN accelerators.

C. Architectural Implications and Limitations

  • Mantissa reduction saves logic and registers even when the controller and neuron schedule remain unchanged.The reported E5M6 results preserve E8M23 RTL accuracy, whereas E4M3 changes recurrent behavior enough to alter final classifications.Source: C. Architectural Implications and… · p. 5
  • Post-route timing depends on placement, routing, and critical-path structure as well as datapath width; accordingly, the non-monotonic Fmax behavior between E5M6 and E4M3 means the smallest format is not automatically fastest.Source: C. Architectural Implications and… · p. 5
  • E4M3's reduced state resolution alters recurrent behavior enough to change final classifications on the validation workload.E4M3 achieves 88.89% accuracy, compared with 96.30% for E8M23 RTL.Source: C. Architectural Implications and… · p. 5, §VII · p. 5

VII. CONCLUSION

  • The RTL changes precision through two format parameters without changing the system-level control architecture.The shared six-stage adder and four-stage multiplier serve time-multiplexed LIF/LI neuron and synaptic-processing operations.Source: §VII · p. 5
  • Compared with E8M23, E5M6 reduces CLBs 69.2%, LUTs 54.4%, flip-flops 59.1%, and estimated dynamic power 46.0%, while increasing estimated Fmax 18.5%; both RTL accuracies are 96.30%.The conclusion identifies this as the strongest measured trade-off on the controlled recurrent event-based validation workload.Source: §VII · p. 5

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