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PARIS: Parallel Arithmetic Reduction and Integrated Selection for MSDF Inner Products

Malik Zohaib Nisar, Ic-Pyo Hong, Dorit Merhof, Muhammad Usman

arXiv:2610.32410v1cs.AR

TL;DR

Existing MSDF accelerators serialize input terms, making inner-product latency grow with fan-in. PARIS uses parallel bit-plane reduction and shared carry-save residual selection to compute exact MSDF outputs. On two MNIST multilayer perceptrons, it substantially improves arithmetic speed and reduces arithmetic energy against a matched reused-MSDF implementation.

  • Problem

    Existing MSDF accelerators process input terms sequentially, so inner-product latency grows with fan-in, while bit-parallel approaches require more hardware resources.

    Source: §1 · p. 1

  • Method

    PARIS combines parallel bit-plane reduction with shared carry-save residual selection to compute exact inner products without serializing input terms within a tile.

    Source: §1 · pp. 1–2

  • Results

    240.44×/180.47× speedups and 98.89%/98.58% arithmetic-energy reductions for Models A/B versus a matched reused-MSDF implementation.

    Source: §4 · p. 6

  • Takeaways & Limitations

    The 784-lane INT8 core computes exact inner products in 88 cycles, independent of active fan-in within the supported tile.

    Source: §1 · p. 2, §4 · p. 6

    Projected accelerator performance assumes continuous operand delivery and excludes cross-tile accumulation and layer-transition overhead.

    Source: §2.3 · p. 4

Abstract

from arXiv · show

Existing most-significant-digit-first (MSDF) accelerators serialize input-term processing, causing inner-product latency to increase with fan-in. This paper presents PARIS, an MSDF architecture that eliminates input-term serialization through parallel bit-plane reduction and shared carry-save residual selection. For $B$-bit operands, PARIS processes $B^2$ bit-position pairs, independent of fan-in within the supported tile, while generating exact MSDF outputs. Synthesized in 45\,nm at 100\,MHz, the 784-lane INT8 core occupies 0.008701\,mm$^2$ and completes an inner product in 88 cycles. Evaluation on two MNIST multilayer perceptrons demonstrates arithmetic-workload speedups of 240.44$\times$ and 180.47$\times$ over a matched reused-MSDF implementation, reducing arithmetic energy by 98.89\% and 98.58\%, respectively. A synthesized 16-engine accelerator occupies 0.90273\,mm$^2$ and meets the 100\,MHz timing constraint. Assuming immediate weight availability, it delivers a projected throughput of 24.33\,GOPS and an estimated energy efficiency of 1,581.14\,GOPS/W at unchanged mapped power. Bias-aware ReLU detection further reduces modeled arithmetic cycles by 5.52\% and 4.86\%. A separate 256-engine RTL implementation completes Model A in 259 cycles, demonstrating output-parallel scalability.

1 Introduction

Existing MSDF accelerators serialize input terms, so inner-product latency grows with fan-in; PARIS instead processes terms in parallel within a tile while retaining digit-serial computation. Its shared residual datapath produces exact outputs, and the paper evaluates the design across core, accelerator, and ReLU workloads.

1 Introduction

  • Fully connected layers require inner products over many terms, contributing significantly to inference latency and energy consumption.Bit-parallel arithmetic offers high throughput with greater hardware resources, while bit-serial arithmetic reduces hardware complexity but takes longer; reducing datapath width does not necessarily improve energy efficiency.Source: §1 · p. 1
  • Existing reused-MSDF accelerators process neuron input terms sequentially, causing inner-product latency to increase with fan-in.This motivates processing input terms concurrently while retaining digit-serial computation.Source: §1 · p. 1
  • For B-bit operands, PARIS requires B^2 bit-position steps, independent of fan-in within the supported tile.PARIS processes input terms in parallel within each tile while evaluating operand bit-position pairs sequentially.Source: §1 · p. 1
  • PARIS combines parallel bitwise operations, population-count reduction, and shared carry-save residual selection to compute exact inner products without serializing input terms within a tile.Source: §1 · pp. 1–2
  • The bias-aware ReLU certificate identifies nonpositive pre-activations early, with bit-exact verification and modeled arithmetic-cycle savings.Source: §1 · p. 2
  • The evaluation covers 45-nm arithmetic-core performance, fan-in and precision scaling, a synthesized 16-engine accelerator, and a 256-engine RTL implementation for output-parallel scalability.Source: §1 · p. 2
  • The 784-lane INT8 core completes an exact inner product in 88 cycles.The evaluation includes matched arithmetic-core comparisons and accelerator-level analysis under a resident-weight operating assumption.Source: §1 · p. 2

2 Proposed PARIS Architecture

PARIS reduces signed activation–weight bit planes in parallel and generates exact MSDF digits through shared carry-save residual selection. For INT8, its inner-product latency is 88 cycles and is independent of active fan-in within the supported tile.

2.1 MSDF Representation and Parallel Bit-Plane Reduction

  • Across 784 lanes, parallel AND and population-count operations reduce bit planes; signed counts account for two’s-complement sign bits across B^2 bit-position steps.For INT8, B^2 is 64 steps.Source: §2.1 · p. 2

2.2 Carry-Save Residual and Shared Selection

  • A shared 5:2 compressor combines signed counts with carry-save partial-product and residual registers, while integrated selection updates residuals without full-width subtraction.The residual correction uses a constant-width digit selector for the inner product.Source: §2.2 · p. 3
  • Residual draining establishes R = 0 and D = S, yielding 26 exact signed digits for the INT8, 784-lane implementation.The initial zero digit is suppressed.Source: §2.2 · p. 3

2.3 Schedule, Tiling, and Operand Delivery

  • PARIS processes all 64 INT8 bit-position pairs in consecutive cycles; five pipeline cycles and 19 residual-drain cycles yield an inner-product latency of 88 cycles.Source: §2.3 · p. 3
  • For fixed precision and lane count, latency is independent of operand values and active fan-in up to the lane limit.Core-only execution estimates assume continuous operand delivery and exclude cross-tile accumulation and layer-transition overhead; reported core evaluation excludes storage and transfer costs.Source: §2.3 · pp. 3–4

2.4 ASIC Implementation

  • At 45 nm and 100 MHz, the PARIS core occupies 0.008701 mm2; mapped-activity power estimates exclude physical implementation effects.Mapped area is the sum of standard cells.Source: §2.4 · p. 4

2.5 MLP Workloads

  • Evaluation uses MNIST Models A (784–256–10) and B (784–200–100–10), with INT8 test accuracies of 98.04% and 98.12%.Accuracy is evaluated in integer software independently of hardware timing.Source: §2.5 · p. 4

2.6 Matched MSDF Baseline and Evaluation Metrics

  • The matched reused-MSDF baseline is an independent reimplementation; both cores use INT8, the same 45-nm library and 100 MHz, and produce exact 26-digit inner products.Network accuracy is evaluated independently using integer inference.Source: §2.6 · pp. 4–5

3 Results and Discussion

PARIS’s arithmetic-core speedups over a matched reused-MSDF design come with large arithmetic-energy reductions, while latency stays nearly independent of fan-in. The evaluation also reports a projected 16-engine result and modeled savings from bias-aware ReLU termination.

3.1 Performance and Energy Efficiency

  • At 784 lanes, INT8 latency rises only from 86 to 88 cycles as fan-in grows from 256 to 1024; INT6 and INT4 reduce latency to 58 and 36 cycles.The precision reductions also lower power.Source: §3.1 · p. 5
  • At 100 MHz, PARIS achieves 240.44× and 180.47× speedups over the matched reused-MSDF core for Models A and B, respectively.Arithmetic energy falls by 98.89% and 98.58% for the two models, despite 3.51× the cell area and approximately 2.6× the power.Source: §3.1 · p. 5
  • Bias-aware ReLU termination predicts 5.52% and 4.86% fewer serialized arithmetic cycles for Models A and B without changing predictions; these are modeled cycle savings, not measured energy savings.The certificate evaluation uses 10,000 test images per model.Source: §3.1 · pp. 5–6, Figure 3 · p. 6

3.2 Comparison with Existing Accelerators

  • For the 784–256–10 network, PARIS’s 16-engine resident-weight configuration is projected to deliver 24.33 GOPS at 100 MHz and 1,581.14 GOPS/W from 15.39 mW synthesized power, 3.46× MSDF MAC assuming unchanged average power.Source: §3.2 · p. 6
  • The synthesized 16-engine accelerator, including weight storage, arithmetic engines, requantization, and control, occupies 0.90273 mm^2 and meets 100 MHz timing with 3.96 ns positive setup slack; a separate 256-engine RTL implementation completes Model A in 259 cycles.Source: §3.2 · p. 6

4 Conclusion

PARIS parallelizes input-term processing within each tile using bit-plane reduction and shared residual selection. The conclusion reports large speedups and arithmetic-energy reductions, along with modeled ReLU cycle savings and a separate RTL scalability result.

4 Conclusion

  • Against a matched reused-MSDF implementation, PARIS achieves 240.44×/180.47× speedups and reduces arithmetic energy by 98.89%/98.58% for Models A/B.The 784-lane INT8 core computes exact inner products in 88 cycles, independent of active fan-in within the supported tile.Source: §4 · p. 6
  • Bias-aware ReLU termination reduces modeled serialized-arithmetic cycles by 5.52%/4.86% for Models A/B.The conclusion also reports a separate 256-engine RTL implementation completing Model A in 259 cycles.Source: §4 · p. 6
  • Future work will address physical implementation and integrated operand storage.Source: §4 · p. 6
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