Fast Path, Exact Path: One Library of Hardwired Operators for Streaming and Exact Canny Edge Detection on a Low-Cost FPGA

I. INTRODUCTION

• Hysteresis is the streaming obstacle: a weak pixel is an edge only when a chain of weak pixels links it to a strong one, however long.The other four Canny stages are local 3 × 3 operations suited to line-buffered pipelines.Source: §I · p. 1
• Existing FPGA compromises approximate within a fixed window, add separate connected-component hardware, or iterate a stored frame until convergence.The iterative local-rule design can require up to 82 passes on a 128 × 128 photo tile.Source: §I · p. 1
• An optimised CPU processes a stored 480 × 720 frame in 0.603 ms, but unlike the FPGA pipeline it cannot decide before the frame is complete.The CPU comparison includes an optimised multithreaded library and a single-threaded port of the authors’ algorithm.Source: §I · p. 1, §II · p. 2
• One hardwired operator library serves a fast path that decides within a few lines and an exact path that completes weak chains; the fast path never adds a false edge.The paper’s proposed system can act on the fast answer and refine it with the exact one.Source: §I · p. 1

II. BACKGROUND AND RELATED WORK

• Streaming FPGA designs typically omit hysteresis or restrict it to a local window, while exact connected-component designs use label and merge hardware separate from local operators.A recent HLS stack-based design uses a large share of block RAM.Source: §II · p. 2
• The contribution is not alternating raster sweeps themselves, but implementing them inside the shared two-clock Canny operator with left-neighbour feedback and row-above write-back.The approach builds on sequential morphological reconstruction and raster-scan propagation.Source: §II · p. 2
• No approach dominates every criterion; the paper’s comparison emphasizes that its last three approaches, two new, use one operator set.Table I covers FPGA Canny hysteresis approaches and gives pass counts for 128 × 128 pattern and photo tiles.Source: §II · p. 2, Table I · p. 2

• The two paths are assembled from the same five operators, each consuming a 3 × 3 window, and differ only in their connections and data storage.Source: §III · p. 2

A. Operator library

• Every operator consumes a 3 × 3 window and produces output two clocks later; validity, border, and address metadata travel in matched delay lines.Source: A. Operator library · p. 2
• The library implements Gaussian smoothing, Sobel gradients, non-maximum suppression, thresholding, and hysteresis; each stage forces its one-pixel frame border to zero.Sobel uses shifts, adds, and direction comparisons rather than a divider, square root, or arctangent.Source: A. Operator library · p. 2
• The paths use the operators identically except for hysteresis feedback enable fb_en; the fast path ties it to zero.Source: A. Operator library · p. 2

B. Exact path

• The exact path holds a 128 × 128 tile in eight block-RAM buffers and runs each stage as a raster pass through a shared window and selected operator.A 4-pixel halo makes each tile’s core identical to whole-image processing for the first four stages; hysteresis may cross tile boundaries.Source: B. Exact path · p. 2
• The fast path decides about 3 + K camera lines after a pixel, while the exact path uses frame buffers for true hysteresis.Source: B. Exact path · p. 3, Figure 1 · p. 3

• Any promotion procedure that only promotes weak pixels adjacent to strong ones and stops when none remain returns exactly S ∪ E, the weak pixels connected to the strong seeds.The proof establishes that every promoted pixel lies in S ∪ E and that any remaining connected weak pixel would have a strong predecessor.Source: C. In-place hysteresis · p. 3
• Both two-buffer and in-place schemes satisfy those promotion and stopping conditions, so they produce identical edge maps and differ only in pass count.Both stop after a pass with no promotions, with a 256-pass cap that no Table II tile reaches.Source: C. In-place hysteresis · p. 3
• In-place passes expose decisions made earlier in the pass and alternate forward and reverse raster order, as in,.Source: C. In-place hysteresis · p. 3
• Left-neighbour feedback promotes a weak pixel when its left neighbour was just promoted, using a one-clock loop without changing the operator’s two-clock latency.Source: C. In-place hysteresis · p. 3, Figure 2 · p. 3
• The row-above buffer is written with the pass’s decisions, so each row sees the updated row above it.A reverse pass reverses read addresses and maps writes back; promotion and the zero border are symmetric under 180-degree rotation, so the window and operators need no change.Source: C. In-place hysteresis · p. 3

D. Fast path

• K local hysteresis stages follow the camera, grayscale, Gaussian, Sobel, NMS and threshold stages in a streaming chain.Each stage performs one plain hysteresis iteration.Source: D. Fast path · p. 3
• About 3+K camera lines after a pixel arrives, its edge decision emerges from the pipeline.The stream is flushed with zero samples during vertical blanking after the frame’s last pixel.Source: D. Fast path · p. 4
• The fast path’s output is bounded by S ∪ E_K ⊆ F_K ⊆ S ∪ E, so it never reports an edge exact hysteresis rejects.After K stages, it includes weak pixels whose shortest path from a strong seed through weak pixels is at most K steps.Source: D. Fast path · p. 4
• It can miss only weak pixels more than K steps from a strong pixel, making recall—not precision—the relevant accuracy measure.Its precision relative to the exact result is 100% by construction.Source: D. Fast path · p. 4

IV. VERIFICATION METHOD

• Byte-level comparison against a software model is used for every check because a one-cycle misalignment can shift the image while leaving a plausible-looking edge map.Visual inspection is not used as the verification check.Source: §IV · p. 4
• RTL regressions exercise the exact path on eight tiles and the fast path on five 640 × 480 frames across K = 1, 2, 4, 8.The fast-path runs include camera-like gaps; the exact-path checks include both hysteresis modes.Source: §IV · p. 4
• On the board, zero of 345,600 output pixels differed from the model for the full 480 × 720 image in two-buffer mode.The designs were placed and routed for the XC7A35T-1 with a 50 MHz timing requirement.Source: §IV · p. 4

V. RESULTS

• The results combine cycle-accurate RTL simulation, camera-model system simulation, Vivado place-and-route, CPU measurements, and board testing.The full-image result was obtained on the board.Source: §V · p. 4

A. Exact path and in-place hysteresis

• 38–82 passes fall to 3–7 on pattern and photo tiles, making hysteresis 6.6–21.7× faster and complete tiles 4.5–9.9× faster.The hardest photo tile drops from 28.42 to 2.97 ms; the serpentine tile needs 3 in-place passes instead of 120 and runs 17.7× faster per tile.Source: A. Exact path and in-place hysteresis · p. 4, Table II · p. 5
• The RTL matches the model at every exact-path stage on all eight tiles in both modes, with matching pass counts.The two modes also reach the same final edge set.Source: A. Exact path and in-place hysteresis · p. 4, Figure 3 · p. 4
• Fig. 3 tracks the fraction of the final edge set found after each hysteresis pass; most edges appear early, while long chains determine the two-buffer pass count.Both modes reach the same final set.Source: Figure 3 · p. 4, A. Exact path and in-place hysteresis · p. 4
• The same algorithmic change makes the single-threaded C++ port 2.4× faster at 20/40 and 4.4× faster at 50/100.These are measured CPU times on stored images.Source: A. Exact path and in-place hysteresis · p. 4

B. Fast-path accuracy

• The fast path matches its model for every frame and K, and its misses are long weak chains that only exact hysteresis completes.The hairpin-road example shows lane markings breaking into fragments at K = 1, with most of each curve recovered at K = 8.Source: B. Fast-path accuracy · p. 5, Figure 5 · p. 5
• At thresholds 20/40, recall rises from 76.6% (K = 1) to 96.1% (K = 8); at 50/100, it rises from 38.3% to 79.9%.Table III reports fast-path recall of exact edge pixels in RTL simulation, with precision at 100% in every case.Source: Table III · p. 5, B. Fast-path accuracy · p. 5

C. Accuracy on a standard benchmark

• ODS F-measure is 0.470–0.477 for the fast path versus 0.476 for the exact path on 200 BSDS500 test images, retaining at least 98.6% of the exact score.Each detector is scored at its own best threshold, so the differences are not monotonic in K.Source: C. Accuracy on a standard benchmark · p. 5

D. Fast-path latency

• The decision arrives 3 + K camera lines after the pixel, matching the architecture’s prediction.The modeled camera delivers one line every 65.33 µs.Source: D. Fast-path latency · pp. 5–6
• Latency is independent of image content because the pipeline has no data-dependent control.Source: D. Fast-path latency · p. 6
• Latency is 262.15 µs for K = 1 and 720.63 µs for K = 8, measured from camera pixel delivery to edge decision.The system simulation uses the camera’s datasheet timing.Source: D. Fast-path latency · pp. 5–6, Table V · p. 6

E. Resources

• The fast path at K = 8 uses 1455 of 20800 LUTs, and both designs close timing at 50 MHz with positive slack.The exact path is dominated by eight tile buffers, using 29 of 50 BRAM36; its estimated power is 0.108 W versus 0.300 W for the fast path.Source: Table VI · p. 6, E. Resources · p. 6

F. Comparison with a CPU

• For the first frame pixels, the fast path decides 46–127× sooner than a frame-based program can begin at 30 frames per second.The comparison is with frame-based software; the first pixel waits 33.3 ms for the frame to arrive, while the fast-path decision takes 0.26–0.72 ms after pixel arrival.Source: F. Comparison with a CPU · p. 6
• OpenCV Canny takes 0.603 ms per stored 480 × 720 image on the 12th Gen Intel Core i5-12500H, and the CPU is faster on stored images.The CPU measurement uses 16 OpenCV threads.Source: Table VII · p. 6, F. Comparison with a CPU · p. 6

VI. DISCUSSION AND LIMITATIONS

• The fast result is always a subset of the exact result, so it never reports an edge that exact hysteresis rejects.The relationship is known exactly because both paths share the same operators and models.Source: §VI · p. 6
• Exact processing is limited to 128 × 128 tiles by block RAM, and board validation with measured power remains future work.The tile boundaries create seams; the reported CPU results also cover only one laptop processor.Source: §VI · p. 6

VII. CONCLUSION

• A common library of two-clock 3 × 3 operators serves both the streaming fast path and exact frame-buffered path on a low-cost Artix-7.The paper’s stated advantage is early, structurally fixed decisions rather than higher throughput on stored frames.Source: §VII · p. 6, §VI · p. 6
• In-place sweeps cut hysteresis from up to 82 to at most 7 passes with identical output, accelerating hysteresis 6.6–21.7× and complete tiles 4.5–9.9×.Fast decisions arrive in 262.15–720.63 µs and retain at least 98.6% of the exact path’s boundary accuracy on BSDS500.Source: §VII · p. 7