Source-linked AI summary
AnalogScout: Simulation-Efficient PVT-Aware Analog Sizing with LLM Agents
Yichen Long, Keren Zhu
TL;DR
PVT-aware analog sizing is expensive because each candidate must satisfy specifications across multiple corners, and existing optimizer- and LLM-driven flows still depend on repeated simulations. AnalogScout reuses verified designs and resolves local gm/Id sizing intent analytically, alongside global refinement and full-corner verification. Across three SKY130 OTAs, it reports 43.3% lower power than CMA-ES at equal simulation budget and reaches CMA-ES’s final power after 7.0% of that budget.
Problem
Sizing must satisfy specifications at every PVT corner, but repeated multi-corner SPICE simulations make candidate evaluation costly, and LLM agents still delegate device sizes to global optimizers.
Source: §I · p. 1, §II · p. 2Method
AnalogScout combines an elite pool of verified designs, analytical lookup-table resolution of agent-stated gm/Id goals, and global refinement under full-corner verification.
Source: §I · p. 1, §III · p. 2Results
43.3% lower power than CMA-ES at an equal 16k-simulation budget across three SKY130 OTAs, with final CMA-ES power reached after 7.0% of that budget.
Source: §I · p. 1, B. Budget Efficiency · p. 3Takeaways & Limitations
AnalogScout sizes analog circuits across PVT corners budget-efficiently by refining verified designs and resolving local sizing intent with almost no simulations.
Source: §V · p. 4The loop checks the 50 mV all-corner saturation margin only at the typical corner; future work would check saturation at all corners inside the loop.
Source: D. Generalization and Sign-off · p. 4, §V · p. 4
Abstract
from arXiv · showhide
Analog device sizing must satisfy all specifications across process, voltage, and temperature (PVT) corners to ensure tape-out success, but simulating every candidate at all corners dominates the sizing time and slows design iteration. Conventional surrogate-based optimizers search the sizing space directly, while recent large language model (LLM) agents add circuit knowledge to designs but still delegate the sizes to global optimizers. Both learn the circuit response from repeated multi-corner SPICE simulations and optimize on top of it, which becomes expensive under a limited simulation budget. Providing an agent with reusable verified designs and sizing sub-blocks analytically could save most of this budget. We propose AnalogScout, a simulation-efficient PVT-aware sizing framework driven by an LLM agent. Combining elite-design reuse, analytic gm/Id local sizing and global refinement under full-corner verification, AnalogScout reduces power by 43.3% relative to the evolution strategy CMA-ES at an equal budget of 16k simulations on three SKY130 OTAs of increasing complexity, and reaches the final CMA-ES power after 7.0% of that budget. It also attains lower power than Bayesian optimization on all three OTAs and than two re-implemented LLM-driven flows on the two OTAs where they were tested.
I. INTRODUCTION
PVT-aware sizing is simulation-intensive because every candidate must meet specifications across all corners, while existing optimizer- and LLM-based approaches still rely on repeated simulations. AnalogScout combines reuse of verified designs and analytical local sizing with full-corner verification; on three SKY130 OTAs, it reports lower power than CMA-ES at equal budget and reaches CMA-ES’s final power with a small fraction of that budget.
I. INTRODUCTION
- Each candidate requires a full multi-corner SPICE sweep because specifications must hold at every process, voltage, and temperature corner.Device sizing selects widths, lengths, and bias currents to meet gain, bandwidth, stability, and noise targets at minimum power.Source: §I · p. 1
- Existing surrogate and population-based optimizers learn circuit response from sampled simulations, while LLM agents add circuit knowledge but still delegate device sizes to global optimizers.Source: §I · p. 1
- AnalogScout’s elite pool and exact evaluation cache let the agent refine verified designs rather than repeat evaluations or restart.The LLM agent edits the design source and states gm/Id sizing intent; a fixed evaluator reuses cached results and resolves that intent analytically.Source: §I · p. 1, Figure 2 · p. 2
- A lookup-table solver resolves agent-stated gm/Id goals for sub-blocks with at most three operating-point simulations per block.Source: §I · p. 1
- 43.3% lower power than CMA-ES at an equal 16k-simulation budget on three SKY130 OTAs; AnalogScout matches final CMA-ES power after 7.0% of that budget.On the Miller and NMC OTAs, it also beats CMA-ES with twice the budget.Source: §I · p. 1
II. PRELIMINARIES
PVT-aware sizing seeks low typical-corner power while satisfying every specification at every PVT corner. The number of simulations grows with the corners evaluated, and existing approaches model or search the corner-dependent response in different ways.
II. PRELIMINARIES
- PVT-aware sizing minimizes typical-corner power subject to every measured performance meeting its specification at every process, voltage, and temperature corner.Each candidate requires |C| sets of SPICE simulations, and methods are measured by simulations consumed.Source: §II · p. 2
- Surrogate methods fit corner-dependent response models, while population-based and reinforcement-learning methods search across corners or train a shared policy.Examples include Bayesian neural networks, contextual Gaussian processes, per-corner evolution, and policies trained over all corners.Source: §II · p. 2
- Some optimizers reduce corner simulations by evaluating only current worst corners or clustering similar corners.Source: §II · p. 2
III. ANALOGSCOUT
AnalogScout assigns an LLM agent the choices of where and toward which goal to size, while deterministic tools compute sizes and verify designs. Its four phases reuse verified designs, resolve gm/Id goals analytically, restructure standard sub-circuits, and refine the best design before sign-off.
III. ANALOGSCOUT
- AnalogScout combines agent-directed sizing intent with deterministic size computation and design verification.The agent edits the netlist and chooses where and toward which goal to size; tools handle the sizing calculations and checks.Source: §III · p. 2
- Phase-Explore rewrites the netlist from the best verified designs, and Phase-Localize resolves sub-block gm/Id goals with a lookup-table solver.Source: §III · p. 2
- Phase-Restructure swaps standard sub-circuits within their families, then Phase-Refine searches globally around the best design before sign-off.Source: §III · p. 2
A. Design Representation and Verification
Designs are represented as Python netlists assembled from PDK devices and reusable or precomputed components. A fixed evaluator checks candidates at the typical corner first and then verifies passing designs across nine PVT corners; feasibility requires every specification to hold at every corner.
A. Design Representation and Verification
- The design is a Python netlist built from PDK MOSFETs, bounded resistors and capacitors, verified building blocks, and precomputed gm/Id tables.Source: A. Design Representation and… · p. 2
- A fixed evaluator checks operating point, saturation, and specifications at the typical corner, then verifies passing designs across nine PVT corners.A design is feasible only if every specification holds at every corner.Source: A. Design Representation and… · p. 2
- Designs are ranked by feasibility, violation, typical-corner power, negative margin, and area; the agent sees each failing specification’s worst corner and flagged devices.Violation is based on specification shortfall at each corner, normalized by its scale.Source: A. Design Representation and… · p. 2
B. Phase-Explore: Agent with Elite Pool
Phase-Explore reuses verified designs and caches repeated evaluations, while Phase-Localize uses gm/Id goals and device tables to size targeted blocks analytically. This keeps global multi-corner simulation focused on evaluating and improving designs.
B. Phase-Explore: Agent with Elite Pool
- The elite pool starts runs from the three best feasible designs, while an exact cache avoids re-simulating identical netlists.In development, 15.5% of evaluation requests repeated an earlier design exactly.Source: B. Phase-Explore: Agent with Elite Pool · p. 2
C. Phase-Localize: Source-Local Sizing Intent
- The agent tags a netlist block with @sized and states its sizing goal as an intent tuple for lookup-table resolution.The tuple specifies a device set, its current, and the gm/Id ratio.Source: C. Phase-Localize: Source-Local Sizing… · p. 2
- A whole-circuit operating-point simulation supplies each targeted device’s actual bias, and the gm/Id table selects minimum current meeting the stated gm floor.The solver derives width from tabulated current density and re-measures bias, using at most three operating-point simulations per block.Source: C. Phase-Localize: Source-Local Sizing… · pp. 2–3
- Precomputed device characterization avoids making a simulation-driven local optimizer compete with the agent for the multi-corner simulation budget.Phase-Localize restarts from the three best Phase-Explore designs, and every evaluated design must call an agent-placed and targeted @sized block.Source: C. Phase-Localize: Source-Local Sizing… · p. 3
D. Phase-Restructure and Phase-Refine
Phase-Restructure swaps recognized circuit structures within their families, and Phase-Refine applies bounded CMA-ES optimization to matched device groups. Sign-off requires full-PVT performance, mismatch yield, and independent measurement reproduction.
D. Phase-Restructure and Phase-Refine
- Phase-Restructure replaces recognized structures with alternatives from the same family, while Phase-Refine runs CMA-ES on matched device groups within a factor of four of their sizes.Phase-Refine restarts on stagnation; running the same engine from the initial design provides the CMA-ES baseline.Source: D. Phase-Restructure and Phase-Refine · p. 3
- Sign-off requires full-PVT feasibility, saturation with at least 50 mV margin at every corner, at least 95% typical-corner mismatch yield, and reproduced measurements.The mismatch Monte Carlo test uses N = 500, and independent reference scripts reproduce the measurements.Source: D. Phase-Restructure and Phase-Refine · p. 3
- Every benchmark specification must hold at all nine PVT corners, while the objective minimizes typical-corner power.The GF180 variants scale voltage specifications by 3.3/1.8.Source: Figure 4 · p. 3
A. Setup
Across three SKY130 OTAs, AnalogScout reaches the lowest power among evaluated methods at the same 16k-simulation budget and matches final CMA-ES power after about 7.0% of that budget. The study compares fixed-budget runs across specified benchmarks, seeds, and optimizer baselines.
A. Setup
- The study sizes three increasingly complex single-ended SKY130 OTAs and repeats the Miller OTA in GF180MCU as a test-only PDK.The SKY130 designs use VDD = 1.8 V; the GF180 variant uses 3.3 V.Source: A. Setup · p. 3
- Each method receives 16k simulations, allocated across AnalogScout’s four phases as 8k, 4k, 2k, and the remainder.The report uses confirmation seeds 4–8, five per OTA and three for GF180.Source: A. Setup · p. 3
- Baselines include CMA-ES and Bayesian optimization from the starting design, CMA-ES at twice the budget, and two LLM-proposed flows handed to global optimizers.The study tests AnalogScout against equal-budget CMA-ES, Phase-Localize against equal-budget restarts, and Phase-Explore with and without the elite pool.Source: A. Setup · p. 3
B. Budget Efficiency
- At 16k simulations, AnalogScout reaches the lowest power of all methods on every OTA and reduces power by 43.3% relative to CMA-ES.It matches final CMA-ES power after 694–1,124 simulations, about 7.0% of the budget.Source: B. Budget Efficiency · p. 3
C. Where the Budget Goes
The ablations attribute exploration efficiency to reusing verified designs, while Phase-Localize reduces simulation use for sizing but does not show a significant equal-budget power reduction over restarts. Restructuring leaves median power unchanged, and refinement contributes at most a further 2.4% reduction.
C. Where the Budget Goes
- At 8k simulations, Phase-Explore with the elite pool reaches 18.1% lower power than fresh starts only.The comparison is reported as H3 with p = 0.00022.Source: C. Where the Budget Goes · p. 3
- Reported designs meet all specifications at all nine PVT corners, and method results use five searches each except for the stated three-search groups.The NMC CMA-ES@32k entry was added after the hypotheses were fixed and is descriptive only.Source: C. Where the Budget Goes · p. 4
- Phase-Localize spends 4.3% of its simulations on sizing, versus 85.3–96.3% for a simulation-based local optimizer, and evaluates about twelve times more designs within 4k simulations.At equal budget it shows no significant power reduction over restarting from the same designs (H2, p = 0.645), so the reported claim is low simulation use rather than a power gain.Source: C. Where the Budget Goes · p. 4
- Phase-Restructure leaves median power unchanged, while Phase-Refine lowers it by at most a further 2.4%.The table reports best full-PVT-feasible typical-corner power for methods and AnalogScout phases.Source: C. Where the Budget Goes · p. 4, Table I · p. 4
D. Generalization and Sign-off
Independent re-measurement found failures among designs from every method, while AnalogScout also achieved a signed-off GF180MCU Miller design. The authors identify limits in the ablations and in the scope of the GF180 test, and outline further work on structural changes and saturation checks.
D. Generalization and Sign-off
- 46 of 156 reference cases failed independent re-measurement; 29 of AnalogScout’s 111 cases failed, as did 3 of CMA-ES’s 12, 2 of BO’s 11, and 14 of the LLM baselines’ 31.Forty failures missed the 50 mV all-corner saturation margin checked only at the typical corner; the other six exceeded a specification by at most 0.5%.Source: D. Generalization and Sign-off · p. 4
- 59.6% lower Miller OTA power than CMA-ES on GF180MCU, with the best design signed off at a 99.8% Monte Carlo yield.The GF180 test covers only the Miller OTA.Source: D. Generalization and Sign-off · p. 4
- Phase-Localize showed no significant power reduction over an equal-budget restart, while Phase-Restructure added little.Phase-Refine lowered median power by at most a further 2.4%.Source: D. Generalization and Sign-off · p. 4
V. CONCLUSION
- AnalogScout’s conclusion is budget-efficient PVT sizing by refining verified designs and resolving local sizing intent with almost no simulations.Future work will resize blocks analytically after structural changes and check saturation at all corners inside the loop.Source: §V · p. 4