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SLICE-CiM: Selective Layer-wise Inference Control Engine with Confidence-Based Early Exit for SRAM based Digital Compute-in-Memory

Pratham Sharma, Mohd Faisal Khan, Santosh Kumar Vishvakarma

arXiv:2610.37601v1cs.ARcs.NE

TL;DR

SRAM digital compute-in-memory macros reduce weight-transfer overhead, but peripheral control can still cause slice over-activation, excess accumulation, and precision-transition stalls. SLICE-CiM combines precision-aware control, confidence-based early exit, and coordinated precision transitions. On the reported CNN workload, it reaches 454.91 TOPS/W at 2b/8b and 0.8 V, a 13.33× improvement over the 8b/8b, 1.2 V baseline.

  • Problem

    Prior work largely optimizes SRAM DCIM arrays and algorithms independently, while peripheral control inefficiencies include bit-slice over-activation, excess accumulation, and precision-transition stalls.

    Source: §I · p. 1

  • Method

    The framework combines precision-aware slice activation, confidence-based early exit, and a flush-merge controller for precision transitions.

    Source: §I · p. 1

  • Results

    454.91 TOPS/W at 2b/8b and 0.8 V is a 13.33× improvement over the 8b/8b, 1.2 V baseline of 31.35 TOPS/W.

    Source: §VI · p. 5

  • Takeaways & Limitations

    The framework is validated for CNN inference workloads exploiting ReLU-induced sparsity and bounded activations.

    Source: §VI · p. 5

    Transformer extension remains future work; the paper cites lower GELU/SiLU sparsity, input-dependent attention distributions, and activation outliers that violate the |xi| ≤1 assumption.

    Source: §VI · p. 5

Abstract

from arXiv · show

Digital SRAM compute-in-memory (CIM) macros enable energy-efficient CNN inference by eliminating off-chip weight transfers; however, peripheral control logic introduces three inefficiencies: bit- slice over-activation at reduced precision (L1), unnecessary accumula- tion depth (L2), and idle precision-transition stalls (L3). To address these, we present four synthesizable peripheral blocks: a Flush-Merge Enable (FME) controller, a Confidence-Based Early-Exit (EE) module, a Precision Register with Decoder (PR/PD), and a Bit-Serial Cycle Controller (CC), co-designed to minimize switching activity, wordline overhead, and leakage. Implemented in TSMC 65-nm CMOS at 335 MHz, the peripheral framework occupies 1769.760 {\mu}m2 post-synthesis and 1982.131 {\mu}m2 post-PnR. Gate-level VCD analysis reports 6.0706 {\mu}W leakage and 288.2902 {\mu}W (post-synthesis) / 322.8850 {\mu}W (post-PnR) dynamic power, totaling 328.9556 {\mu}W (0.2402% of system power). The EE module dominates dynamic power (58.2%), while WLG dominates area (58.1%). System evaluation on MobileNetV2 (CIFAR-100) shows efficiency scaling from 31.35 TOPS/W (8b/8b, 1.2 V) to 454.91 TOPS/W (2b/8b, 0.8 V), achieving 13.33x improvement without bitcell modification or retraining. The framework targets CNN workloads exploiting sparsity, with Transformer extension as future work.

I. INTRODUCTION

The paper addresses three unresolved peripheral-control inefficiencies in SRAM DCIM and proposes coordinated control for precision-aware slice activation, confidence-based early exit, and stall-free precision transitions. Its bit-serial array uses MSB-first ordering so successive slice contributions support bounded-error early termination.

I. INTRODUCTION

  • Prior work largely optimized arrays and algorithms independently, leaving bit-slice over-activation, excess accumulation, and precision-transition stalls unresolved jointly.The paper identifies these as L1, L2, and L3, respectively.Source: §I · p. 1
  • A unified peripheral framework integrates precision-aware slice activation, confidence-based early exit, and zero-stall precision transitions.The proposed controllers target redundant activations, excess accumulation, and precision-transition stalls.Source: §I · p. 1

A. SRAM DCIM Array Specification and design methodology

  • The bit-serial MAC processes B-bit weights over B clock cycles, with MSB-first slice ordering and shift-and-add accumulation.Each slice’s scale factor is implemented as a fixed left shift in the adder-tree output path.Source: A. SRAM DCIM Array Specification and… · p. 2
  • MSB-first ordering enables confidence-based early exit because each successive slice contributes at most half the magnitude of the preceding slice.This ordering bounds the tail error when accumulation terminates early.Source: A. SRAM DCIM Array Specification and… · p. 2

B. Precision Register (PR) and Precision Decoder (PD)

The PR/PD selects the active wordline subset for each layer’s precision, while the FME controller combines boundary updates into one cycle. Together, these mechanisms address slice over-activation and precision-transition stalls.

B. Precision Register (PR) and Precision Decoder (PD)

  • The PR/PD maps a 2-bit precision mode register to an 8-bit wordline-enable vector and a 4-bit active depth, keeping inactive slice drivers static.A shadow register stores the upcoming layer’s precision mode one layer in advance.Source: B. Precision Register (PR) and… · p. 2
  • The PR occupies 51.84 µm² post-synthesis (58.06 µm² post-PnR), while the PD occupies 8.64 µm² post-synthesis (9.68 µm² post-PnR).Together, they account for 3.4% of total peripheral area.Source: B. Precision Register (PR) and… · p. 2

C. Flush-Merge Enable (FME) Controller

  • The FME controller parallelizes four mode-transition operations at the layer boundary to eliminate idle stalls.At one rising edge, it latches the accumulator output, resets the accumulator and cycle counter, and loads the next precision mode.Source: C. Flush-Merge Enable (FME) Controller · p. 2

D. Cycle Controller (CC)

The cycle controller coordinates bit-serial operations and constrains early termination to a safe slice range. The confidence-based early-exit module checks the running accumulation against a threshold, reducing unnecessary accumulation depth.

D. Cycle Controller (CC)

  • The cycle controller maintains a 3-bit synchronous counter, generates completion signals, asserts accumulation enable during valid compute cycles, and enforces the safe-exit constraint.It occupies 109.80 µm² post-synthesis (122.98 µm² post-PnR), or 6.2% of peripheral area.Source: D. Cycle Controller (CC) · p. 2

E. Confidence-Based Early-Exit Module

  • The early-exit module uses a per-layer Q8.8 threshold and permits exits only when k ≥ kmin = ⌊B/2⌋.It occupies 536.040 µm² post-synthesis (600.365 µm² post-PnR), or 30.3% of peripheral area, and consumes 167.6591 µW dynamic power.Source: E. Confidence-Based Early-Exit Module · p. 3
  • The early-exit module is the largest peripheral dynamic-power consumer, at 167.6591 µW, due to its magnitude computation and comparator pipeline.Its 16-bit magnitude computation uses two pipeline stages to meet the 335 MHz timing constraint.Source: E. Confidence-Based Early-Exit Module · p. 3

F. Wordline Driver

The wordline driver gates inactive slices at the array interface, while the early-exit analysis bounds omitted accumulation tails and constrains safe exit.

F. Wordline Driver

  • 1,028.160 µm² post-synthesis (58.1% of peripheral area) and 46.6360 µW switching power make the wordline driver the largest, highest-switching block.It broadcasts each slice's enable signal to 64 column drivers; inactive slices are held off.Source: F. Wordline Driver · p. 3

A. Formal Early-Exit Error Bound

B. Per-Layer Threshold Calibration

Per-layer confidence thresholds are calibrated offline using training images and a sweep that selects the threshold maximizing the Early-Exit Efficiency Factor.

  • Threshold calibration uses an offline forward pass on 1,000 randomly selected training images, with no test-set leakage.Source: B. Per-Layer Threshold Calibration · p. 3
  • A sweep of 32 logarithmically spaced thresholds within [Tmin, Tmax] selects the value maximizing the Early-Exit Efficiency Factor.Source: B. Per-Layer Threshold Calibration · p. 3
  • Tmax is the 95th percentile of final-slice accumulator magnitudes for each layer, and calibrated thresholds are stored as 16-bit Q8.8 fixed-point values.The quantization rounding error is negligible compared with the approximately 0.30-wide plateau in normalized threshold units.Source: B. Per-Layer Threshold Calibration · p. 3

IV. TRAINING-FREE MIXED-PRECISION ASSIGNMENT

The paper assigns layer precision with a CIM-native sensitivity metric calibrated in one forward pass, without gradient computation or weight updates. On MobileNetV2 for CIFAR-100, the assignment maps layers across INT8, INT4, and INT2.

  • The CIM-native sensitivity metric maps directly to per-slice switching activity and assigns precision through a single forward calibration, unlike HAWQ and HAQ approaches described as requiring heavier calibration.HAWQ requires Hessian trace computation and quantization-aware retraining; HAQ uses reinforcement learning with hardware-in-the-loop latency feedback.Source: §IV · p. 3
  • Layer sensitivity combines weight variability measured by coefficient of variation and post-ReLU activation sparsity, then assigns INT8, INT4, or INT2 using sensitivity thresholds.INT8 applies above SH, INT4 between SL and SH, and INT2 below SL.Source: §IV · p. 4
  • 3 INT8, 11 INT4, and 3 INT2 layers yield 4.31-bit weighted-average precision for MobileNetV2 on CIFAR-100.The assignment uses SH = 0.65 and SL = 0.35; the passage also reports thresholds α = 0.6 and β = 0.4 for the illustrated 3/11/3 split.Source: §IV · p. 4

A. Experimental Setup

The evaluation combines a full-custom 10T NOR SRAM compute-in-memory macro with RTL peripheral controls in a TSMC 65-nm implementation flow. The array and control logic are characterized and evaluated at a 335 MHz target.

  • The full-custom CIM macro uses a 64×64 array of 10T cells, combining a 6T storage core with a 4T NOR compute extension.Source: A. Experimental Setup · p. 4
  • Post-layout simulations verified 1-bit NOR multiplication and non-destructive read at 335 MHz across three stated process-voltage-temperature conditions.The conditions were TT/1.2 V/27°C, SS/1.08 V/125°C, and FF/1.32 V/−40°C.Source: A. Experimental Setup · p. 4
  • Peripheral RTL was synthesized with the TSMC 65-nm library at a 335 MHz target, with gate-level switching activity from 500 CIFAR-100 inference images used for VCD-based power analysis.Source: A. Experimental Setup · p. 4

B. Results Calculation

The peripheral framework has small area overhead relative to the CIM macro, while its dynamic power is a small fraction of system power. Area and dynamic-power burdens are concentrated in different blocks.

B. Results Calculation

  • 1769.760 µm2 post-synthesis and 1982.131 µm2 post-PnR correspond to 0.380% and 0.425% area overhead, respectively.The comparison baselines are the 19,880 µm2 macro post-synthesis and 22,265.60 µm2 post-PnR.Source: B. Results Calculation · p. 4
  • 288.2902 µW post-synthesis and 322.8850 µW post-PnR are the peripheral framework's dynamic-power measurements.Post-synthesis leakage is 6.0706 µW; total peripheral power is 294.3608 µW, or 0.2402% of system power.Source: B. Results Calculation · p. 4
  • The early-exit block accounts for 58.2% of dynamic power, while the wordline driver accounts for 58.1% of area.The wordline driver has the highest toggle component at 46.6360 µW.Source: B. Results Calculation · p. 4
  • Peripheral dynamic power remains 288.2902 µW as the array scales from 64 × 64 to 256 × 256, while array power scales with column count.The passage reports monotonic improvement in system-level TOPS/W with increasing array size.Source: B. Results Calculation · p. 4

C. System-Level Accuracy and Efficiency Scaling

On MobileNetV2/CIFAR-100, the framework's reported efficiency rises with lower precision and voltage scaling. The conclusion reports a 13.33× improvement over the 8b/8b, 1.2 V baseline without retraining or bitcell modification, and limits validation to CNN workloads exploiting sparsity.

C. System-Level Accuracy and Efficiency Scaling

  • MobileNetV2 inference on 10,000 CIFAR-100 images used thresholds α = 0.6 and β = 0.4, mapping 3 layers to INT8, 11 to INT4, and 3 to INT2.The reported average precision is 4.31; Top-1 accuracy is 68.70% versus a 70.10% baseline.Source: C. System-Level Accuracy and… · pp. 4–5
  • 454.91 TOPS/W at 2b/8b and 0.8 V is a 13.33× improvement over 31.35 TOPS/W at 8b/8b and 1.2 V.The conclusion reports this result without retraining or bitcell modification.Source: C. System-Level Accuracy and… · p. 5, §VI · p. 5
  • At 4b/8b, efficiency is 90.58 TOPS/W (2.65×); further voltage scaling to 0.8 V yields 187.25 TOPS/W.The passage attributes the efficiency scaling to precision scaling, sparsity-aware execution, and voltage scaling.Source: C. System-Level Accuracy and… · p. 5

VI. CONCLUSION

  • The 65-nm, 335-MHz peripheral framework occupies 1769.760 µm2 post-synthesis and 1982.131 µm2 post-PnR, totaling 0.2402% of system power.Its dynamic power is 288.2902 µW and leakage is 6.0706 µW.Source: §VI · p. 5
  • Validation targets CNN workloads exploiting ReLU-induced sparsity and bounded activations; Transformer extension remains future work.The conclusion cites lower GELU/SiLU sparsity, input-dependent attention distributions, and activation outliers violating the |xi| ≤1 assumption as challenges.Source: §VI · p. 5
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