Source-linked AI summary
From Natural Language to Real Schematics: An Automated Workflow for Power Electronics Schematic Synthesis
Bowen Su, Huan Chen, Jiahua Ying, Ran Ou, Weilong Chen, Li Xue, Kai Sun
TL;DR
Power-electronics schematic design requires expertise across sizing, component selection, verification, and drafting, while standalone LLMs can make engineering errors in these tasks. The paper proposes a bounded workflow combining domain knowledge, commercial evidence, and ngspice verification to produce hardware deliverables. Its demonstrations include Buck and DAB converter designs, with the Buck proposal spanning 29 physical positions.
Problem
Standalone LLMs can miscalculate power-stage sizing, hallucinate commercial parts or overlook derating, and generate circuits without physical verification.
Source: §1 · p. 2Method
The bounded workflow combines domain-knowledge-driven synthesis, evidence-backed commercial component selection, closed-loop ngspice verification, and modular control integration.
Source: §1 · p. 3, §3 · p. 4, §6 · p. 12Results
The Buck case study includes 29 physical positions across 22 unique MPNs, with 100% part-number assignment.
Source: §4.2 · p. 8Takeaways & Limitations
The framework produces verified, editable power-electronics hardware deliverables, including schematics, BOMs, netlists, and design documentation.
Source: §1 · p. 3, §6 · p. 12Passing power-stage reference simulation does not establish full-system closed-loop stability, DSP firmware validity, or electro-thermal SOA qualification.
Source: §5 · p. 12
Abstract
from arXiv · showhide
Designing power electronics converters traditionally requires intensive human expertise across topology sizing, commercial component selection, circuit simulation verification, and schematic drafting. While Large Language Models (LLMs) show promise in electronic design automation (EDA), applying standalone LLMs directly to board-level power electronics schematic synthesis suffers from severe engineering hallucinations, including inaccurate analytical sizing, fabricated or mismatched component part numbers, violated voltage derating margins, and broken topological connectivity. In this paper, we propose a Bounded Dual-Loop Automated Schematic Synthesis Framework that translates natural language specifications into verified, editable KiCad schematics and manufacturing deliverables. Our workflow integrates six stages across three functional columns: (1) requirement parsing and knowledge-driven power stage synthesis covering non-isolated (Buck, Boost) and isolated/resonant (Flyback, DAB, half-bridge LLC) topologies; (2) contract- and evidence-coordinated component selection grounded in distributor APIs and OEM datasheets, coupled with closed-loop ngspice transient verification and stress feedback; and (3) modular control hardware integration and multi-format deliverable generation featuring native KiCad netlist round-trip verification. End-to-end case studies on a 24-36V to 12V,2A Buck converter (29 positions, 83 verified terminals) and an isolated 48V to 24V, 0.5A, Dual-Active Bridge (DAB) converter (87 positions, 341 verified terminals), alongside comparative evaluations against a Vanilla LLM baseline, demonstrate that our framework improves component verification coverage from 22.2 to 98.6, nominal value consistency from 0 to 97.7, and SPICE simulation pass rates from 0 to 100.
1 Introduction
Power-electronics schematic design bridges functional requirements and physical hardware, but traditionally demands expertise across sizing, component selection, simulation, and documentation. The paper proposes an LLM-based agentic workflow that combines engineering rules and external tools to generate verified schematics and deliverables.
1 Introduction
- Customized converters across diverse voltage and power ratings are increasingly needed as application scenarios and wide-bandgap semiconductor use expand.The introduction names renewable integration, electric vehicles, industrial drives, and AI data-center power delivery as application areas.Source: §1 · p. 1
- Traditional schematic design requires engineers to select topologies, size passives, find commercial parts, verify waveforms, and compile manufacturing deliverables.The paper describes this expertise-intensive, iterative process as a bottleneck to design productivity.Source: §1 · p. 2
- Standalone LLMs can miscalculate component sizing, hallucinate parts or ignore derating, and generate circuits without physical verification.The paper identifies these as practical bottlenecks for board-level power-electronics schematic design.Source: §1 · p. 2
- The proposed workflow generates power-electronics schematics and complete engineering deliverables directly from natural-language prompts.It orchestrates the LLM with calculation modules, distributor APIs, and NGSPICE waveform analysis to refine circuit parameters against design targets.Source: §1 · pp. 2–3
2 Related Work
Prior power-electronics automation has optimized converter parameters and performance, while LLM-based hardware work has addressed other design levels. The paper positions its contribution at the intersection of board-level power electronics, commercial component evidence, and verification-in-the-loop automation.
2.1 Design Automation and AI in Power Electronics
- Earlier power-electronics automation used expert systems, metaheuristics, and surrogate models for performance optimization, while PowerSynth addressed module layout and electro-thermal optimization.LLM work such as PE-GPT and Guo et al. focused on parameter sizing or modulation, not complete supply-chain-grounded schematics and manufacturing deliverables.Source: §2.1 · p. 3
2.2 Large Language Models for Hardware and Circuit EDA
- Digital EDA work includes RTL generation systems such as ChipNeMo [8] and VerilogEval [9], while AnalogCoder [10], SPICEPilot [11], and AnalogXpert [12] target analog circuit generation.The cited circuit-level frameworks focus on low-voltage integrated CMOS circuits, unlike board-level power electronics with discrete high-voltage/current parts and derating requirements.Source: §2.2 · pp. 3–4
2.3 Tool-Augmented and Verification-in-the-Loop Agents
- Tool-augmented agents such as ReAct [13] and Toolformer [14] combine reasoning with external execution, and physical simulators support iterative engineering self-correction [10].The paper applies these principles by linking analytical sizing and distributor APIs with automated NGSPICE transient simulation.Source: §2.3 · p. 4
3 Proposed Automated Synthesis Workflow
The paper frames natural-language-to-hardware translation as a knowledge-constrained, bounded dual-loop workflow. It coordinates domain knowledge, commercial supply-chain evidence, and time-domain simulation.
3 Proposed Automated Synthesis Workflow
- The framework coordinates symbolic domain knowledge, multi-source commercial evidence, and circuit simulation rather than relying on open-loop text generation.Figure 2 presents three functional columns and distinguishes forward synthesis from diagnostic feedback pathways.Source: §3 · p. 4, Figure 2 · p. 4
3.1 System Overview and Bounded Dual-Loop Architecture
The system organizes six stages across input specification, iteration and search, and integration and deliverables. Two decision nodes govern component-evidence checks and simulation-based refinement, with bounded termination when targets pass or execution budgets expire.
3.1 System Overview and Bounded Dual-Loop Architecture
- The six-stage architecture groups parsing and knowledge-driven synthesis, component selection and SPICE verification, then control integration and deliverable consistency checks.A shared structured circuit intermediate representation supports multi-format outputs.Source: §3.1 · p. 5
- The inner loop checks that each physical component has an evidence-backed commercial part number meeting electrical ratings, refining retrieval or redesigning the topology when needed.Passing this check advances the workflow to power-stage SPICE verification.Source: §3.1 · p. 5
- The outer loop checks NGSPICE operation, output and gate-drive targets, ripple, and simulated stresses against component contracts.Excess stress triggers higher-rated part reselection; failed output or ripple targets trigger passive or modulation retuning.Source: §3.1 · p. 5
- Requirements and acceptance boundaries remain fixed, while candidate pools, design degrees of freedom, and model bindings can change during bounded repair.When verification targets are unmet at the computational, retrieval, or iteration budget limit, the system returns a best-effort design with unresolved items and diagnostic logs.Source: §3.1 · p. 5
3.2 Input Specifications: Parsing and Knowledge-Driven Synthesis
Stage 1 converts natural-language requirements into a normalized, validated constraint set; Stage 2 uses that set and engineering derating priors to synthesize power stages across five topologies.
3.2.1 Stage 1: Parsing and Constraint Modeling
- Stage 1 extracts topology, electrical ratings, switching frequency, ripple tolerances, and isolation needs, then normalizes units and validates completeness and consistency.It distinguishes mandatory constraints, preferences, and unspecified conditions in the resulting Cspec.Source: §3.2.1 · p. 5
3.2.2 Stage 2: Knowledge-Driven Synthesis
- Stage 2 combines Cspec with engineering derating priors to synthesize the power stage through three coordinated sub-modules.Sizing spans duty cycle, inductors, capacitors, transformer turns ratios, and resonant-tank parameters across five supported topologies.Source: §3.2.2 · pp. 5–6
- Buck and Boost sizing uses inductor volt-second and capacitor ampere-second balance under continuous-conduction-mode ripple constraints.The analytical sizing engine computes passive components and duty cycles.Source: §3.2.2 · p. 6
- Flyback and DAB sizing uses energy-storage and demagnetization relations or single-phase-shift power transfer, while LLC sizing targets inductive-region operation for ZVS.Isolated topologies also use literature-backed winding configurations and physical core rules; the resulting parameterized power graph carries topology connectivity, gate-driver interfaces, and a verification test plan.Source: §3.2.2 · p. 6
3.3 Iteration and Search Engine: Selection and SPICE Verification
Stages 3 and 4 select real components against explicit contracts, then simulate the power stage and route selection or stress problems back for correction.
3.3.1 Stage 3: Real Component Selection
- Stage 3 formalizes power-stage requirements as position-specific contracts covering nominal bounds, ratings, supply voltages, and interface rules.Candidate parts come from curated catalogs, the Mouser API, and OEM datasheets; normalized evidence is checked against contract requirements, package, thermal limits, frequency, and guarantee types.Source: §3.3.1 · p. 6
- Inadequate component selection triggers a query-refinement loop to Stage 3 or a redesign loop to Stage 2.The routing is governed by Decision 1.Source: §3.3.1 · p. 6
3.3.2 Stage 4: Power-Stage SPICE Verification
- Stage 4 runs nominal and fine-step transient ngspice simulations and evaluates output, ripple, and gate-drive behavior while extracting component peak and RMS stresses.The testbench supplies sources, loads, auxiliary supplies, and gate-drive modulation signals.Source: §3.3.2 · p. 6
- Electrical target violations trigger the Resize L/C pathway back to Stage 2, whereas elevated component stresses trigger Stress Feedback back to Stage 3 to update Ki and re-select affected devices.Source: §3.3.2 · p. 6
3.4 Integration and Deliverables: Control Hardware and Consistency Check
Stage 5 integrates controller hardware and standardized peripheral modules within an explicit scope; Stage 6 unifies the design in a shared circuit representation and generates deliverables, including a netlist-verified editable KiCad schematic.
3.4.1 Stage 5: Modular Control Integration
- Stage 5 configures analog PWM, digital PWM, or integrated half-bridge controllers and assembles standardized peripheral application modules.Its scope is control-hardware selection and pin-level connectivity, excluding control algorithms, DSP firmware, and closed-loop stability design; control hardware remains separate from the verified power-stage simulation model.Source: §3.4.1 · pp. 6–7
3.4.2 Stage 6: Deliverables and Consistency Check
- Stage 6 unifies verified power-stage and control hardware in a shared structured circuit IR linking topology, verified MPNs, simulation models, and datasheet evidence.It generates a design report, production BOM, SPICE netlist, and simulation and stress report.Source: §3.4.2 · p. 7
- The editable KiCad schematic is round-trip checked by exporting its native netlist and verifying 100% topological consistency against the shared circuit IR.Source: §3.4.2 · p. 7
4 Case Studies and Experimental Evaluation
The evaluation tests the workflow on Buck and DAB converters, then compares it with a one-shot Vanilla LLM baseline. Across the benchmark, the workflow improves component verification, nominal-value matching, connectivity, and simulation outcomes.
4 Case Studies and Experimental Evaluation
- The evaluation comprises end-to-end Buck and isolated DAB synthesis case studies followed by a quantitative and diagnostic comparison with a one-shot Vanilla LLM baseline.Both methods were assessed using identical ngspice testbenches and audits against distributor and OEM documentation.Source: §4 · pp. 7–8, §4.4 · p. 10
4.1 Implementation Details
- The modular Python implementation combines requirement compilation, topology synthesis, evidence-backed component selection, ngspice verification, and multi-format deliverable generation.The implementation uses a bounded stress-feedback re-selection pass, and generates editable schematics with native netlist round-trip checks through KiCad CLI.Source: §4.1 · p. 8, Table 2 · p. 8
4.2 End-to-End Case Study I: Non-Isolated Buck Converter
- The Buck case produced a 29-position hardware proposal across 22 unique MPNs and verified all 83 connected terminals against the internal circuit representation.The ngspice reference circuit passed four operating-condition checks; at low input it achieved 11.8639 V mean output and 0.0671 Vpp ripple against a 0.6 Vpp limit.Source: §4.2 · pp. 8–9, Table 4 · p. 9
4.3 End-to-End Case Study II: Isolated Dual-Active Bridge (DAB) Converter
- The DAB case expanded a 57-position power-stage BOM to 87 physical positions across 20 unique MPNs, with native KiCad round-trip verification confirming 341 of 341 connected terminals.Its commercial transformer winding configuration realizes the required Ns/Np = 0.5 turns ratio; the nominal simulation produced 22.7423 V mean output, within the ±10% open-loop reference tolerance band.Source: §4.3 · pp. 9–10, Figure 3 · p. 10
5 Discussion and Limitations
The discussion presents progress from plausible part numbers to traceable, executable engineering artifacts, while identifying scope boundaries in optimization, verification, and evaluation.
5 Discussion and Limitations
- The selection engine prioritizes provenance, rating compliance, and connectivity over global cost, volume, or efficiency optimization, sometimes choosing components rated 7.8× to 16.1× above minimum derated thresholds.The authors describe these components as electrically safe for functional prototyping and plan multi-objective cost, footprint, and switching-loss ranking.Source: §5 · p. 12
- Power-stage reference simulations use parameterized behavioral semiconductor models and do not establish full-system stability, firmware validity, or electro-thermal SOA qualification.Modular controller hardware is synthesized separately for schematic connectivity.Source: §5 · p. 12
- Some specialized passive positions may remain UNKNOWN when local datasheet evidence is incomplete, and the two-case comparison leaves larger-query and multi-turn-baseline evaluation for future work.The Buck inductor is cited as an example of a position lacking strict current-saturation evidence.Source: §5 · p. 12
6 Conclusion and Future Work
The framework synthesizes power-electronics schematics and engineering deliverables from natural-language specifications. In two converter demonstrations, it improved verification and simulation metrics over a one-shot Vanilla LLM baseline, with further optimization, verification, control, and layout extensions planned.
6 Conclusion and Future Work
- Component evidence verification rose from 22.2% to 98.6%, datasheet nominal-value consistency from 0.0% to 97.7%, and SPICE simulation pass rates from 0.0% to 100.0% versus a one-shot Vanilla LLM baseline.The demonstrations produced 100% connectivity-verified schematics for a 24–36 V to 12 V/2 A Buck and an isolated 48 V to 24 V/0.5 A DAB.Source: §6 · p. 12
- The framework coordinates domain-knowledge-driven synthesis across five topologies, evidence-backed commercial component selection, ngspice verification with stress feedback, modular control hardware, and KiCad netlist round-trip verification.It generates synchronized design reports, production BOMs, SPICE netlists, and connectivity-verified schematics.Source: §6 · p. 12
- Future work targets Pareto-optimal component selection using pricing, footprint, and loss metrics, alongside vendor-specific nonlinear SPICE models for SOA and soft-switching qualification.The cited loss figure-of-merit is RDS(on) × Qg.Source: §6 · p. 12
- The planned extension adds compensator sizing and digital-control firmware generation, and couples custom magnetic design with automated KiCad PCB layout synthesis.The goal is to connect schematic verification with parasitic-aware physical implementation.Source: §6 · p. 12