Source-linked AI summary
How to build a 300 bit, 1 Giga-operation quantum computer
Andrew M. Steane
TL;DR
The paper considers how a trapped-ion computer could be designed for a substantial quantum computation using laser-control methods. It combines ion-chip hardware with fault-tolerant encoding and estimates a 10 kHz logical gate rate for a 10^9-operation computation. The design also identifies practical limits on scaling and speed.
Problem
The paper asks how to design a trapped-ion computer for 10^9 logical operations on 300 logical qubits.
Source: §1 · p. 4Method
The design combines trapped-ion gates and transport with concatenated decoherence-free and [[127, 29, 15]] CSS error-correcting encodings.
Source: §2 · pp. 6–8Results
The design estimates a logical gate rate of approximately 10 kHz and about 30 hours to complete O(10^9) operations.
Source: §1 · p. 4Takeaways & Limitations
The design identifies photon scattering during optical gates and ion movement through chip channels as main speed constraints, with faster operation potentially gaining several orders of magnitude.
Source: §1 · p. 4, §3 · p. 10Further increasing the gate rate would ultimately require abandoning optical control and measurement, while electronic methods expose the qubits to more complex decoherence processes.
Source: §3 · p. 10
Abstract
from arXiv · showhide
Experimental methods for laser-control of trapped ions have reached sufficient maturity that it is possible to set out in detail a design for a large quantum computer based on such methods, without any major omissions or uncertainties. The main features of such a design are given, with a view to identifying areas for study. The machine is based on 13000 ions moved via 20 micron vacuum channels around a chip containing 160000 electrodes and associated classical control circuits; 1000 laser beam pairs are used to manipulate the hyperfine states of the ions and drive fluorescence for readout. The computer could run a quantum algorithm requiring 10^9 logical operations on 300 logical qubits, with a physical gate rate of 1 MHz and a logical gate rate of 8 kHz, using methods for quantum gates that have already been experimentally implemented. Routes for faster operation are discussed.
1 Overview
The overview specifies a trapped-ion quantum-computer design sized for 10^9 logical operations on 300 logical qubits, with its encoding and gate rate chosen to support repeated quantum error correction. It outlines the chip, laser, and control requirements and assesses their feasibility against demonstrated techniques and available fabrication capabilities.
1 Overview
- The ion chip combines 160,000 individually controlled electrodes with hyperfine-state qubits, voltage-driven ion transport, Raman gates, and fluorescence readout.The design uses an external optical system and approximately 990 laser beam pairs; integrating that system onto a second chip would reduce construction scale and power requirements.Source: §1 · pp. 3–4
- 10^9 logical operations on 300 logical qubits define the benchmark, chosen to comfortably outperform classical computers on suitably chosen algorithms.The paper notes that one such computer would not factor numbers of cryptographic interest, while quantum algorithms for eigenvalue problems, spin systems, and quantum chemistry are predicted to outperform classical computers at 50–100 qubits.Source: §1 · p. 4
- Approximately 10 kHz logical gates and about 30 hours for O(10^9) operations follow from the [[127, 29, 15]] CSS code and concatenated two-qubit decoherence-free encoding.The design targets gate noise of 10^-4; its logical rate is limited by the physical gate rate, with photon scattering and ion transport identified as the main speed constraints.Source: §1 · p. 4
1.1 Feasibility
- The design uses 20 µm vacuum channels and roughly 1 µm electrodes, dimensions close to those implemented in ion traps and arrays.The major new ingredient is approximately 160,000 electrodes and around 1,000 parallel operations, requiring integrated control circuitry because there is insufficient room for external wiring.Source: §1.1 · pp. 4–5
- The proposed measurement and gate techniques had been demonstrated, while the design assumes laser power and stability sufficient to keep several gate-error contributions below 10^-4.Raman beam-path differences must remain stable to a few nanometres during a gate pulse; electrical noise must likewise preserve ion-position stability during phase gates.Source: §1.1 · p. 5
- A physical gate rate of about 1 MHz is the main limitation on the logical gate rate.The overview cautions that classical control must not be assumed to operate so quickly that it becomes the feasibility bottleneck itself.Source: §1.1 · p. 6
2 Methods
The design combines pair-encoded qubits and a block code with ion transport, laser gates, fluorescence readout, and repeated error correction. Its estimated physical-gate stages take similar time, while scattering, heating, and hardware demands constrain the operating choices.
2 Methods
- 290 logical qubits use 58 additional workspace qubits, with pair-encoded p-bits protected from joint phase noise and then encoded in a [[127, 29, 15]] CSS code.Each pair stores |0⟩ as |01⟩ and |1⟩ as |10⟩.Source: §2 · p. 6
- Recovery errors are estimated using a crash probability per block, with larger single-bit and measurement errors tolerable than two-bit gate errors because recovery uses more two-bit gates.The memory quality factor compares p-bit decoherence time with the time for a controlled operation between p-bits initially separated by about 10 p-bits.Source: §2 · p. 6
- Two physical measurements per recovery set a lower bound on logical-gate time unless extra ancillas are prepared in the background; fluorescence readout targets error below 10^-3 with a mean count of at least 10.The assumed detector threshold is 2 counts and combined collection and detection efficiency is 0.02.Source: §2 · p. 6
- Photon-scattering infidelity combines Raman scattering and motional heating, while the estimate assumes leaked population can be reclaimed cheaply and neglects gross-structure levels when ε_s is not too small.The operating detuning and laser intensity are chosen to keep scattering error below 10^-4 per gate.Source: §2 · p. 7
- A gate between separated p-bits uses split, move, recombine, cool, and operate; cooling to n̄ = 0.5 at η = 0.07 targets thermal infidelity of 5 × 10^-5.For linearly arranged qubits, the mean separation of bits requiring gates is 22 bits; a rectangular ancilla arrangement reduces communication distance.Source: §2 · pp. 8–9
- Room-temperature heating requires ρ ≥ 5 µm under the stated field condition, while the design adopts ρ = 10 µm for transport and splitting to balance speed and heating.The split time is constrained by electrode breakdown and scales almost linearly with electrode distance; gate zones place electrode surfaces 2 to 10 times farther away.Source: §2 · pp. 8–9
- 1.2 µs for Cd and 1.08 µs for Ca; the five physical-gate stages take similar time, and logical gate rate is limited by physical gate rate rather than measurement time.The adopted τp ≃ 0.5 µs saves laser power without much overall speed cost.Source: §2 · pp. 8–9
- The ion chip uses about 160,000 electrodes and 990 parallel zones; the estimated laser power is about 440 W for Cd+ and 100 W for Ca+ at the specified intensity.The beams have a 4 µm diameter, and pulses on different ion pairs can be separated in time to reduce instantaneous power when τp < τg.Source: §2 · p. 9
3 Faster, larger, noisier
The paper outlines ways to increase speed, tolerate more noise, or reduce measurement time through changes in resources, encoding, and gate techniques. These improvements can gain several orders of magnitude in speed or make the machine more robust, while replacing optical control with electronic methods trades away optical advantages.
3 Faster, larger, noisier
- Ancilla preparation can raise logical gate speed by up to about 100-fold, at the same factor increase in ions, traps, and laser beams.The gain continues until recovery time is similar to gate time.Source: §3 · p. 10
- Scaling physical bits without increasing logical bits can raise the noise threshold with a different QEC encoding, though the threshold increases slowly with machine size.For γ < 0.003, the rough rule of thumb is N ∝ γ^2.5.Source: §3 · p. 10
- Parallel majority-vote measurement can reduce measurement time by coupling a p-bit to additional ions, provided controlled-not operations are fast relative to measurement.Source: §3 · p. 10
- Fast pulses and higher trap frequencies can reduce phase-gate and cooling time, but require greater laser detuning and power to counter photon scattering.Smaller electrode distance ρ can then reduce split and move time.Source: §3 · p. 10
- The proposed improvements could gain several orders of magnitude in speed or increase robustness; electronic ion–electron control would sacrifice optical advantages and expose electrons to more complex decoherence processes.Optical methods are described as insensitive to electromagnetic field noise and fully switchable off.Source: §3 · p. 10