Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain

Motivation

• The brain’s scale and efficiency make real-time, detailed human-scale simulation impractical for conventional computers, motivating brain-inspired hardware [3].The brain uses over 100 billion neurons and 100 trillion synapses; mouse-scale simulation can consume 40,000 times more power and run 9000 times slower than the brain.Source: §1 · p. 2

Neuromorphic computing

• Silicon-neuron hardware emulates neural electrophysiology directly, enabling energy-efficient, real-time large-scale neural networks whose speed can be independent of neuron count or coupling.Silicon neurons are hybrid analog/digital VLSI circuits that emulate real neurons and synapses rather than relying on general-purpose computer simulations.Source: §1 · p. 2

Applications

• Neuromorphic processors are being developed for real-time recognition applications and emerging technologies including autonomous cars, drones, and brain-machine interfaces [5][6][7].Commercial examples include biometric and touchpad systems, CMOS imagers, asynchronous image sensors, artificial retinas, and dynamic vision sensors –.Source: §1 · pp. 2–3

Advantages

• Massively parallel, co-localized-memory neuromorphic processors can reduce the von Neumann bottleneck, power consumption, silicon area, and bandwidth requirements while supporting pattern recognition and autonomous agents –.Mixed-signal processors also provide additional computational complexity relative to pure digital solutions.Source: §1 · p. 3

Scope

• The review covers neural processors spanning current-mode, sub-threshold, voltage-mode, and switched-capacitor neuron and synapse designs, emphasizing each system’s strengths and potential applications.The systems use different neural design strategies and synapses.Source: §1 · p. 3

2.1 MNIFAT: (Mihalas-Niebur and Integrate-and-Fire Array Transceiver)

• MNIFAT integrated 2040 Mihalas-Niebur neurons capable of operating as 4080 leaky integrate-and-fire neurons in 0.5 µm CMOS at 5 V.Each I&F neuron occupied 1495 µm2, and the array dissipated 360 pJ per synaptic event.Source: §2.1 · p. 4

2.1.1 Neural array design

• The MNIFAT design shares one membrane synapse and soma across the array, uses an off-chip LUT for reconfigurable connections, and routes address-events through shared row and column buses.This sharing maximizes density, reduces power and process-variation mismatch, and eliminates the need for an output arbiter/transmitter.Source: §2.1.1 · pp. 4–5
• Each supercell contains two M-N neurons or four independent leaky I&F neurons, with event-selected cells buffering membrane and threshold voltages through a router.A comparator emits an event when membrane voltage exceeds threshold; the maximum input event rate is ~1 MHz, with speed traded for low power and area.Source: §2.1.1 · p. 5

2.1.2 Mihalas-Niebur(M-N) neuron model and circuit implementation

• The modified CMOS M-N implementation omitted internal induced-spike currents and set reset voltage equal to resting potential, reducing model generality while retaining Eq. (9)'s biologically relevant spiking behavior.The circuit models membrane and adaptive-threshold dynamics with switch-capacitor synapse and threshold-adaptation elements.Source: §2.1.2 · p. 6

2.1.5 Results

• 668.9 I&F neurons/mm2 were achieved, compared with 416.7 in and 387.1 in, while each cell used 62.3% of 's area.The array also consumed 360 pJ per synaptic event at 5 V and estimated ~14.4 pJ at 1.0 V; the 1.0 V value was simulation-validated.Source: §2.1.5 · pp. 8–9, Table 1 · p. 8, Table 2 · p. 9
• At a 1 MHz input rate, MNIFAT showed mean output-to-input event ratios of 0.0208 ±1.22e-5 for M-N neurons and 0.0222 ±5.57e-5 for I&F neurons, with significantly less deviation than.Shared synapse, comparator, and threshold-adaptation circuitry confined mismatch primarily to devices within each neuron cell.Source: §2.1.5 · p. 8, Table 1 · p. 8

2.2 HiAER-IFAT: Hierarchical Address-Event Routing (HiAER) Integrate-and-Fire Array Transceivers (IFAT)

• HiAER-IFAT extends AER routing with a multiscale tree hierarchy for dynamically reconfigurable long-range connectivity alongside locally dense and globally sparse synaptic communication,.IFAT arrays support up to 65k neurons per chip and continuous-time analog membrane dynamics down to 22 pJ/spike.Source: §2.2 · p. 9, Figure 4 · p. 10
• HiAER-IFAT energy efficiency is primarily constrained by external memory access for sparse synaptic-table lookup, motivating vertically integrated memristor synapse arrays and a targeted sub-pJ/spike system efficiency [32],.The architecture also supports event-driven contrastive divergence and biologically inspired spike-timing-dependent plasticity for generative and Bayesian learning,.Source: §2.2 · p. 10

3 DeepSouth

• The DE5 prototype simulated 20 million–2.6 billion LIF neurons in real time and 100 million–12.8 billion at five times slower than real time.The latter represented the maximum network size on the selected FPGA board because of memory limitations.Source: §3 · p. 11

3.1.1 Modular structure

• The emulator uses programmable 100-neuron minicolumns grouped into configurable hypercolumns containing up to 128 minicolumns, with hierarchical connections at hypercolumn, minicolumn, and neuron levels.Each minicolumn supports up to eight programmable neuron types, while the architecture stores parameters and connections in on-chip memory rather than point-to-point lookup tables.Source: §3.1.1 · pp. 11–12, §3 · p. 11

3.1.2 Emulating dynamically

• Time multiplexing maps one physical 100-neuron minicolumn onto up to 200k time-multiplexed minicolumns in real time and 1M at five times slower than real time.Each time-multiplexed minicolumn is updated every millisecond in real time or every 5 ms in the slower mode.Source: §3.1.2 · p. 12

3.1.3 Hierarchical communication

• Hierarchical event communication stores connection types and generates addresses on the fly, while spike-count events reduce the communication bottleneck for large-scale simulations.One minicolumn can reach up to 16 hypercolumns, or 200k neurons, with configurable 1–16 ms axonal delays.Source: §3.1.3 · p. 12

3.2 Hardware implementation

• The scalable hardware architecture combines a neural engine, Master, off-chip memories, and serial interface, and can target standalone or multiple parallel FPGA boards.The neural engine contains minicolumn, axon, and synapse arrays; off-chip memory stores time-multiplexed neural states and events, increasing flow-control complexity.Source: §3.2 · p. 13, Figure 6 · p. 13

3.2.1 Minicolumn array

• The minicolumn array integrates weighted excitatory and inhibitory events with leaky neuron dynamics, while the axon array implements programmable delays through two-phase DDR event storage and retrieval.The synapse array applies synaptic weights and destination addresses, leaving exponential decay to the postsynaptic-current generator.Source: §3.2.1 · p. 14, §3.2.2 · p. 14, §3.2.3 · p. 14

3.2.4 Master

• The Master coordinates neural-engine modules, memory-bus sharing, external input/output, and instruction decoding to prevent event loss or deadlock and regulate module timing.The external interface outputs individual neuron spikes and minicolumn events while configuring parameter lookup tables and system registers.Source: §3.2.4 · p. 15

3.3 Programming API

• A Python API similar to PyNN lets users specify neurons, connections, and network topologies, rapidly configure models, and monitor spikes across hypercolumns.Full PyNN script support and interactive visualization were identified as future work.Source: §3.3 · p. 15

4 BrainScaleS

• BrainScaleS directly emulates neuron and synapse equations, with electronic circuits acting as physical models whose electrical quantities represent the model variables.The circuits implicitly solve the associated differential equations through their physical dynamics.Source: §4 · p. 15
• The first-generation system implements the Adaptive Exponential Integrate-and-Fire Model and targets 10^4 acceleration, making firing rates and communication rates 10^4 higher than biological values.Model parameters are linearly scaled to match electronic-circuit operating conditions, including an approximately 500 mV membrane-voltage range.Source: §4 · p. 15
• Continuous-time analog implementation of complete neurons and synapses consumes substantial silicon area, so networks larger than a few hundred neurons require multiple chips.Source: §4 · p. 15
• Wafer-scale integration addresses the high inter-ASIC bandwidth required by acceleration, using an uncut wafer integrating 384 neuromorphic chips.Figure 8 shows the wafer module and its communication-board and heat-sink configuration.Source: §4 · p. 16, Figure 8 · p. 16

4.1 HICANN ASIC

• HICANN integrates a mixed-signal analog network core, digital communication logic, and serial wafer links, with Layer 1 time-multiplexing supporting fan-in above 10k presynaptic neurons.The current system uses the third HICANN version; a 65 nm second generation adds hybrid plasticity and high-speed membrane-voltage readout.Source: §4.1 · pp. 16–18, Figure 9 · p. 17

4.1.1 Neuron Circuits

• HICANN implements AdEx neurons by combining up to 64 membrane circuits, each with 220 synapses, shared spike generation, and 23 floating-gate calibration parameters.Synaptic circuits use current-mode integration with adjustable conductance decay, rise time, and conductance-to-current scaling.Source: §4.1.1 · pp. 18–20, Figure 11 · p. 19

4.1.2 Synapse array and drivers

• The synapse array provides address-matched 4-bit weights, row-wise gmax scaling, variable-duration presynaptic activation for short-term plasticity, and correlation circuits for STDP.Each synapse driver controls two adjacent rows, while individual rows select excitatory or inhibitory membrane inputs.Source: §4.1.1 · p. 19, §4.1.2 · p. 21

4.2 Communication infrastructure

• The analog network core routes 220 synapse-driver L1 signals through surrounding and central metal-layer connections constrained by the synapse array layout.Vertical L1 lines use metal6, while horizontal lines use the layer beneath; available routing space is around and within the analog network core.Source: §4.2 · p. 21
• 640 Gbits−1 total bandwidth is provided by 640 differential wires, with each wire pair supporting up to 2 Gbits−1.The network uses 64 horizontal lines in the center and 128 on each side of the analog network core.Source: §4.2 · p. 21

4.2.1 Wafer-scale integration

• Wafer-scale integration was selected because 3D stacking supports only a few chips, while packaged PCB connections would make asynchronous differential transmission unfeasible and increase communication-circuit area and power.The approach had to solve both reticle interconnection and whole-wafer-to-system connection problems; eight HICANN dies fit on one reticle in the 180 nm process.Source: §4.2.1 · p. 22
• Post-processed multilayer wafer metallization connects neighboring HICANN reticles and redistributes wafer I/O and power lines to PCB contact stripes.The scheme uses a wafer-scale maskset with µm resolution and thick inner-area pads for wafer-to-PCB connection.Source: §4.2.1 · p. 22
• The wafer-scale L1 interconnect uses 5×5µm2 pad windows, 15×15µm2 copper areas, and an 8.4µm pitch with staggered contacts.The post-processing process was reliable down to a 6 µm pitch, but the design used a relaxed pitch because higher density was unnecessary.Source: §4.2.1 · p. 22

4.3 Wafer module

• The module uses 48 communication subgroups around the wafer and 48 1Gbit/s Ethernet links to connect with the host compute cluster.Each subgroup provides LVDS and JTAG signals for one reticle, while the links use an industrial-standard Ethernet switch hierarchy.Source: §4.3 · p. 23
• Four IO boards provide the Ethernet links, with twelve RJ45 connectors visible on each board and additional connectors reserved for future wafer-to-wafer networking.Only one IO board is shown in place in Figure 9 to avoid obstructing the communication subgroups.Source: §4.3 · p. 23

4.3.1 Wafer-PCB connection

• The HICANN wafer connects to the main PCB through mirrored post-processed contact stripes measuring 1.2 mm wide with a 400 µm pitch.The contact array is formed on the wafer, with a corresponding mirror image on the main PCB.Source: §4.3.1 · p. 23
• Elastomeric connectors with 5 conducting stripes per mm require only about 50 µm wafer-to-PCB alignment, achieved using an aluminum bracket, frame, and eight precision screws.The connectors are 1 mm wide and need not be precisely aligned individually to the wafer or PCB.Source: §4.3.1 · p. 23
• A slotted FR4 mask, optical alignment tool, and electrical-resistance monitoring position the connectors and optimize contact pressure before the bracket is sealed with nitrogen.The alignment tool corrects wafer-to-PCB placement during screw fastening, while resistance measurements monitor selected contacts.Source: §4.3.1 · p. 24

• The BrainScaleS system is designed to satisfy these combined requirements using the previously described BrainScaleS wafer module.Source: §4.4 · p. 24
• BrainScaleS integrates continuous-time analog neurons and synapses with programmable parameters, topology, per-synapse long-term plasticity, wafer-scale scalability, and accelerated operation.Source: §4.4 · p. 24
• Several-orders-of-magnitude timescale compression enables learning and development processes to be modeled in seconds instead of hours.The acceleration also supports parameter searches and statistical analysis across model types.Source: §4.4 · p. 24

5.1 The Dynap-SEL neuromorphic processor

• The processor contains four 16×16 analog-neuron cores and one plastic core with 64 neurons, on-chip learning circuits, and programmable synapses, using AER events for communication.All synaptic inputs are triggered by incoming Address Events, while neuron spikes are encoded into events routed to destinations.Source: §5.1 · p. 24

5.1.1 Dynap-SEL routing architecture

• Three hierarchical router levels provide intra-core, inter-core, and inter-chip communication through mixed source- and destination-address routing using TCAM and SRAM.R1 uses source-address routing, R2 uses absolute destination addresses in a 2D tree, and R3 uses relative destination coordinates; Figure 15 depicts this hierarchy.Source: §5.1.1 · p. 25, Figure 15 · p. 25
• Dynap-SEL supports arrays of up to 16×16 chips with all-to-all connectivity and direct communication to AER sensors and computing devices for large-scale sensory systems.Its modular programmable routers provide scalable connectivity without external mapping, memory, or computing support.Source: §5.1.1 · pp. 25–26

5.1.2 The plastic core

• The plastic core combines programmable plastic, non-plastic, and time-multiplexed linear synapses with spike-driven learning and configurable fan-in and fan-out.Merging synapse rows can provide up to 1k plastic and 512 non-plastic synapses per neuron, while event replication enables up to 8k destinations in principle.Source: §5.1.2 · pp. 26–27

5.2 Conclusion of the Dynap-SEL system

• Dynap-SEL scales by merging plastic cores from up to 4×4 chips, while reconfigurable routing tables support structural plasticity and evolutionary algorithms.Sixteen merged chips can form plastic cores with either 1k neurons and 128×1k plastic synapses or 128 neurons and 1k×128 plastic synapses.Source: §5.2 · p. 27
• By co-localizing computation with distributed memory and using multiple physical circuits for parallel processing, Dynap-SEL eliminates the von Neumann bottleneck by design.The architecture reduces memory-access power and bandwidth requirements, while emerging ReRAM technologies could further shrink the design and increase synapse and neuron density.Source: §5.1.1 · p. 26, §5.2 · p. 27

6 The 2DIFWTA chip: a 2D array of integrate-and-fire neurons for implementing cooperative-competitive networks

• The chip targets cooperative-competitive networks, where recurrent excitation and inhibition produce amplification, soft winner-take-all selection, signal restoration, and multi-stability.It supports computational analysis in both mean-rate and time domains through dedicated hardware for one 2D or multiple 1D networks.Source: §6 · pp. 28–29

6.1 Chip description

• The 32×64 array integrates 2048 I&F neurons, AER excitatory and inhibitory inputs, and configurable local excitation in 2D or 1D cooperative networks.The chip uses 0.35 µm four-metal CMOS technology and occupies about 15 mm2; competition is implemented flexibly through AER connectivity.Source: §6.1 · p. 29, Figure 18 · p. 29

6.2 Neuron (I&F) model

• Each neuron uses a compact leaky I&F circuit with spike-frequency adaptation, tunable refractory period, and voltage-threshold modulation to reduce power and communication demands.Adaptation models calcium-dependent after-hyperpolarization potassium currents, while refractory periods limit firing rates and adaptation reduces address-event bandwidth.Source: §6.2 · p. 30, Figure 20 · p. 31

6.3 Synapses

• The DPI synapse provides linear filtering that permits multiplexing multiple spiking sources through one circuit when a shared time constant is acceptable.This compact implementation is used for both AER and local connections under the chip’s tight two-dimensional area constraints.Source: §6.3 · p. 31

6.4 Full neuron and local connectivity

• Independent AER, local, self-excitation, and neighbor-output blocks provide flexible connectivity for one 2D network or 32 one-dimensional networks of 64 neurons.LAT plus VERT1 connections implement 2D cooperation, whereas VERT1 plus VERT2 implement first- and second-neighbor cooperation; all synaptic blocks can be independently enabled or disabled.Source: Figure 19 · p. 30, §6.4 · pp. 31–32

6.5 Application

• The chip functions as a general-purpose neuron pool and has supported olfactory processing, function approximation, inference, auditory learning, biological perception models, and a real-time context-dependent visual task.The advanced visual application demonstrated systematic configuration of reliable finite-state-machine computation on spiking neural arrays [84]. Other studies used global inhibition, 1D networks,, axonal-delay distributions, auditory learning, cricket perception, and weakly electric fish latency coding.Source: §6.5 · p. 32

Architecture

• PARCA performs parallel weighted-sum computation and synaptic-weight updates in an RRAM crossbar using peripheral read and write circuits.Read mode computes matrix-vector products through conductance-weighted currents, while write mode changes conductance to implement gradient-descent or spike-based learning.Source: §7 · pp. 32–33, Figure 21 · p. 33

Read operation

• The architecture reads the entire RRAM array simultaneously, converts column currents into thresholded spikes or digital values, and retains digital communication between arrays.This avoids conventional row-by-row memory reads and accelerates weighted-sum computation.Source: §7 · pp. 32–33

Write operation

• Write updates encode x_iy_j through overlapping row pulses and column duty-cycle windows, with fixed-width, evenly distributed pulses reducing quantization error.The column pulse duty cycle follows the column neuron value, while the row pulse count follows the row neuron value.Source: §7 · p. 33

Implementations

• Experimental crossbars ranged from 12×12 to 500×661, while a fabricated 64×64 RRAM 1T1R core integrated CMOS neurons in a 130 nm process for binary neural networks.The core time-multiplexed column neurons to reduce area and sequentially read different columns.Source: §7 · pp. 33–34

Non-idealities and mitigation

• ~95 % recognition accuracy was restored by circuit- and architecture-level mitigation of device non-idealities, at penalties in area, power, and latency.Strategies included dummy columns, more linear programming, multi-cell averaging, and wider wires to reduce IR drop,.Source: §7 · p. 35

8.5 Potential directions of channel model computation

• Channel-model physical computation is positioned as a route to energy-efficient analog and neuromorphic systems for cortical structures, embedded applications, classification, and learning.Mead’s physical-computation hypothesis estimated at least 1000× lower energy than digital computation, and such estimates were experimentally demonstrated multiple times.Source: §8 · p. 35, §8.5 · p. 42, Figure 30 · p. 42

8.1 Transistor-channel models of neural systems

• MOSFET channel models reproduce biological channel dynamics in dense circuits, with a spiking action-potential circuit requiring six transistors and modeling Hodgkin–Huxley and voltage-clamp behavior.The approach uses analogous gating physics and voltage differences between biological and silicon channels.Source: §8.1 · p. 36, Figure 24 · p. 36

8.2 Long-term analog memories: Dense silicon synapse models

• Floating-gate synapses provide nonvolatile weight storage, biological PSP generation, and LTP, LTD, and STDP learning in a single transistor device.The learning circuitry can be placed at array edges, preserving synaptic-matrix area; devices retain 7-10 bits across 100s of quantization levels, even at 10 nm.Source: §8.2 · pp. 36–37, Figure 25 · p. 37

8.3 Neuromorphic IC of somas and learning synapses

• The configurable neuromorphic IC combines mesh or crossbar synapses, programmable multi-channel somas, AER communication, and local WTA feedback, while floating-gate approaches improve synaptic density.The implementation supports 10,000 STDP synapses in recurrent connections, 10,000 STDP synapses from AER, and 10,000 programmable excitatory or inhibitory synapses from AER.Source: §8.3 · pp. 37–38, Figure 26 · p. 38, Table 4 · p. 39
• 100% correct and optimal performance was demonstrated across many randomized maze scenarios using a realistic-neuron IC that propagates a goal-initiated wavefront through programmable grid connections.The planner’s analytical time and space complexity metrics were also verified experimentally.Source: §8.3 · p. 39, Figure 27 · p. 40

8.4 Reconfigurable neuromorphic ICs of dendrites, learning synapses, and somas

• Reconfigurable channel-model ICs implement dense dendritic compartments, active and passive channels, programmable somas, and sparse or dense routing through FPAA-like architectures.Dendritic structures support localized learning and can interface with off-chip devices through address-event senders and receivers.Source: §8.4 · pp. 40–41, Figure 28 · p. 40
• Dendritic computation can be 1000s of times more efficient than most analog signal-processing algorithms while supporting word spotting through approximate HMM-like classifier structures.The framework demonstrated temporal classification of YES-NO and NO-YES word sequences.Source: Figure 29 · p. 41, §8.4 · p. 42

9.1 Neurogrid

• Neurogrid models soma, dendritic trees, synapses, and axonal arbors across 1 M neurons using 16 sub-threshold analog neurocores, with the board consuming roughly 3 W [118].Each neurocore contains 65k neurons and consumes approximately 150 mW.Source: §9.1 · p. 43

9.2 TrueNorth

• TrueNorth integrates 1 million digital neurons across 4096 cores per die, while a 16-chip NS16e board consumes 1 W at 1 KHz.Each core contains 256 neurons and 256 synapses per neuron; a single die consumes 72 mW.Source: §9.2 · p. 43

9.3 SpiNNaker

• SpiNNaker targets scalable, energy-efficient neural simulation and event-based processing using nodes with 18 ARM968 cores and 16,000 digital neurons consuming 1 W per node.Its largest 48-node board supports 768,000 neurons and consumes 80 W.Source: §9.3 · p. 43

• The systems span mixed-signal, digital, analog, FPGA, wafer-scale, multicore, crossbar, and reconfigurable designs, supporting low power, dense integration, real-time scale, learning, and nonlinear computation.Deep South simulates 20 million to 2.6 billion LIF neurons in real time, while BrainScaleS uses wafer-scale integration and programmable analog parameters.Source: §10 · pp. 43–44
• Application-specific strengths include 2DIFWTA for winner-take-all processing, Dynap-SEL for on-chip learning, and user-friendly programming interfaces in Neurogrid, SpiNNaker, DeepSouth, and TrueNorth.Dynap-SEL also supports general-purpose neuron arrays and combines resources across chips through memory-optimized routing.Source: §10 · p. 44
• Simulator selection depends on constraints: IFAT, PARCA, and transistor-channel systems target low power; BrainScaleS and HiAER-IFAT target high speed; software, application, or learning needs favor other systems.BrainScaleS reaches 10,000× biological real-time speed, while low-power approaches may sacrifice speed or accuracy.Source: §10 · p. 44, Table 5 · p. 45
• Biological resemblance varies across systems: Neurogrid and transistor-channel designs most closely reproduce physical neuron properties, while digital approaches can improve robustness but may increase area and power.Many systems nevertheless emulate prominent spiking behaviors beyond integrate-and-fire, including IFAT, BrainScaleS, TrueNorth, and SpiNNaker.Source: §10 · p. 44
• Table 5 compares the event-based neural processors, whose unique architectures provide complementary capabilities rather than establishing one universally superior system.The assessment is intended to compare systems, not deem one inferior to another.Source: §10 · pp. 43, 45, Table 5 · p. 45