DAMO: Deep Agile Mask Optimization for Full Chip Scale

1 Introduction

• Earlier OPC methods required costly lithography simulation, while learning-based approaches were limited by low resolution and a focus on single clips rather than full chips.The paper also cites dataset limitations and low wafer-pattern fidelity as barriers to learning-based full-chip mask optimization.Source: §1 · pp. 1–2
• DAMO combines high-resolution GANs, a Deep Lithography Simulator, and a Deep Mask Generator in an end-to-end OPC framework for full-chip layouts.The DMG is trained with correction gradients back-propagated from the DLS, and stitchless splitting supports full-chip processing with few GPUs.Source: §1 · p. 2
• DAMO reports 5× speed-up for single-clip OPC and 1.3× acceleration for full-chip OPC versus Calibre, while maintaining better solution quality.Source: §1 · p. 2
• The authors identify DCGAN-HD, DLS and DMG, and stitchless full-chip splitting as contributions, and describe the paper's subsequent sections.DCGAN-HD is designed for 1024 × 1024 inputs; the splitting algorithm is intended to apply DAMO to layouts of any size.Source: §1 · p. 2

2.1 cGAN Basis

• A conditional GAN (cGAN) uses generator inputs and outputs linked by constraints, building on the generator-discriminator structure of classical GANs.Source: §2.1 · p. 2

2.2 Problem Formulation

• Mask quality is evaluated using squared L2 error under nominal conditions and PV Band for robustness across process variations.Squared L2 error compares design and wafer images; PV Band is the area among lithography contours across process conditions.Source: §2.2 · p. 2
• Mask optimization seeks a mask whose post-lithography patterns are close to the design, minimizing PV Band and squared L2 error.Source: §2.2 · p. 2

3 DAMO Framework

• DAMO's DLS predicts lithography contours, while its DMG shares the DLS architecture and learns mask generation using gradients back-propagated from the pretrained DLS.Source: §3 · pp. 2–3

3.1 Improving Accuracy by Higher Resolution

• DAMO uses 1024 × 1024-pixel inputs to preserve layout precision that lower-resolution OPC images can lose, and pairs this resolution with window splitting for layouts of any size.At 256 × 256 pixels, a prior 1000 × 1000 nm² layout representation made a one-pixel shift equivalent to 8 nm.Source: §3.1 · p. 3

3.2 DCGAN-HD: Solution for High Resolution

• DCGAN-HD is a high-resolution conditional GAN designed to address unstable adversarial training, with a redesigned generator, multi-scale discriminators, and a novel adversarial loss.Source: §3.1 · p. 3, §3.2 · p. 3

3.2.1 High-resolution Generator for DCGAN-HD.

• The generator uses a modified UNet++ backbone with redesigned skip pathways and nine residual blocks to support low-level feature extraction and identity-like mapping.The paper notes that OPC requires preserving shape and relative-distance information in design and SRAF patterns.Source: §3.2.1 · p. 3

3.2.2 Multi-scale Discriminators for DCGAN-HD.

• Two discriminators operate at 1024 × 1024 and 512 × 512 scales; using only the larger-scale discriminator is an option for one-via windows to reduce over-fitting and training time.The design addresses failures of a simple discriminator when windows contain five or six vias.Source: §3.2.2 · pp. 3–4

3.2.3 Perceptual Losses.

• Perceptual loss compares high-level CNN representations rather than pixels, avoiding pixel-loss sensitivity to small shifts and blur while targeting wafer quality reflected in L2 error and PV Band.Source: §3.2.3 · p. 4

4 Data preparation and training

• The training-data pipeline generates unlimited examples, enabling full use of DCGAN-HD for lithography simulation and mask-pattern generation.DAMO’s overall training is divided into two parts.Source: §4 · p. 4

4.1 Building Training Set from Scratch

• Training images are built through five steps, while balanced via-pattern densities and enlarged SRAF clips address sampling bias and patterns outside the design window.Calibre-generated mask-wafer pairs train DLS; centrally cropping 2048 × 2048-pixel images to 1024 × 1024 pixels focuses mask generation and reduces computation.Source: §4.1 · p. 4

4.2 Training of DLS

• DLS learns to predict wafer images from paired mask-wafer examples using adversarial training and a perceptual-loss term.Its objective uses multiple discriminators and a pre-trained VGG19 feature network.Source: §4.2 · pp. 4–5

4.3 Training of DAMO

• DAMO trains DLS first, freezes its generator, then trains DMG on design-mask-wafer pairs and back-propagates DLS perceptual-loss gradients to guide mask generation.The combined objective bridges generated wafer images and target via patterns, allowing DAMO to optimize masks directly.Source: §4.3 · p. 5

5 Full-chip Splitting Algorithm

• Coarse-to-fine splitting extends DAMO from 1024 × 1024 nm² clips to industrial full-chip layouts with randomly distributed vias and varying local densities.The method skips empty areas, and DBSCAN scans the via patterns once.Source: §5 · p. 6
• DBSCAN first groups dense via neighborhoods; KMeans++ then finds cluster-centered 1024 × 1024 nm² windows, producing the full-chip split.Each fine cluster must fit within the maximum via count per window, and every via must fall within the split windows.Source: §5 · p. 6
• The clustering avoids overlapping windows and stitching errors because each design pattern belongs to a fine cluster.Centering windows on cluster centroids places via patterns near the window centers, reducing the model’s search space and the required training data and time.Source: §5 · p. 6

6.1 Dataset

• 16,035 design patterns were split into 11,649 windows, and 52.5% of those windows contained one via.Figure 6 shows the full-chip layout and splitting windows, alongside the via-window distribution.Source: §6.1 · p. 6, Figure 6 · p. 7

6.2 Implementation Details

• Training used four TITAN Xp GPUs, batch size 4, and 100 epochs; evaluation used mIoU, pixAcc, L2 error, and PV Band.Generated masks were converted to GDSII and validated through Calibre lithography simulation.Source: §6.2 · pp. 6–7

6.3 Effectiveness of DLS

• 98.68% mIoU followed replacing L1 loss with perceptual loss; DLS also handles multiple vias per clip, unlike LithoGAN.The cGAN baseline reached 94.16% mIoU, while the original UNet++ generator reached 93.98%; the high-resolution generator and multi-scale discriminator stages each report 97.63%.Source: §6.3 · p. 7, Table 1 · p. 7

6.4 Performance of DAMO

• Across epochs 20–100, DAMO wafer patterns progress from lower quality than Calibre to surpassing it after iterative optimization.Figure 7 visualizes this progression on the via layer.Source: §6.4 · p. 7, Figure 7 · p. 7
• On validation sets, DAMO has 2.7× less L2 error and 1.3× less PV Band than GAN-OPC, and beats Calibre on both while achieving 4× speed-up.GAN-OPC’s 1024×1024 inputs were downsampled to 256×256 for training and its outputs upsampled for testing.Source: §6.4 · p. 7, Table 2 · p. 8

6.5 Results on ISPD 2019 Full-chip Layout

• On ISPD 2019, DAMO outperforms Calibre and GAN-OPC across split-window L2, PV Band, and runtime; its split-window metric sums remain close to full-chip results.Full-chip runtime was 4,395 s for preparation and 231.5 s for inference.Source: §6.5 · pp. 7–8, Table 3 · p. 8, Figure 8 · p. 8

• DAMO targets full-chip mask optimization with high-resolution generative machine-learning models.Source: §7 · p. 8
• Its DLS provides precise lithography prediction and enables efficient DMG training for manufacturing-friendly masks without costly fine-tuning.Source: §7 · p. 8
• DAMO's advantage over representative industrial and academic state-of-the-art demonstrates the possibility of deep neural networks as an alternative for layout and mask optimization.Source: §7 · p. 8
• Future research includes deployment on more complicated designs, such as metal layers, and transferability as technology nodes advance.Source: §7 · p. 8