MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning

1 Introduction

• Placement must minimize metrics including power, timing, area, and wirelength while meeting hard density and routing-congestion constraints.Wirelength is linked to delay and power, but reducing it by overlapping modules violates the density constraint.Source: §1 · p. 1
• Classic optimization methods relax hard constraints, so DREAMPlace may produce overlaps and require legalization that can increase wirelength or fail to find a feasible solution.The cited text identifies manual refinement and legalization as post-processing steps for removing overlaps.Source: §1 · p. 2
• Prior RL methods represent netlists as hypergraphs, but omit pin offsets or require heavy computation to encode them, while reduced placement scope or resolution sacrifices performance.Graph Placement places 15% of modules with RL; DeepPR reduces module and canvas resolution.Source: §1 · p. 2
• MaskPlace learns pixel-level visual representations of circuit modules and uses a policy network to aggregate global and subtle canvas information for efficient placement.The approach targets macro placement and can generate valid layouts within a few hours, unlike prior methods requiring manual refinement.Source: §1 · p. 3
• Across 24 public benchmarks, MaskPlace always produces layouts with 0% overlap and reduces wirelength up to 5× versus Graph Placement and 9× versus DeepPR.Figure 1 also shows MaskPlace with the lowest HPWL, wirelength, and overlap area ratio among the four illustrated approaches on bigblue3.Source: Figure 1 · p. 2, §1 · p. 3

2 Preliminary and Notation

• HPWL estimates wirelength by summing the half-perimeters of each net’s bounding box, with each half-perimeter equal to the box’s height plus width.For the illustrated example, the total is h1 + w1 + h2 + w2.Source: §2 · p. 3
• A valid layout requires congestion below a desired threshold and zero overlap between modules.Congestion is estimated with the RUDY estimator; overlap measures overlapping regions between pairs of modules.Source: §2 · pp. 3–4
• Figure 2 contrasts pixel-level placement masks with a hypergraph representation that loses pin-location information.Its position mask marks feasible locations and placed modules, while lighter wire-mask values indicate shorter wirelength.Source: Figure 2 · p. 4
• MaskPlace avoids explicitly calculating the O(V^2) density metric during training by ensuring non-overlapping placement.The text identifies pairwise overlap-density calculation as time-consuming.Source: §2 · p. 4

Model Architecture Overview

• The policy network turns pixel-level features into placement probabilities, while the value network evaluates the state using global features and the current module’s positional embedding.The policy uses a convolutional encoder-decoder, and the value network uses an embedding model.Source: §3 · pp. 4–6

Position Mask

• The position mask marks feasible canvas locations for the current module, supporting non-overlapping placement and learning the relationship between placement and wirelength.The mask is a binary matrix on a 224 × 224 canvas grid.Source: §3 · p. 4

Wire Mask

• The wire mask encodes each candidate position’s increase in HPWL, including pin offsets, so the policy can seek placements with smaller wirelength increases.The described fast calculation reduces complexity from O(N^2P) to O(NP).Source: §3 · p. 5

View Mask

• The view mask records occupied cells using actual module sizes, rather than assuming every module has unit size.A module of size w × h covers ⌈wN/W⌉ × ⌈hN/H⌉ canvas cells.Source: §3 · p. 5

Reinforcement Learning

• The policy and value networks are trained with actor-critic PPO2, using HPWL as a dense reward based on its change after each placement.The step reward is HPWL_t−1 − HPWL_t, and bounding-box ranges can be maintained with O(P) cost.Source: §3 · p. 6

Training and Testing

• At test time, a congestion satisfaction block checks sampled actions against a threshold and selects a final action that meets the constraint when possible.If sampled actions cannot meet the threshold, it selects the action with minimal congestion.Source: §3 · p. 6

Main Results

• MaskPlace achieves the lowest wirelength in six of seven benchmarks, while conventional optimization methods may fail on high-area-usage circuits such as ariane.The comparison uses five random seeds for learning-based methods and reports means and variances.Source: §4 · pp. 6–7, Table 2 · p. 7

Compare to Graph Representation

• Compared with Graph Placement, MaskPlace reduces HPWL by up to 80% in the ISPD benchmark while ensuring zero overlaps across all benchmarks.Soft constraints may improve HPWL and congestion, but can produce nonzero overlap area.Source: §4 · p. 7, Table 3 · p. 7, Table 4 · p. 8

Routing Wirelength

• MaskPlace achieves 60% to 90% shorter routing wirelength than DeepPR.The comparison attributes the result to using HPWL rather than true wirelength as the reward; true-wirelength reward lowers efficiency and produces sparse rewards.Source: §4 · p. 7, Table 5 · p. 8

Standard Cells

• On bigblue3, which has more than a million standard cells, MaskPlace surpasses the other approaches by up to 50%.The comparison reports HPWL for macros and standard cells.Source: §4 · pp. 7–8, Table 6 · p. 8

Additional Evaluations

• The experiments also evaluate MaskPlace without real module sizes and test transfer from a model trained on adaptec1, but the supplied passages report no quantitative outcomes for these tests.The text says the no-real-size setting has significant advantages and describes transferability as good, without giving the values.Source: §4 · p. 8, Table 7 · p. 8, Table 8 · p. 8

Efficiency

• MaskPlace is faster than the two other learning-based approaches in inference under the reported evaluation setup.All methods were evaluated on one GeForce RTX 3090 GPU; DREAMPlace's CPU version used 16 threads on a 16-core environment.Source: §4 · p. 8, Table 9 · p. 9

Ablation Study

• The standard MaskPlace configuration with curriculum learning performs best among the tested component variants on adaptec1.The ablation uses five seeds; tested variants include sparse reward, input masks, placement-order features, and local feature fusion kernels.Source: §4 · pp. 8–9, Figure 6 · p. 9

Congestion Satisfaction

• MaskPlace satisfies the congestion constraint across five seeds in a suitable range, but lowering the threshold increases HPWL and thresholds below about 40 are hard to satisfy on adaptec3.The authors attribute the lower-threshold difficulty to nets needing a minimum amount of wire resources.Source: §4 · p. 9

Conclusion

• MaskPlace uses rich visual representations that learn position, wirelength, and view information to guide placement actions without reducing the search space.The paper says its direct reward function is based on practical scenarios and reports satisfactory results on key metrics while avoiding undesired overlaps.Source: §5 · p. 9, Figure 7 · p. 9
• The method's demonstrated scope is one stage of chip design flow; placing millions of standard cells still requires an optimization method because RL's state space is too large.The authors identify suitable representations for RL-based standard-cell placement as future work.Source: §5 · p. 9

Checklist

• The checklist marks the main claims and limitations as discussed and the potential societal impacts as addressed.It also records conformity with ethics review guidelines.Source: Checklist · p. 12
• For experiments, the checklist marks reproduction materials, training details, error bars, and compute-resource reporting as included.Source: Checklist · p. 12
• The checklist marks citation of existing assets and release of new assets as complete, while personal-information and human-subject items are marked not applicable.Source: Checklist · p. 12

A.1 Module, Net and Pin

• MaskPlace is currently used for macro placement because standard cells are numerous, while placement methods usually place macros first to reserve enough space for them.Macros include DRAMs, caches, and IO interfaces; standard cells are mainly much smaller logical gates.Source: §A.1 · p. 13
• Pins are module input/output interfaces connected directly by wires, with fixed relative positions on their modules.Source: §A.1 · p. 13
• A net groups pins connected by the same wires; pins from a net form a bounding box, and usually each pin belongs to one net with more than two pins.Source: §A.1 · p. 13

A.2 Metric

• HPWL estimates wirelength as the sum of half-perimeters of net bounding boxes; it is an optimization objective, while congestion and density are constraints.HPWL is smaller-is-better, and congestion and density must remain below given thresholds.Source: §A.2 · pp. 13–14
• RUDY estimates congestion by accumulating 1/h + 1/w for net bounding boxes covering each grid cell, then using the maximum cell value or the average of the top k values.The method uses RUDY because rough-routing-based congestion estimation is computationally intensive.Source: §A.2 · pp. 13–14
• Density is the maximum stackable coverage-area ratio over grid cells; a low density alone does not guarantee that placements have no overlaps.The method considers density in evaluation because its placement method ensures no overlaps.Source: §A.2 · p. 14

A.3 Algorithms

• The algorithms generate dense incremental HPWL rewards and efficiently construct position and wire masks for each module.Position masks use the widths, heights, and positions of previously placed modules; wire masks accumulate wirelength increases using net coordinates and pin offsets.Source: §A.3 · pp. 14–15

end

• The congestion-satisfaction procedure samples actions, evaluates congestion and wirelength, and selects an action meeting the threshold when possible.If no sampled action satisfies the threshold, it chooses the one with minimum congestion increase.Source: end · p. 16

A.4 Details of Model Architecture

• Table 10 contains the model architecture parameters, while Table 11 lists features used for pixel-level mask generation.Source: §A.4 · p. 17, Table 10 · p. 17, Table 11 · p. 17
• Table 12 presents a comparison of the features used for placement order across methods.Source: §A.4 · p. 17, Table 12 · p. 17

A.5 Training Configuration

• Table 13 contains the model configuration and hyperparameter settings.Source: §A.5 · p. 17, Table 13 · p. 18
• DREAMPlace, Graph Placement, and DeepPR are implemented using their open-source code with default settings.Source: §A.5 · p. 18

• Graph Placement places hard macros with RL and soft macros with a classic optimization method; MaskPlace places all macros with RL.Source: §A.6 · p. 18
• Ports are fixed, zero-size terminals connecting a circuit to external circuitry, and MaskPlace supports circuits with ports without modification.Source: §A.6 · p. 18
• Table 14 summarizes statistics for the different chip benchmarks.Source: Table 14 · p. 18

A.7 Supplementary Experiment

• MaskPlace achieves the lowest HPWL across the evaluated IBM benchmarks, where DREAMPlace places standard cells and MaskPlace places large macros.Table 15 identifies the comparison as HPWL for macro and standard-cell placement in the IBM benchmark.Source: §A.7 · pp. 18–19, Table 15 · p. 19
• MaskPlace achieves the best reported performance on the larger ISPD 2005 benchmark circuit bigblue4.Table 16 reports HPWL results for bigblue4; the supplied text does not state the individual values.Source: §A.7 · p. 19, Table 16 · p. 19
• In an adaptec1 comparison using HPWL, MaskPlace achieves the best performance in a few hours against Graph Placement and DeepPR.The methods were tested in the same environment; Figure 10 presents the search-time comparison.Source: §A.7 · p. 19, Figure 10 · p. 19

A.8 Detailed equation description of the model

• Given current state st, the method calculates position, wire, and view masks through m(·), then extracts a local feature and uses global mask encoder encη(·).The passage identifies gω(·) as a 1×1 convolutional neural network.Source: §A.8 · p. 20
• The model decodes global features to the action-space dimension, combines them with local features and a position mask, and uses the result to derive policy outputs.A transpose-convolutional network decodes global features; a 1×1 convolution merges features before the policy network.Source: §A.8 · p. 20

B Related Work

• Partitioning-based methods divide circuits to reduce inter-part connections, but isolated within-part optimization and difficult partitioning can limit them; simulated annealing is inefficient and sensitive to its random initial state.Source: B Related Work · p. 20
• Analytical methods offer strong classic placement quality, but quadratic methods use rough approximations and nonlinear methods can retain approximations and overlaps.Nonlinear methods can handle large-scale modules, but combining multiple metrics in one objective does not avoid overlaps.Source: B Related Work · p. 20
• Learning-assisted classic tools still depend heavily on those tools, while pure RL methods use graph representations that lose pin information and may allow overlaps; routing-wirelength rewards can also be sparse.DeepPR also ignores realistic module sizes; HPWL is described as a high-quality wirelength estimate with an inherent dense reward.Source: B Related Work · p. 21