Source-linked AI summary
BetterV: Controlled Verilog Generation with Discriminative Guidance
Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu
TL;DR
Modern IC complexity creates a need for automated circuit design, while Verilog generation remains constrained by limited domain resources and the demands of syntactic, functional, and downstream-task correctness. BetterV combines processed-data instruct-tuning, Verilog–C alignment, augmentation, and task-specific generative discriminators; it reports strong Verilog generation, surpasses GPT-4 on VerilogEval, and improves EDA downstream tasks. Its guidance currently requires token-level probabilities unavailable for closed-source models and adds computational overhead.
Problem
Complex IC design, limited Verilog resources, and insufficiently addressed syntactic, functional, and downstream-task requirements motivate more capable automated Verilog generation.
Method
BetterV fine-tunes LLMs on processed Verilog data using domain-specific instruction tuning and Verilog–C alignment, augments data, and uses task-specific generative discriminators to guide implementations.
Results
BetterV generates syntactically and functionally correct Verilog, surpasses GPT-4 on VerilogEval, and improves Verilog-related EDA downstream tasks.
Takeaways & Limitations
Task-specific discriminator guidance extends Verilog generation toward optimization of implementation performance across EDA downstream tasks.
Takeaways & Limitations
Closed-source models remain limited because BetterV requires token-level probabilities, and the discriminator introduces non-negligible computational overhead.
Abstract
from arXiv · showhide
Due to the growing complexity of modern Integrated Circuits (ICs), there is a need for automated circuit design methods. Recent years have seen rising research in hardware design language generation to facilitate the design process. In this work, we propose a Verilog generation framework, BetterV, which fine-tunes the large language models (LLMs) on processed domain-specific datasets and incorporates generative discriminators for guidance on particular design demands. The Verilog modules are collected, filtered and processed from internet to form a clean and abundant dataset. Instruct-tuning methods are specially designed to fine-tune the LLMs to understand the knowledge about Verilog. Furthermore, data are augmented to enrich the training set and also used to train a generative discriminator on particular downstream task, which leads a guidance for the LLMs to optimize the Verilog implementation. BetterV has the ability to generate syntactically and functionally correct Verilog, which can outperform GPT-4 on the VerilogEval benchmark. With the help of task-specific generative discriminator, BetterV can achieve remarkable improvement on various electronic design automation (EDA) downstream tasks, including the netlist node reduction for synthesis and verification runtime reduction with Boolean Satisfiability (SAT) solving.
1. Introduction
BetterV addresses the difficulty of generating reliable Verilog for complex IC design by combining domain-specific instruction tuning, data augmentation, and task-specific generative discriminators. It reports syntactically and functionally correct generation and improvements on EDA downstream tasks.
- EDA supports IC design and analysis, but the slowing Moore’s law increases pressure to improve and automate its design flow.
- Writing HDL is time-consuming and bug-prone, while prior Verilog-generation work largely neglects direct syntactic or functional correctness and downstream EDA tasks.
- BetterV combines domain-specific instruct-tuning on processed datasets, data augmentation, and generative discriminators to optimize Verilog implementations for downstream tasks.
- BetterV is presented as the first downstream task-driven method for Verilog generation, using task-specific discriminator guidance for EDA optimization.
- 6.7B/7B-parameter BetterV models surpass GPT-4 on VerilogEval without prompt-engineering strategies while generating syntactically and functionally correct Verilog.
- BetterV uses data augmentation to provide Verilog implementations tailored to diverse specifications despite scarce Verilog resources.
2. Related Works
Related work covers LLM-based Verilog generation and controllable generation methods. BetterV builds on these directions by applying discriminator-guided control to downstream EDA optimization.
- LLM-based Verilog generation has attracted substantial attention as part of broader progress in code generation and hardware design research.
- Discriminator-guided controllable generation combines discriminators with generative LLMs to steer outputs toward desired classes or constraints.
- Prior controllable-generation methods include next-token discrimination, latent-state updates, generative discriminators, and contrastive guidance during decoding.
3. Algorithm
BetterV combines domain-specific instruct-tuning, augmented Verilog data, and task-specific generative discriminators to guide Verilog generation for downstream EDA objectives.
- Framework overview: BetterV constructs a customized dataset from open-source Verilog, filtering files and extracting modules and functions before training.The processing also checks licenses, removes auto-generated or unsuitable files, and produces Verilog-C and Verilog definition-body pairs.
- Domain-specific instruct-tuning: Domain-specific instruct-tuning maps Verilog to C and trains bidirectional Verilog-C translation alongside Verilog autocompletion.The C implementation serves as a functional description, while autocompletion teaches the model to complete module definitions.
- Data augmentation: Synthetic Verilog modules are generated from collected module heads, checked for syntactic correctness with EDA tools, and added to enrich the training data.The augmentation uses high-temperature generation to increase module diversity and filters modules containing syntax errors.
- Generative discriminator: The generative discriminator models desired and undesired attributes with control and anticontrol codes, then uses Bayes-rule token probabilities to guide generation.The discriminator is trained on class-conditional sequences and ranks or filters candidate next tokens before sampling.
- Downstream-task guidance: Task-specific augmented data lets BetterV train distinct discriminators that guide Verilog toward downstream constraints and reduce manual optimization loops.The framework is presented as a downstream task-driven method for Verilog generation with discriminator guidance for EDA objectives.
4. Experiments
BetterV is evaluated for functional and syntactic correctness, synthesis node reduction, verification-runtime reduction, and discriminator effects across EDA tasks. The experiments report that discriminator guidance improves circuit implementations for both synthesis and formal verification.
- Experimental setting: The framework fine-tunes generative LLMs and smaller generative discriminators, using CodeLlama-7B-Instruct and DeepSeek-Coder-6.7b-Instruct as generation models.TinyLlama and DeepSeek-Coder-1.3b-Instruct serve as discriminator models; CodeQwen1.5-7B-Chat is fine-tuned directly.
- Experimental setting: BetterV is evaluated on VerilogEval functional correctness using pass@k, with downstream-task correctness measured by Yosys tools and n = 20 completions per problem.The downstream experiments use k = 1,5,10, while the functional-correctness evaluation follows VerilogEval’s simulation-based metric.
- Synthesis nodes reduction: 46.52% fewer nodes than the reference and 31.68% fewer than BetterV-base are achieved after discriminator-guided synthesis optimization.The node count is measured on synthesized And-Inverter-Graph netlists using Yosys commands.
- Verification runtime reduction: 22.45% less verification time than the reference and 13.99% less than BetterV-base are achieved with discriminator-guided SAT-runtime optimization.SAT solving is measured with Yosys commands that prove circuit assertions over 100 time steps.
- Discriminator impact: Discriminator guidance further improves functional correctness for both fine-tuned BetterV models and original pretrained CodeLlama models.The discriminator labels generated modules according to functional equivalence checked with Yosys eqy.
- Discriminator impact: BetterV achieves over 99 pass@10 for syntactic correctness, while discriminator guidance improves pass@1 by 7.6 for CodeLlama-7B-Instruct and 4.5 for BetterV-base.Syntactic correctness is determined by whether Yosys can compile the generated module using the prep command.
5. Discussion
BetterV improves Verilog generation and enables generative-discriminator gains on Verilog-related EDA downstream tasks. Its scope is limited by closed-source model access requirements and discriminator overhead.
- BetterV achieves remarkable performance on Verilog generation and improves Verilog-related EDA downstream tasks through generative discriminator guidance.
- Closed-source models remain limited because guidance generation requires access to token-level probabilities.
- The generative discriminator adds non-negligible computational overhead despite using only a small model.
- BetterV’s instruct-tuning and generative discriminators may extend to structured languages such as SQL, LaTeX, and XML where precision and correctness are required.
6. Conclusion
BetterV introduces a framework for controlling Verilog implementations and optimizing circuit performance across EDA tasks. It combines processed domain-specific data, instruct-tuning, data augmentation, and task-specific generative discriminators, achieving state-of-the-art capability across various tasks.
- BetterV controls Verilog implementations and optimizes circuit performance across multiple aspects of the EDA flow.
- The framework combines processed Verilog data, domain-specific instruct-tuning, data augmentation, and task-specific generative discriminators.
- BetterV achieves state-of-the-art capability on various tasks and provides a direction for PPA optimization and faster verification.